Fixed setting of SYSCLK when derived from divided HSI16

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15744 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

os/hal/ports/STM32/STM32G0xx/hal_lld.c

@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2022 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -74,7 +74,7 @@ const halclkcfg_t hal_clkcfg_reset = {
 #else
   .pwr_cr2              = 0U,
 #endif
-  .rcc_cr               = RCC_CR_HSION,
+  .rcc_cr               = RCC_CR_HSION | STM32_HSIDIV,
   .rcc_cfgr             = RCC_CFGR_SW_HSI,
   .rcc_pllcfgr          = 0U,
   .flash_acr            = STM32_FLASH_ACR_RESET
@@ -90,7 +90,7 @@ const halclkcfg_t hal_clkcfg_default = {
 #else
   .pwr_cr2              = 0U,
 #endif
-  .rcc_cr               = 0U
+  .rcc_cr               = STM32_HSIDIV
 #if STM32_HSI16_ENABLED
                         | RCC_CR_HSIKERON | RCC_CR_HSION
 #endif
@@ -127,6 +127,7 @@ const halclkcfg_t hal_clkcfg_default = {
  */
 static halfreq_t clock_points[CLK_ARRAY_SIZE] = {
   [CLK_SYSCLK]      = STM32_SYSCLK,
+  [CLK_HSISYSCLK]   = STM32_HSISYSCLK,
   [CLK_PLLPCLK]     = STM32_PLL_P_CLKOUT,
   [CLK_PLLQCLK]     = STM32_PLL_Q_CLKOUT,
   [CLK_PLLRCLK]     = STM32_PLL_R_CLKOUT,
@@ -266,13 +267,16 @@ __STATIC_INLINE void hal_lld_set_static_clocks(void) {
   /* Clock-related settings (dividers, MCO etc).*/
   RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_PPRE | STM32_HPRE;
 
+  /* Set HSISYS divisor.*/
+  RCC->CR |= STM32_HSIDIV;
+
 #if STM32_RCC_HAS_CCIPR2
   /* CCIPR register initialization.*/
   RCC->CCIPR =  STM32_ADCSEL    | STM32_RNGDIV     | STM32_RNGSEL    |
                 STM32_TIM15SEL  | STM32_TIM1SEL    | STM32_LPTIM2SEL |
                 STM32_LPTIM1SEL | STM32_I2C2SEL    | STM32_I2C1SEL   |
-                STM32_CECSEL    | STM32_USART2SEL | STM32_USART1SEL |
+                STM32_CECSEL    | STM32_USART3SEL  | STM32_USART2SEL |
-                STM32_LPUART1SEL;
+                STM32_USART1SEL | STM32_LPUART2SEL | STM32_LPUART1SEL;
 
   /* CCIPR2 register initialization.*/
   RCC->CCIPR2 = STM32_USBSEL    | STM32_FDCANSEL  | STM32_I2S2SEL   |
@@ -282,8 +286,8 @@ __STATIC_INLINE void hal_lld_set_static_clocks(void) {
   RCC->CCIPR =  STM32_ADCSEL    | STM32_RNGDIV     | STM32_RNGSEL    |
                 STM32_TIM15SEL  | STM32_TIM1SEL    | STM32_LPTIM2SEL |
                 STM32_LPTIM1SEL | STM32_I2S1SEL    | STM32_I2C1SEL   |
-                STM32_CECSEL    | STM32_USART2SEL | STM32_USART1SEL |
+                STM32_CECSEL    | STM32_USART3SEL  | STM32_USART2SEL |
-                STM32_LPUART1SEL;
+                STM32_USART1SEL | STM32_LPUART2SEL | STM32_LPUART1SEL;
 #endif
 }
 
@@ -325,7 +329,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
   }
 
   /* HSISYS clock.*/
-  hsidiv = 1U << ((ccp->pwr_cr1 & RCC_CR_HSIDIV_Msk) >> RCC_CR_HSIDIV_Pos);
+  hsidiv = 1U << ((ccp->rcc_cr & RCC_CR_HSIDIV_Msk) >> RCC_CR_HSIDIV_Pos);
   hsisysclk = hsi16clk / hsidiv;
 
   /* HSE clock.*/

os/hal/ports/STM32/STM32G0xx/hal_lld.h

@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2022 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -221,6 +221,12 @@
 #define STM32_USART2SEL_HSI16   (2U << 2U)  /**< USART2 source is HSI16.    */
 #define STM32_USART2SEL_LSE     (3U << 2U)  /**< USART2 source is LSE.      */
 
+#define STM32_USART3SEL_MASK    (3U << 4U)  /**< USART3 mask.               */
+#define STM32_USART3SEL_PCLK    (0U << 4U)  /**< USART3 source is PCLK.     */
+#define STM32_USART3SEL_SYSCLK  (1U << 4U)  /**< USART3 source is SYSCLK.   */
+#define STM32_USART3SEL_HSI16   (2U << 4U)  /**< USART3 source is HSI16.    */
+#define STM32_USART3SEL_LSE     (3U << 4U)  /**< USART3 source is LSE.      */
+
 #define STM32_CECSEL_MASK       (1U << 6U)  /**< CEC mask.                  */
 #define STM32_CECSEL_HSI16DIV   (0U << 6U)  /**< CEC source is HSI16/448.   */
 #define STM32_CECSEL_LSE        (1U << 6U)  /**< CEC source is LSE.         */
@@ -231,6 +237,12 @@
 #define STM32_LPUART1SEL_HSI16  (2U << 10U) /**< LPUART1 source is HSI16.   */
 #define STM32_LPUART1SEL_LSE    (3U << 10U) /**< LPUART1 source is LSE.     */
 
+#define STM32_LPUART2SEL_MASK   (3U << 8U)  /**< LPUART2 mask.              */
+#define STM32_LPUART2SEL_PCLK   (0U << 8U)  /**< LPUART2 source is PCLK.    */
+#define STM32_LPUART2SEL_SYSCLK (1U << 8U)  /**< LPUART2 source is SYSCLK.  */
+#define STM32_LPUART2SEL_HSI16  (2U << 8U)  /**< LPUART2 source is HSI16.   */
+#define STM32_LPUART2SEL_LSE    (3U << 8U)  /**< LPUART2 source is LSE.     */
+
 #define STM32_I2C1SEL_MASK      (3U << 12U) /**< I2C1SEL mask.              */
 #define STM32_I2C1SEL_PCLK      (0U << 12U) /**< I2C1 source is PCLK.       */
 #define STM32_I2C1SEL_SYSCLK    (1U << 12U) /**< I2C1 source is SYSCLK.     */
@@ -690,6 +702,13 @@
 #define STM32_USART2SEL                     STM32_USART2SEL_SYSCLK
 #endif
 
+/**
+ * @brief   USART3 clock source.
+ */
+#if !defined(STM32_USART3SEL) || defined(__DOXYGEN__)
+#define STM32_USART3SEL                     STM32_USART3SEL_SYSCLK
+#endif
+
 /**
  * @brief   LPUART1 clock source.
  */
@@ -697,6 +716,13 @@
 #define STM32_LPUART1SEL                    STM32_LPUART1SEL_SYSCLK
 #endif
 
+/**
+ * @brief   LPUART2 clock source.
+ */
+#if !defined(STM32_LPUART2SEL) || defined(__DOXYGEN__)
+#define STM32_LPUART2SEL                    STM32_LPUART2SEL_SYSCLK
+#endif
+
 /**
  * @brief   CEC clock source.
  */
@@ -1415,9 +1441,27 @@
 #endif
 
 /**
- * @brief   USART3 frequency.
+ * @brief   USART3 clock frequency.
  */
-#define STM32_USART3CLK             hal_lld_get_clock_point(CLK_PCLK)
+#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
+#if (STM32_USART3SEL == STM32_USART3SEL_PCLK) || defined(__DOXYGEN__)
+  #define STM32_USART3CLK           hal_lld_get_clock_point(CLK_PCLK)
+
+#elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK
+  #define STM32_USART3CLK           hal_lld_get_clock_point(CLK_SYSCLK)
+
+#elif STM32_USART3SEL == STM32_USART3SEL_HSI16
+  #define STM32_USART3CLK           STM32_HSI16CLK
+
+#elif STM32_USART3SEL == STM32_USART3SEL_LSE
+  #define STM32_USART3CLK           STM32_LSECLK
+#else
+  #error "invalid source selected for USART3 clock"
+#endif
+
+#else
+  #define STM32_USART3CLK           hal_lld_get_clock_point(CLK_PCLK)
+#endif
 
 /**
  * @brief   UART4 frequency.
@@ -1429,6 +1473,11 @@
  */
 #define STM32_UART5CLK              hal_lld_get_clock_point(CLK_PCLK)
 
+/**
+ * @brief   UART6 frequency.
+ */
+#define STM32_UART6CLK              hal_lld_get_clock_point(CLK_PCLK)
+
 /**
  * @brief   LPUART1 clock frequency.
  */
@@ -1448,6 +1497,27 @@
   #error "invalid source selected for LPUART1 clock"
 #endif
 
+/**
+ * @brief   LPUART2 clock frequency.
+ */
+#if defined(STM32G0B1xx) || defined(STM32G0C1xx) || defined(__DOXYGEN__)
+#if (STM32_LPUART2SEL == STM32_LPUART2SEL_PCLK) || defined(__DOXYGEN__)
+  #define STM32_LPUART2CLK          hal_lld_get_clock_point(CLK_PCLK)
+
+#elif STM32_LPUART2SEL == STM32_LPUART2SEL_SYSCLK
+  #define STM32_LPUART2CLK          hal_lld_get_clock_point(CLK_SYSCLK)
+
+#elif STM32_LPUART2SEL == STM32_LPUART2SEL_HSI16
+  #define STM32_LPUART2CLK          STM32_HSI16CLK
+
+#elif STM32_LPUART2SEL == STM32_LPUART2SEL_LSE
+  #define STM32_LPUART2CLK          STM32_LSECLK
+
+#else
+  #error "invalid source selected for LPUART2 clock"
+#endif
+#endif
+
 /**
  * @brief   CEC clock frequency.
  */