From dc5964f59f591bffdbe875cea33b419000cd3568 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Tue, 16 Feb 2016 10:32:43 +0000 Subject: [PATCH] RT4 and NIL2 merged. All demos and test applications to be updated. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8901 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- .../STM32/NIL-STM32F746G-DISCOVERY/.cproject | 55 +++ demos/STM32/NIL-STM32F746G-DISCOVERY/.project | 95 +++++ demos/STM32/NIL-STM32F746G-DISCOVERY/Makefile | 216 ++++++++++ demos/STM32/NIL-STM32F746G-DISCOVERY/chconf.h | 276 +++++++++++++ ...-DISCOVERY (OpenOCD, Flash and Run).launch | 52 +++ .../STM32/NIL-STM32F746G-DISCOVERY/halconf.h | 381 +++++++++++++++++ demos/STM32/NIL-STM32F746G-DISCOVERY/main.c | 98 +++++ .../STM32/NIL-STM32F746G-DISCOVERY/mcuconf.h | 386 ++++++++++++++++++ demos/STM32/RT-STM32F746G-DISCOVERY/Makefile | 6 +- demos/STM32/RT-STM32F746G-DISCOVERY/chconf.h | 42 +- demos/STM32/RT-STM32F746G-DISCOVERY/main.c | 2 +- doc/rt/reports/STM32F746-216-GCC.txt | 65 ++- os/hal/osal/nil/osal.c | 4 +- os/hal/osal/nil/osal.h | 24 +- readme.txt | 15 +- 15 files changed, 1653 insertions(+), 64 deletions(-) create mode 100644 demos/STM32/NIL-STM32F746G-DISCOVERY/.cproject create mode 100644 demos/STM32/NIL-STM32F746G-DISCOVERY/.project create mode 100644 demos/STM32/NIL-STM32F746G-DISCOVERY/Makefile create mode 100644 demos/STM32/NIL-STM32F746G-DISCOVERY/chconf.h create mode 100644 demos/STM32/NIL-STM32F746G-DISCOVERY/debug/NIL-STM32F746G-DISCOVERY (OpenOCD, Flash and Run).launch create mode 100644 demos/STM32/NIL-STM32F746G-DISCOVERY/halconf.h create mode 100644 demos/STM32/NIL-STM32F746G-DISCOVERY/main.c create mode 100644 demos/STM32/NIL-STM32F746G-DISCOVERY/mcuconf.h diff --git a/demos/STM32/NIL-STM32F746G-DISCOVERY/.cproject b/demos/STM32/NIL-STM32F746G-DISCOVERY/.cproject new file mode 100644 index 000000000..e4ac15359 --- /dev/null +++ b/demos/STM32/NIL-STM32F746G-DISCOVERY/.cproject @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/STM32/NIL-STM32F746G-DISCOVERY/.project b/demos/STM32/NIL-STM32F746G-DISCOVERY/.project new file mode 100644 index 000000000..6f8ebf740 --- /dev/null +++ b/demos/STM32/NIL-STM32F746G-DISCOVERY/.project @@ -0,0 +1,95 @@ + + + NIL-STM32F746G-DISCOVERY + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/os/hal/boards/ST_STM32F746G_DISCOVERY + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/STM32/NIL-STM32F746G-DISCOVERY/Makefile b/demos/STM32/NIL-STM32F746G-DISCOVERY/Makefile new file mode 100644 index 000000000..850c7454b --- /dev/null +++ b/demos/STM32/NIL-STM32F746G-DISCOVERY/Makefile @@ -0,0 +1,216 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +# Startup files. +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/platform.mk +include $(CHIBIOS)/os/hal/boards/ST_STM32F746G_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/osal/nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/nil/nil.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). +include $(CHIBIOS)/test/nil/test.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/STM32F746xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/demos/STM32/NIL-STM32F746G-DISCOVERY/chconf.h b/demos/STM32/NIL-STM32F746G-DISCOVERY/chconf.h new file mode 100644 index 000000000..0a948883b --- /dev/null +++ b/demos/STM32/NIL-STM32F746G-DISCOVERY/chconf.h @@ -0,0 +1,276 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +#define _CHIBIOS_NIL_CONF_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Number of user threads in the application. + * @note This number is not inclusive of the idle thread which is + * Implicitly handled. + */ +#define CH_CFG_NUM_THREADS 3 + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timer settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @note This value together with the @p CH_CFG_ST_RESOLUTION + * option defines the maximum amount of time allowed for + * timeouts. + */ +#define CH_CFG_ST_FREQUENCY 50000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note Feature not currently implemented. + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_MUTEXES FALSE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note Feature not currently implemented. + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK TRUE + +/** + * @brief Debug option, parameters checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS TRUE + +/** + * @brief System assertions. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS TRUE + +/** + * @brief Stack check. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_STACK_CHECK TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System initialization hook. + */ +#if !defined(CH_CFG_SYSTEM_INIT_HOOK) || defined(__DOXYGEN__) +#define CH_CFG_SYSTEM_INIT_HOOK() { \ +} +#endif + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + */ +#define CH_CFG_THREAD_EXT_INIT_HOOK(tr) { \ + /* Add custom threads initialization code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ +} + +/** + * @brief System halt hook. + */ +#if !defined(CH_CFG_SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in nilcore.h). */ +/*===========================================================================*/ + +#define CORTEX_VTOR_INIT 0x00200000U + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/STM32/NIL-STM32F746G-DISCOVERY/debug/NIL-STM32F746G-DISCOVERY (OpenOCD, Flash and Run).launch b/demos/STM32/NIL-STM32F746G-DISCOVERY/debug/NIL-STM32F746G-DISCOVERY (OpenOCD, Flash and Run).launch new file mode 100644 index 000000000..6068cf8e3 --- /dev/null +++ b/demos/STM32/NIL-STM32F746G-DISCOVERY/debug/NIL-STM32F746G-DISCOVERY (OpenOCD, Flash and Run).launch @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/STM32/NIL-STM32F746G-DISCOVERY/halconf.h b/demos/STM32/NIL-STM32F746G-DISCOVERY/halconf.h new file mode 100644 index 000000000..dddc44db8 --- /dev/null +++ b/demos/STM32/NIL-STM32F746G-DISCOVERY/halconf.h @@ -0,0 +1,381 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/STM32/NIL-STM32F746G-DISCOVERY/main.c b/demos/STM32/NIL-STM32F746G-DISCOVERY/main.c new file mode 100644 index 000000000..423e62cc2 --- /dev/null +++ b/demos/STM32/NIL-STM32F746G-DISCOVERY/main.c @@ -0,0 +1,98 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" +#include "ch.h" +#include "ch_test.h" + +/* + * Blinker thread #1. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + + /* + * GPIOI1 is programmed as output (board LED). + */ + palClearLine(LINE_ARD_D13); + palSetLineMode(LINE_ARD_D13, PAL_MODE_OUTPUT_PUSHPULL); + + while (true) { + palSetLine(LINE_ARD_D13); + chThdSleepMilliseconds(500); + palClearLine(LINE_ARD_D13); + chThdSleepMilliseconds(500); + } +} + +/* + * Tester thread. + */ +THD_WORKING_AREA(waThread2, 128); +THD_FUNCTION(Thread2, arg) { + + (void)arg; + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* Welcome message.*/ + chnWrite(&SD1, (const uint8_t *)"Hello World!\r\n", 14); + + /* Waiting for button push and activation of the test suite.*/ + while (true) { + if (palReadLine(LINE_BUTTON_USER)) + test_execute((BaseSequentialStream *)&SD1); + chThdSleepMilliseconds(500); + } +} + +/* + * Threads static table, one entry per thread. The number of entries must + * match CH_CFG_NUM_THREADS. + */ +THD_TABLE_BEGIN + THD_TABLE_ENTRY(waThread1, "blinker1", Thread1, NULL) + THD_TABLE_ENTRY(wa_test_support, "test_support", test_support, (void *)&nil.threads[2]) + THD_TABLE_ENTRY(waThread2, "tester", Thread2, NULL) +THD_TABLE_END + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* This is now the idle thread loop, you may perform here a low priority + task but you must never try to sleep or wait in this loop. Note that + this tasks runs at the lowest priority level so any instruction added + here will be executed after all other tasks have been started.*/ + while (true) { + } +} diff --git a/demos/STM32/NIL-STM32F746G-DISCOVERY/mcuconf.h b/demos/STM32/NIL-STM32F746G-DISCOVERY/mcuconf.h new file mode 100644 index 000000000..8e6720728 --- /dev/null +++ b/demos/STM32/NIL-STM32F746G-DISCOVERY/mcuconf.h @@ -0,0 +1,386 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _MCUCONF_H_ +#define _MCUCONF_H_ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 25 +#define STM32_PLLN_VALUE 432 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 4 +#define STM32_PLLSAIR_VALUE 4 +#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK +#define STM32_SRAM2_NOCACHE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 250 +#define STM32_SDC_SDMMC_READ_TIMEOUT 25 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* _MCUCONF_H_ */ diff --git a/demos/STM32/RT-STM32F746G-DISCOVERY/Makefile b/demos/STM32/RT-STM32F746G-DISCOVERY/Makefile index 3d6f7eedb..4a8badb25 100644 --- a/demos/STM32/RT-STM32F746G-DISCOVERY/Makefile +++ b/demos/STM32/RT-STM32F746G-DISCOVERY/Makefile @@ -88,7 +88,7 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../.. # Startup files. -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk # HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/platform.mk @@ -96,7 +96,7 @@ include $(CHIBIOS)/os/hal/boards/ST_STM32F746G_DISCOVERY/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk # RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk # Other files (optional). include $(CHIBIOS)/test/rt/test.mk @@ -212,5 +212,5 @@ ULIBS = # End of user defines ############################################################################## -RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC include $(RULESPATH)/rules.mk diff --git a/demos/STM32/RT-STM32F746G-DISCOVERY/chconf.h b/demos/STM32/RT-STM32F746G-DISCOVERY/chconf.h index fe1c8d375..daebfe66e 100644 --- a/demos/STM32/RT-STM32F746G-DISCOVERY/chconf.h +++ b/demos/STM32/RT-STM32F746G-DISCOVERY/chconf.h @@ -28,6 +28,8 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ +#define _CHIBIOS_RT_CONF_ + /*===========================================================================*/ /** * @name System timers settings @@ -360,9 +362,16 @@ * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p CH_DBG_TRACE_MASK_NONE. */ -#define CH_DBG_ENABLE_TRACE FALSE +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_NONE + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_NONE. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 /** * @brief Debug option, stack checks. @@ -427,10 +436,6 @@ /** * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. */ #define CH_CFG_THREAD_EXIT_HOOK(tp) { \ /* Add threads finalization code here.*/ \ @@ -444,6 +449,20 @@ /* Context switch code here.*/ \ } +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + /** * @brief Idle thread enter hook. * @note This hook is invoked within a critical zone, no OS functions @@ -451,6 +470,7 @@ * @note This macro can be used to activate a power saving mode. */ #define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ } /** @@ -460,6 +480,7 @@ * @note This macro can be used to deactivate a power saving mode. */ #define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ } /** @@ -488,6 +509,15 @@ /* System halt code here.*/ \ } +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + /** @} */ /*===========================================================================*/ diff --git a/demos/STM32/RT-STM32F746G-DISCOVERY/main.c b/demos/STM32/RT-STM32F746G-DISCOVERY/main.c index eea6da024..9598a834b 100644 --- a/demos/STM32/RT-STM32F746G-DISCOVERY/main.c +++ b/demos/STM32/RT-STM32F746G-DISCOVERY/main.c @@ -71,7 +71,7 @@ int main(void) { * sleeping in a loop and check the button state. */ while (true) { - if (palReadPad(GPIOI, GPIOI_BUTTON_USER)) + if (palReadLine(LINE_BUTTON_USER)) TestThread(&SD1); chThdSleepMilliseconds(500); } diff --git a/doc/rt/reports/STM32F746-216-GCC.txt b/doc/rt/reports/STM32F746-216-GCC.txt index 472ca618c..158264aa5 100644 --- a/doc/rt/reports/STM32F746-216-GCC.txt +++ b/doc/rt/reports/STM32F746-216-GCC.txt @@ -1,8 +1,8 @@ *** ChibiOS/RT test suite *** -*** Kernel: 3.1.0 -*** Compiled: Jan 4 2016 - 11:31:27 +*** Kernel: 4.0.0 +*** Compiled: Feb 16 2016 - 11:13:58 *** Compiler: GCC 4.9.3 20150529 (release) [ARM/embedded-4_9-branch revision 227977] *** Architecture: ARMv7E-M *** Core Variant: Cortex-M7 @@ -83,72 +83,63 @@ --- Test Case 9.1 (Memory Pools, queue/dequeue) --- Result: SUCCESS ---------------------------------------------------------------------------- ---- Test Case 10.1 (Dynamic APIs, threads creation from heap) +--- Test Case 10.1 (Queues, input queues) --- Result: SUCCESS ---------------------------------------------------------------------------- ---- Test Case 10.2 (Dynamic APIs, threads creation from memory pool) +--- Test Case 10.2 (Queues, output queues) --- Result: SUCCESS ---------------------------------------------------------------------------- ---- Test Case 10.3 (Dynamic APIs, registry and references) +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 1079993 msgs/S, 2159986 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- ---- Test Case 11.1 (Queues, input queues) +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 959994 msgs/S, 1919988 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- ---- Test Case 11.2 (Queues, output queues) +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 959993 msgs/S, 1919986 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- ---- Test Case 12.1 (Benchmark, messages #1) ---- Score : 1074619 msgs/S, 2149238 ctxswc/S +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 4965488 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- ---- Test Case 12.2 (Benchmark, messages #2) ---- Score : 947361 msgs/S, 1894722 ctxswc/S +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 830762 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- ---- Test Case 12.3 (Benchmark, messages #3) ---- Score : 947361 msgs/S, 1894722 ctxswc/S +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 1148929 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- ---- Test Case 12.4 (Benchmark, context switch) ---- Score : 4909064 ctxswc/S +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 360455 reschedules/S, 2162730 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- ---- Test Case 12.5 (Benchmark, threads, full cycle) ---- Score : 717602 threads/S +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 2579080 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- ---- Test Case 12.6 (Benchmark, threads, create only) ---- Score : 1136835 threads/S +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 2522620 bytes/S --- Result: SUCCESS ---------------------------------------------------------------------------- ---- Test Case 12.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 349378 reschedules/S, 2096268 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 12.8 (Benchmark, round robin context switching) ---- Score : 2548660 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 12.9 (Benchmark, I/O Queues throughput) ---- Score : 2530008 bytes/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 12.10 (Benchmark, virtual timers set/reset) +--- Test Case 11.10 (Benchmark, virtual timers set/reset) --- Score : 2000026 timers/S --- Result: SUCCESS ---------------------------------------------------------------------------- ---- Test Case 12.11 (Benchmark, semaphores wait/signal) +--- Test Case 11.11 (Benchmark, semaphores wait/signal) --- Score : 3052996 wait+signal/S --- Result: SUCCESS ---------------------------------------------------------------------------- ---- Test Case 12.12 (Benchmark, mutexes lock/unlock) ---- Score : 2489904 lock+unlock/S +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 2482752 lock+unlock/S --- Result: SUCCESS ---------------------------------------------------------------------------- ---- Test Case 12.13 (Benchmark, RAM footprint) +--- Test Case 11.13 (Benchmark, RAM footprint) --- System: 336 bytes ---- Thread: 68 bytes +--- Thread: 64 bytes --- Timer : 20 bytes --- Semaph: 12 bytes --- EventS: 4 bytes diff --git a/os/hal/osal/nil/osal.c b/os/hal/osal/nil/osal.c index f1d8c5e2a..e33747149 100644 --- a/os/hal/osal/nil/osal.c +++ b/os/hal/osal/nil/osal.c @@ -73,7 +73,7 @@ void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg) { } tp++; - chDbgAssert(tp < &nil.threads[NIL_CFG_NUM_THREADS], + chDbgAssert(tp < &nil.threads[CH_CFG_NUM_THREADS], "pointer out of range"); } } @@ -97,7 +97,7 @@ void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg) { tp = nil.threads; while (cnt < (cnt_t)0) { - chDbgAssert(tp < &nil.threads[NIL_CFG_NUM_THREADS], + chDbgAssert(tp < &nil.threads[CH_CFG_NUM_THREADS], "pointer out of range"); /* Is this thread waiting on this semaphore?*/ diff --git a/os/hal/osal/nil/osal.h b/os/hal/osal/nil/osal.h index aac0d5e77..34249e74f 100644 --- a/os/hal/osal/nil/osal.h +++ b/os/hal/osal/nil/osal.h @@ -29,7 +29,7 @@ #include #include -#include "nil.h" +#include "ch.h" #if defined(__SPC5_HAL__) #include "platform.h" @@ -92,17 +92,17 @@ /** * @brief Size in bits of the @p systick_t type. */ -#define OSAL_ST_RESOLUTION NIL_CFG_ST_RESOLUTION +#define OSAL_ST_RESOLUTION CH_CFG_ST_RESOLUTION /** * @brief Required systick frequency or resolution. */ -#define OSAL_ST_FREQUENCY NIL_CFG_ST_FREQUENCY +#define OSAL_ST_FREQUENCY CH_CFG_ST_FREQUENCY /** * @brief Systick mode required by the underlying OS. */ -#if (NIL_CFG_ST_TIMEDELTA == 0) || defined(__DOXYGEN__) +#if (CH_CFG_ST_TIMEDELTA == 0) || defined(__DOXYGEN__) #define OSAL_ST_MODE OSAL_ST_MODE_PERIODIC #else #define OSAL_ST_MODE OSAL_ST_MODE_FREERUNNING @@ -117,8 +117,12 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if NIL_CFG_USE_EVENTS == FALSE -#error "OSAL requires NIL_CFG_USE_EVENTS=TRUE" +#if CH_CFG_USE_SEMAPHORES == FALSE +#error "OSAL requires CH_CFG_USE_SEMAPHORES=TRUE" +#endif + +#if CH_CFG_USE_EVENTS == FALSE +#error "OSAL requires CH_CFG_USE_EVENTS=TRUE" #endif #if !(OSAL_ST_MODE == OSAL_ST_MODE_NONE) && \ @@ -258,19 +262,17 @@ typedef struct { * * @api */ -#define osalDbgCheck(c) chDbgAssert(c, "parameter check") +#define osalDbgCheck(c) chDbgCheck(c) /** * @brief I-Class state check. - * @note Not implemented in this simplified OSAL. */ -#define osalDbgCheckClassI() /*chDbgCheckClassI()*/ +#define osalDbgCheckClassI() chDbgCheckClassI() /** * @brief S-Class state check. - * @note Not implemented in this simplified OSAL. */ -#define osalDbgCheckClassS() /*chDbgCheckClassS()*/ +#define osalDbgCheckClassS() chDbgCheckClassS() /** @} */ /** diff --git a/readme.txt b/readme.txt index 580444554..8de727a7a 100644 --- a/readme.txt +++ b/readme.txt @@ -34,6 +34,11 @@ | | +--index.html - Local documentation access (after rebuild). +--ext/ - External libraries, not part of ChibiOS/RT. +--os/ - ChibiOS components. + | +--common/ - Shared OS modules. + | +--common/ext/ - Vendor files used by the OS. + | +--common/oslib/ - RTOS modules usable by both RT and NIL. + | +--common/ports/ - RTOS ports usable by both RT and NIL. + | +--common/startup/ - Startup support for all compilers and platforms. | +--hal/ - HAL component. | | +--boards/ - HAL board support files. | | +--dox/ - HAL documentation resources. @@ -48,14 +53,12 @@ | | +--dox/ - NIL documentation resources. | | +--include/ - NIL high level headers. | | +--src/ - NIL high level source. - | | +--ports/ - NIL ports. - | | +--templates/ - NIL port template files. + | | +--templates/ - NIL configuration template files. | +--rt/ - RT RTOS component. | | +--dox/ - RT documentation resources. | | +--include/ - RT high level headers. | | +--src/ - RT high level source. - | | +--ports/ - RT ports. - | | +--templates/ - RT port template files. + | | +--templates/ - RT configuration template files. | +--various/ - Various portable support files. +--test/ - Kernel test suite source code. | +--lib/ - Portable test engine. @@ -73,6 +76,10 @@ ***************************************************************************** *** Next *** +- ALL: Reorganized source tree, now ports are shared between RT and NIL. +- RT: Merged RT4. +- NIL: Merged NIL2. +- NIL: Added STM32F7 demo. - RT: Removed the p_msg field from the thread_t structure saving a msg_t-sized field from the structure. Messages now use a new field into the p_u union. Now synchronous messages are even faster.