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Fixed bug #479. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6798 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2014-03-22 11:30:59 +00:00
parent e12b846cda
commit dc5d7d2592
4 changed files with 766 additions and 4 deletions
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380
os/hal/platforms/STM32/DACv1/dac_lld.c Normal file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32F37x/dac_lld.c
* @brief STM32F37x DAC subsystem low level driver source.
*
* @addtogroup DAC
* @{
*/
#include "ch.h"
#include "hal.h"
#if HAL_USE_DAC || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#if !defined(DAC1)
#define DAC1 DAC
#define rccEnableDAC1 rccEnableDAC
#define rccDisableDAC1 rccDisableDAC
#endif
#define DAC_CHN1_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_DAC_CHN1_DMA_STREAM, \
STM32_DAC_CHN1_DMA_CHN)
#define DAC_CHN2_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_DAC_CHN2_DMA_STREAM, \
STM32_DAC_CHN2_DMA_CHN)
#define DAC_CHN3_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_DAC_CHN3_DMA_STREAM, \
STM32_DAC_CHN3_DMA_CHN)
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/** @brief CHN1 driver identifier.*/
#if STM32_DAC_USE_CHN1 || defined(__DOXYGEN__)
DACDriver DACD1;
#endif
/** @brief CHN2 driver identifier.*/
#if STM32_DAC_USE_CHN2 || defined(__DOXYGEN__)
DACDriver DACD2;
#endif
/** @brief CHN3 driver identifier.*/
#if STM32_DAC_USE_CHN3 || defined(__DOXYGEN__)
DACDriver DACD3;
#endif
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief Shared end/half-of-tx service routine.
*
* @param[in] dacp pointer to the @p DACDriver object
* @param[in] flags pre-shifted content of the ISR register
*/
static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) {
#if defined(STM32_DAC_DMA_ERROR_HOOK)
(void)dacp;
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
/* DMA errors handling.*/
_dac_isr_error_code(dacp);
}
else {
if ((flags & STM32_DMA_ISR_HTIF) != 0) {
/* Half transfer processing.*/
_dac_isr_half_code(dacp);
}
if ((flags & STM32_DMA_ISR_TCIF) != 0) {
/* Transfer complete processing.*/
_dac_isr_full_code(dacp);
}
}
#else
(void)dacp;
(void)flags;
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level DAC driver initialization.
*
* @notapi
*/
void dac_lld_init(void) {
#if STM32_DAC_USE_CHN1
dacObjectInit(&DACD1);
DACD1.dac = DAC1;
DACD1.tim = STM32_TIM6;
DACD1.irqprio = STM32_DAC_CHN1_IRQ_PRIORITY;
DACD1.dma = STM32_DMA_STREAM(STM32_DAC_CHN1_DMA_STREAM);
DACD1.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN1_DMA_CHANNEL) | \
STM32_DMA_CR_PL(STM32_DAC_CHN1_DMA_PRIORITY) | \
STM32_DMA_CR_DIR_M2P | \
STM32_DMA_CR_DMEIE | \
STM32_DMA_CR_TEIE | \
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
#endif
#if STM32_DAC_USE_CHN2
dacObjectInit(&DACD2);
DACD2.dac = DAC1;
DACD2.tim = STM32_TIM7;
DACD2.irqprio = STM32_DAC_CHN2_IRQ_PRIORITY;
DACD2.dma = STM32_DMA_STREAM(STM32_DAC_CHN2_DMA_STREAM);
DACD2.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN2_DMA_CHANNEL) | \
STM32_DMA_CR_PL(STM32_DAC_CHN2_DMA_PRIORITY) | \
STM32_DMA_CR_DIR_M2P | \
STM32_DMA_CR_DMEIE | \
STM32_DMA_CR_TEIE | \
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
#endif
#if STM32_DAC_USE_CHN3
dacObjectInit(&DACD3);
DACD3.dac = DAC2;
DACD3.tim = STM32_TIM18;
DACD3.irqprio = STM32_DAC_CHN3_IRQ_PRIORITY;
DACD3.dma = STM32_DMA_STREAM(STM32_DAC_CHN3_DMA_STREAM);
DACD3.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN3_DMA_CHANNEL) | \
STM32_DMA_CR_PL(STM32_DAC_CHN2_DMA_PRIORITY) | \
STM32_DMA_CR_DIR_M2P | \
STM32_DMA_CR_DMEIE | \
STM32_DMA_CR_TEIE | \
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
#endif
}
/**
* @brief Configures and activates the DAC peripheral.
*
* @param[in] dacp pointer to the @p DACDriver object
*
* @notapi
*/
void dac_lld_start(DACDriver *dacp) {
uint32_t arr, regshift, trgo, dataoffset;
bool_t b;
/* If in stopped state then enables the DAC and DMA clocks.*/
if (dacp->state == DAC_STOP) {
#if STM32_DAC_USE_CHN1
if (&DACD1 == dacp) {
rccEnableDAC1(FALSE);
/* DAC1 CR data is at bits 0:15 */
regshift = 0;
dataoffset = 0;
/* Timer setup */
rccEnableTIM6(FALSE);
rccResetTIM6();
trgo = STM32_DAC_CR_TSEL_TIM6;
}
#endif
#if STM32_DAC_USE_CHN2
if (&DACD2 == dacp) {
rccEnableDAC1(FALSE);
/* DAC2 CR data is at bits 16:31 */
regshift = 16;
dataoffset = &dacp->dac->DHR12R2 - &dacp->dac->DHR12R1;
/* Timer setup */
rccEnableTIM7(FALSE);
rccResetTIM7();
trgo = STM32_DAC_CR_TSEL_TIM7;
}
#endif
#if STM32_DAC_USE_CHN3
if (&DACD3 == dacp) {
rccEnableDAC2(FALSE);
/* DAC3 CR data is at bits 0:15 */
regshift = 0;
dataoffset = 0;
/* Timer setup */
rccEnableTIM18(FALSE);
rccResetTIM18();
trgo = STM32_DAC_CR_TSEL_TIM18;
}
#endif
#if STM32_DAC_USE_CHN1 || STM32_DAC_USE_CHN2 || STM32_DAC_USE_CHN3
dacp->clock = STM32_TIMCLK1;
arr = (dacp->clock / dacp->config->frequency);
chDbgAssert((arr <= 0xFFFF),
"dac_lld_start(), #1", "invalid frequency");
/* Timer configuration.*/
dacp->tim->CR1 = 0; /* Initially stopped. */
dacp->tim->PSC = 0; /* Prescaler value. */
dacp->tim->DIER = 0;
dacp->tim->ARR = arr;
dacp->tim->EGR = TIM_EGR_UG; /* Update event. */
dacp->tim->CR2 &= (uint16_t)~TIM_CR2_MMS;
dacp->tim->CR2 |= (uint16_t)TIM_CR2_MMS_1; /* Enable TRGO updates. */
dacp->tim->CNT = 0; /* Reset counter. */
dacp->tim->SR = 0; /* Clear pending IRQs. */
/* Update Event IRQ enabled. */
/* Timer start.*/
dacp->tim->CR1 = TIM_CR1_CEN;
/* DAC configuration */
dacp->dac->CR |= ( (dacp->dac->CR & ~STM32_DAC_CR_MASK) | \
(STM32_DAC_CR_EN | STM32_DAC_CR_DMAEN | dacp->config->cr_flags) ) << regshift;
/* DMA setup. */
b = dmaStreamAllocate(dacp->dma,
dacp->irqprio,
(stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
(void *)dacp);
chDbgAssert(!b, "dac_lld_start(), #2", "stream already allocated");
switch (dacp->config->dhrm) {
/* Sets the DAC data register */
case DAC_DHRM_12BIT_RIGHT:
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12R1 + dataoffset);
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
break;
case DAC_DHRM_12BIT_LEFT:
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12L1 + dataoffset);
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
break;
case DAC_DHRM_8BIT_RIGHT:
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR8R1 + dataoffset);
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
break;
#if defined(STM32_HAS_DAC_CHN2) && STM32_HAS_DAC_CHN2
case DAC_DHRM_12BIT_RIGHT_DUAL:
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12RD);
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
break;
case DAC_DHRM_12BIT_LEFT_DUAL:
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12LD);
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
break;
case DAC_DHRM_8BIT_RIGHT_DUAL:
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR8RD);
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
break;
#endif
}
dacp->dac->CR |= trgo << regshift; /* Enable trigger */
#endif
}
}
/**
* @brief Deactivates the DAC peripheral.
*
* @param[in] dacp pointer to the @p DACDriver object
*
* @notapi
*/
void dac_lld_stop(DACDriver *dacp) {
/* If in ready state then disables the DAC clock.*/
if (dacp->state == DAC_READY) {
/* DMA disable.*/
dmaStreamRelease(dacp->dma);
#if STM32_DAC_USE_CHN1
if (&DACD1 == dacp) {
dacp->dac->CR &= ~STM32_DAC_CR_EN; /* DAC1 disable.*/
}
#endif
#if STM32_DAC_USE_CHN2
if (&DACD2 == dacp) {
dacp->dac->CR &= ~STM32_DAC_CR_EN << 16; /* DAC1 disable.*/
}
#endif
#if STM32_DAC_USE_CHN3
if (&DACD3 == dacp) {
dacp->dac->CR &= ~STM32_DAC_CR_EN; /* DAC2 disable.*/
rccDisableDAC2(FALSE); /* DAC Clock disable.*/
}
#endif
dacp->tim->CR1 &= ~TIM_CR1_CEN; /* Disable associated timer */
dacp->state = DAC_STOP;
if (!(DAC1->CR & (STM32_DAC_CR_EN | STM32_DAC_CR_EN << 16))) {
/* DAC Clock disable only if all channels are off.*/
rccDisableDAC1(FALSE);
}
}
}
/**
* @brief Sends data over the DAC bus.
* @details This asynchronous function starts a transmit operation.
* @post At the end of the operation the configured callback is invoked.
*
* @param[in] dacp pointer to the @p DACDriver object
* @param[in] n number of words to send
* @param[in] txbuf the pointer to the transmit buffer
*
* @notapi
*/
void dac_lld_send(DACDriver *dacp) {
chDbgAssert(dacp->config->buffer1, "dac_lld_send_doublebuffer(), #1",
"First buffer is NULL pointer");
dmaStreamSetMemory0(dacp->dma, dacp->config->buffer1);
dmaStreamSetTransactionSize(dacp->dma, dacp->config->buffers_size);
dmaStreamSetMode(dacp->dma, dacp->dmamode | STM32_DMA_CR_EN);
}
void dac_lld_send_continuous(DACDriver *dacp){
chDbgAssert(dacp->config->buffer1, "dac_lld_send_doublebuffer(), #1",
"First buffer is NULL pointer");
dmaStreamSetMemory0(dacp->dma, dacp->config->buffer1);
dmaStreamSetTransactionSize(dacp->dma, dacp->config->buffers_size);
dmaStreamSetMode(dacp->dma, dacp->dmamode | STM32_DMA_CR_EN | \
STM32_DMA_CR_CIRC);
}
#if defined(STM32_ADVANCED_DMA) && STM32_ADVANCED_DMA
void dac_lld_send_doublebuffer(DACDriver *dacp) {
chDbgAssert(dacp->config->buffer1, "dac_lld_send_doublebuffer(), #1",
"First buffer is NULL pointer");
chDbgAssert(dacp->config->buffer1, "dac_lld_send_doublebuffer(), #2",
"Second buffer is NULL pointer");
dmaStreamSetMemory0(dacp->dma, dacp->config->buffer1);
dmaStreamSetMemory1(dacp->dma, dacp->config->buffer2);
dmaStreamSetTransactionSize(dacp->dma, dacp->config->buffers_size);
dmaStreamSetMode(dacp->dma, dacp->dmamode | STM32_DMA_CR_EN | \
STM32_DMA_CR_DBM);
}
#else
void dac_lld_send_doublebuffer(DACDriver *dacp) {
(void)dacp;
chDbgAssert(0, "dac_lld_send_doublebuffer(), #1",
"This DMA mode is not supported by your hardware.");
};
#endif
#endif /* HAL_USE_DAC */
/** @} */

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os/hal/platforms/STM32/DACv1/dac_lld.h Normal file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32F37x/dac_lld.h
* @brief STM32F37x DAC subsystem low level driver header.
*
* @addtogroup DAC
* @{
*/
#ifndef _DAC_LLD_H_
#define _DAC_LLD_H_
#if HAL_USE_DAC || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
#define STM32_DAC_CR_EN DAC_CR_EN1
#define STM32_DAC_CR_DMAEN DAC_CR_DMAEN1
#define STM32_DAC_CR_TEN DAC_CR_TEN1
#define STM32_DAC_CR_MASK (uint32_t)0x00000FFE
#define STM32_DAC_CR_BOFF_ENABLE (uint32_t)0x00000000
#define STM32_DAC_CR_BOFF_DISABLE DAC_CR_BOFF1
#define STM32_DAC_CR_TSEL_NONE (uint32_t)0x00000000
#define STM32_DAC_CR_TSEL_TIM2 DAC_CR_TEN1 | DAC_CR_TSEL1_2
#define STM32_DAC_CR_TSEL_TIM4 DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_2
#define STM32_DAC_CR_TSEL_TIM5 DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_1
#define STM32_DAC_CR_TSEL_TIM6 DAC_CR_TEN1
#define STM32_DAC_CR_TSEL_TIM7 DAC_CR_TEN1 | DAC_CR_TSEL1_1
#define STM32_DAC_CR_TSEL_TIM3 DAC_CR_TEN1 | DAC_CR_TSEL1_0
#define STM32_DAC_CR_TSEL_TIM18 DAC_CR_TEN1 | DAC_CR_TSEL1_0 | DAC_CR_TSEL1_1
#define STM32_DAC_CR_TSEL_EXT_IT9 DAC_CR_TEN1 | DAC_CR_TEN1 | DAC_CR_TSEL1_2
#define STM32_DAC_CR_TSEL_SOFT DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_2
#define STM32_DAC_CR_WAVE_NONE (uint32_t)0x00000000
#define STM32_DAC_CR_WAVE_NOISE DAC_CR_WAVE1_0
#define STM32_DAC_CR_WAVE_TRIANGLE DAC_CR_WAVE1_1
#define STM32_DAC_MAMP_1 (uint32_t)0x00000000
#define STM32_DAC_MAMP_3 DAC_CR_MAMP1_0
#define STM32_DAC_MAMP_7 DAC_CR_MAMP1_1
#define STM32_DAC_MAMP_15 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1
#define STM32_DAC_MAMP_31 DAC_CR_MAMP1_2
#define STM32_DAC_MAMP_63 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_2
#define STM32_DAC_MAMP_127 DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
#define STM32_DAC_MAMP_255 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
#define STM32_DAC_MAMP_511 DAC_CR_MAMP1_3
#define STM32_DAC_MAMP_1023 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_3
#define STM32_DAC_MAMP_2047 DAC_CR_MAMP1_1 | DAC_CR_MAMP1_3
#define STM32_DAC_MAMP_4095 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief DAC1 driver enable switch.
* @details If set to @p TRUE the support for DAC1 is included.
* @note The default is @p TRUE.
*/
#if !defined(STM32_DAC_USE_DAC1) || defined(__DOXYGEN__)
#define STM32_DAC_USE_DAC1 FALSE
#endif
/**
* @brief DAC2 driver enable switch.
* @details If set to @p TRUE the support for DAC2 is included.
* @note The default is @p TRUE.
*/
#if !defined(STM32_DAC_USE_DAC2) || defined(__DOXYGEN__)
#define STM32_DAC_USE_DAC2 FALSE
#endif
/**
* @brief DAC1 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_DAC_DAC1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC1_DMA_PRIORITY 2
#endif
/**
* @brief DAC2 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_DAC_DAC2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC2_DMA_PRIORITY 2
#endif
/**
* @brief DAC1 interrupt priority level setting.
*/
#if !defined(STM32_DAC_DAC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC1_IRQ_PRIORITY 10
#endif
/**
* @brief DAC2 interrupt priority level setting.
*/
#if !defined(STM32_DAC_DAC2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC2_IRQ_PRIORITY 10
#endif
/**
* @brief DAC1 interrupt priority level setting.uhm
*/
#if !defined(STM32_DAC_DAC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC1_DMA_IRQ_PRIORITY 10
#endif
/**
* @brief DAC2 interrupt priority level setting.
*/
#if !defined(STM32_DAC_DAC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC2_DMA_IRQ_PRIORITY 10
#endif
/**
* @brief DMA stream used for DAC CHN1 TX operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_DAC_CHN1_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_DAC_CHN1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#endif
/**
* @brief DMA stream used for DAC CHN2 TX operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_DAC_CHN2_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_DAC_CHN2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#endif
/**
* @brief DMA stream used for DAC CHN3 TX operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_DAC_CHN3_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_DAC_CHN3_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if STM32_DAC_USE_CHN1 && !STM32_HAS_DAC_CHN1
#error "DAC CHN1 not present in the selected device"
#endif
#if STM32_DAC_USE_CHN2 && !STM32_HAS_DAC_CHN2
#error "DAC CHN2 not present in the selected device"
#endif
#if STM32_DAC_USE_CHN3 && !STM32_HAS_DAC_CHN3
#error "DAC CHN3 not present in the selected device"
#endif
#if !STM32_DAC_USE_CHN1 && !STM32_DAC_USE_CHN2 && !STM32_DAC_USE_CHN3
#error "DAC driver activated but no DAC peripheral assigned"
#endif
#if STM32_DAC_USE_CHN1 && \
!STM32_DMA_IS_VALID_ID(STM32_DAC_CHN1_DMA_STREAM, STM32_DAC_CHN1_DMA_MSK)
#error "invalid DMA stream associated to DAC CHN1"
#endif
#if STM32_DAC_USE_CHN2 && \
!STM32_DMA_IS_VALID_ID(STM32_DAC_CHN2_DMA_STREAM, STM32_DAC_CHN2_DMA_MSK)
#error "invalid DMA stream associated to DAC CHN2"
#endif
#if STM32_DAC_USE_CHN3 && \
!STM32_DMA_IS_VALID_ID(STM32_DAC_CHN3_DMA_STREAM, STM32_DAC_CHN3_DMA_MSK)
#error "invalid DMA stream associated to DAC CHN3"
#endif
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief Type of a structure representing an DAC driver.
*/
typedef struct DACDriver DACDriver;
/**
* @brief DAC notification callback type.
*
* @param[in] dacp pointer to the @p DACDriver object triggering the
* callback
*/
typedef void (*daccallback_t)(DACDriver *dacp);
typedef enum {
DAC_DHRM_12BIT_RIGHT = 0,
DAC_DHRM_12BIT_LEFT = 1,
DAC_DHRM_8BIT_RIGHT = 2,
#if defined(STM32_HAS_DAC_CHN2) && STM32_HAS_DAC_CHN2 && !defined(__DOXYGEN__)
DAC_DHRM_12BIT_RIGHT_DUAL = 3,
DAC_DHRM_12BIT_LEFT_DUAL = 4,
DAC_DHRM_8BIT_RIGHT_DUAL = 5
#endif
} dacdhrmode_t;
/**
* @brief Driver configuration structure.
*/
typedef struct {
/**
* @brief DAC mode selection.
*/
dacmode_t mode;
/**
* @brief Timer frequency in Hz.
*/
uint32_t frequency;
/**
* @brief Transmission buffer 1 pointer.
*/
const void *buffer1;
/**
* @brief Transmission buffer 2 pointer.
*/
const void *buffer2;
/**
* @brief Transmission buffers size in number of samples.
*/
size_t buffers_size;
/**
* @brief Operation complete callback or @p NULL.
*/
daccallback_t callback;
/**
* @brief Error handling callback or @p NULL.
*/
daccallback_t errcallback;
/* End of the mandatory fields.*/
/**
* @brief DAC data holding register mode.
*/
dacdhrmode_t dhrm;
/**
* @brief DAC initialization data.
*/
uint32_t cr_flags;
} DACConfig;
/**
* @brief Structure representing a DAC driver.
*/
struct DACDriver {
/**
* @brief Driver state.
*/
dacstate_t state;
/**
* @brief Current configuration data.
*/
const DACConfig *config;
#if DAC_USE_WAIT || defined(__DOXYGEN__)
/**
* @brief Waiting thread.
*/
Thread *thread;
#endif /* DAC_USE_WAIT */
#if DAC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
#if CH_USE_MUTEXES || defined(__DOXYGEN__)
/**
* @brief Mutex protecting the bus.
*/
Mutex mutex;
#elif CH_USE_SEMAPHORES
Semaphore semaphore;
#endif
#endif /* DAC_USE_MUTUAL_EXCLUSION */
#if defined(DAC_DRIVER_EXT_FIELDS)
DAC_DRIVER_EXT_FIELDS
#endif
/* End of the mandatory fields.*/
/**
* @brief Pointer to the DAC registers block.
*/
DAC_TypeDef *dac;
/**
* @brief Pointer to the TIMx registers block.
*/
stm32_tim_t *tim;
/**
* @brief The Timer IRQ priority.
*/
uint32_t irqprio;
/**
* @brief Transmit DMA stream.
*/
const stm32_dma_stream_t *dma;
/**
* @brief TX DMA mode bit mask.
*/
uint32_t dmamode;
/**
* @brief Timer base clock.
*/
uint32_t clock;
};
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if STM32_DAC_USE_CHN1 && !defined(__DOXYGEN__)
extern DACDriver DACD1;
#endif
#if STM32_DAC_USE_CHN2 && !defined(__DOXYGEN__)
extern DACDriver DACD2;
#endif
#if STM32_DAC_USE_CHN3 && !defined(__DOXYGEN__)
extern DACDriver DACD3;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void dac_lld_init(void);
void dac_lld_start(DACDriver *dacp);
void dac_lld_stop(DACDriver *dacp);
void dac_lld_send(DACDriver *dacp);
void dac_lld_send_continuous(DACDriver *dacp);
void dac_lld_send_doublebuffer(DACDriver *dacp);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_DAC */
#endif /* _DAC_LLD_H_ */
/** @} */

13
os/hal/platforms/STM32F37x/adc_lld.c
View File

@ -433,7 +433,7 @@ void adc_lld_start(ADCDriver *adcp) {
(void *)adcp);
chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &SDADC2->JDATAR);
rccEnableSDADC1(FALSE);
rccEnableSDADC2(FALSE);
PWR->CR |= PWR_CR_SDADC2EN;
adcp->sdadc->CR2 = 0;
adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
@ -450,7 +450,7 @@ void adc_lld_start(ADCDriver *adcp) {
(void *)adcp);
chDbgAssert(!b, "adc_lld_start(), #4", "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &SDADC3->JDATAR);
rccEnableSDADC1(FALSE);
rccEnableSDADC3(FALSE);
PWR->CR |= PWR_CR_SDADC3EN;
adcp->sdadc->CR2 = 0;
adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
@ -589,11 +589,16 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
adcp->sdadc->CONFCHR1 = grpp->u.sdadc.confchr[0];
adcp->sdadc->CONFCHR2 = grpp->u.sdadc.confchr[1];
/* SDADC trigger modes, this write must be performed when
SDADC_CR1_INIT=1.*/
adcp->sdadc->CR2 = cr2;
/* Leaving initialization mode.*/
adcp->sdadc->CR1 &= ~SDADC_CR1_INIT;
/* SDADC conversion start, the start is performed using the method
specified in the CR2 configuration, usually SDADC_CR2_JSWSTART.*/
/* Special case, if SDADC_CR2_JSWSTART is specified it has to be
written after SDADC_CR1_INIT has been set to zero. Just a write is
performed, any other bit is ingore if not in initialization mode.*/
adcp->sdadc->CR2 = cr2;
}
#endif /* STM32_ADC_USE_SDADC */

2
readme.txt
View File

@ -89,6 +89,8 @@
*****************************************************************************
*** 2.7.0 ***
- FIX: Fixed problem in STM32 SDADC driver initialization (bug #479)
(backported to 2.6.4).
- FIX: Fixed spurious callback in STM32 EXT driver (bug #477)(backported
to 2.6.4).
- FIX: Fixed several macro errors in STM32L1xx HAL driver (bug #476)