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ChibiOS
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More L4+ code. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12209 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
Giovanni Di Sirio 2018-07-28 10:07:34 +00:00
parent 8e9cc35969
commit dc86c1a9a2
5 changed files with 1224 additions and 9 deletions
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4
demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
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@ -90,8 +90,8 @@
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 TRUE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 TRUE
#define STM32_SERIAL_USE_LPUART1 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12

8
os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c
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@ -55,7 +55,7 @@
#define ST_ENABLE_CLOCK() rccEnableTIM2(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM2_STOP
#elif defined(STM32L4XX)
#elif defined(STM32L4XX) || defined(STM32L4XXP)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM2_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM2
@ -80,7 +80,7 @@
#define ST_ENABLE_CLOCK() rccEnableTIM3(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM3_STOP
#elif defined(STM32L4XX)
#elif defined(STM32L4XX) || defined(STM32L4XXP)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM3_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM3
@ -105,7 +105,7 @@
#define ST_ENABLE_CLOCK() rccEnableTIM4(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM4_STOP
#elif defined(STM32L4XX)
#elif defined(STM32L4XX) || defined(STM32L4XXP)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM4_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM4
@ -130,7 +130,7 @@
#define ST_ENABLE_CLOCK() rccEnableTIM5(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM5_STOP
#elif defined(STM32L4XX)
#elif defined(STM32L4XX) || defined(STM32L4XXP)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM5_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM5

17
os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c
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@ -39,6 +39,23 @@
#define USART_CR2_LBDIE 0
#endif
/* Differences in L4+ headers.*/
#if defined(USART_CR1_TXEIE_TXFNFIE)
#define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
#endif
#if defined(USART_CR1_RXNEIE_RXFNEIE)
#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
#endif
#if defined(USART_ISR_TXE_TXFNF)
#define USART_ISR_TXE USART_ISR_TXE_TXFNF
#endif
#if defined(USART_ISR_RXNE_RXFNE)
#define USART_ISR_RXNE USART_ISR_RXNE_RXFNE
#endif
/* STM32L0xx/STM32F7xx ST headers difference.*/
#if !defined(USART_ISR_LBDF)
#define USART_ISR_LBDF USART_ISR_LBD

4
os/hal/ports/STM32/STM32L4xx+/hal_lld.c
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@ -200,14 +200,12 @@ void stm32_clock_init(void) {
; /* Wait until HSI16 is stable. */
#endif
#if STM32_CLOCK_HAS_HSI48
#if STM32_HSI48_ENABLED
/* HSI activation.*/
RCC->CRRCR |= RCC_CRRCR_HSI48ON;
while ((RCC->CRRCR & RCC_CRRCR_HSI48RDY) == 0)
; /* Wait until HSI48 is stable. */
#endif
#endif
#if STM32_HSE_ENABLED
#if defined(STM32_HSE_BYPASS)
@ -339,7 +337,7 @@ void stm32_clock_init(void) {
/* CCIPR register initialization, note, must take care of the _OFF
pseudo settings.*/
{
uint32_t ccipr = STM32_DFSDMSEL | STM32_SWPMI1SEL | STM32_ADCSEL |
uint32_t ccipr = STM32_DFSDMSEL | STM32_ADCSEL |
STM32_CLK48SEL | STM32_LPTIM2SEL | STM32_LPTIM1SEL |
STM32_I2C3SEL | STM32_I2C2SEL | STM32_I2C1SEL |
STM32_UART5SEL | STM32_UART4SEL | STM32_USART3SEL |

1200
os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h Normal file
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