diff --git a/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c b/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c index a7efc9183..a217f68f7 100644 --- a/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c +++ b/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c @@ -31,7 +31,7 @@ /*===========================================================================*/ #if STM32_ADC_DUAL_MODE == TRUE -#define ADC12_CCR_DUAL ADC_CCR_DUAL_REG_SIMULT +#define ADC12_CCR_DUAL ADC_CCR_DUAL_REG_SIMULT #if STM32_ADC_SAMPLES_SIZE == 8 /* Compact type dual mode, 2x8-bit.*/ #define ADC12_DMA_SIZE (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD) @@ -46,7 +46,7 @@ #endif /* STM32_ADC_SAMPLES_SIZE == 8 */ #else /* STM32_ADC_DUAL_MODE == FALSE */ -#define ADC12_CCR_DUAL ADC_CCR_DUAL_INDEPENDENT +#define ADC12_CCR_DUAL ADC_CCR_DUAL_INDEPENDENT #if STM32_ADC_SAMPLES_SIZE == 8 /* Compact type single mode, 8-bit.*/ #define ADC12_DMA_SIZE (STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE) @@ -641,9 +641,9 @@ void adc_lld_start_conversion(ADCDriver *adcp) { adcp->adcm->ISR = adcp->adcm->ISR; /* If a callback is set enable the overflow and analog watch dog interrupts. */ if (grpp->error_cb != NULL) { - adcp->adcm->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE - | ADC_IER_AWD2IE - | ADC_IER_AWD3IE; + adcp->adcm->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE | + ADC_IER_AWD2IE | + ADC_IER_AWD3IE; } #if STM32_ADC_DUAL_MODE == TRUE && STM32_ADC_USE_ADC12 == TRUE /* Configuration for dual mode ADC12 */ @@ -652,9 +652,10 @@ void adc_lld_start_conversion(ADCDriver *adcp) { adcp->adcs->ISR = adcp->adcs->ISR; /* If a callback is set enable the overflow and analog watch dog interrupts. */ if (grpp->error_cb != NULL) { - adcp->adcs->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE - | ADC_IER_AWD2IE - | ADC_IER_AWD3IE; + adcp->adcs->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE | + ADC_IER_AWD2IE | + ADC_IER_AWD3IE; + /* Configuring the CCR register with the user-specified settings in the conversion group configuration structure, static settings are preserved.*/ diff --git a/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h b/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h index 433f5fbf2..5a8272dfc 100644 --- a/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h +++ b/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h @@ -199,7 +199,7 @@ /** * @brief Specifies the ADC samples width. * @note Must be 8, 16 or 32. - * @note 10, 12, 14 and 16 bits sampling modes must not be used when + * @note 10, 12, 14 and 16 bits sampling modes must not be used when * this option is set to 8. * @note 32 is useful when oversampling is activated. */ @@ -374,8 +374,8 @@ #error "Invalid IRQ priority assigned to ADC3" #endif -#if ((STM32_ADC_SAMPLES_SIZE != 8) && \ - (STM32_ADC_SAMPLES_SIZE != 16) && \ +#if ((STM32_ADC_SAMPLES_SIZE != 8) && \ + (STM32_ADC_SAMPLES_SIZE != 16) && \ (STM32_ADC_SAMPLES_SIZE != 32)) #error "STM32_ADC_SAMPLES_SIZE must be 8, 16 or 32" #endif diff --git a/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h b/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h index 16e35250e..1ef4969a5 100644 --- a/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h +++ b/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h @@ -254,7 +254,6 @@ #error "ADC DMA stream not defined" #endif - /* ADC clock source checks.*/ #if STM32_ADC_PRESCALER_VALUE == 2 #define STM32_ADC_PRESC 1U diff --git a/os/hal/ports/STM32/LLD/CRYPv1/hal_crypto_lld.c b/os/hal/ports/STM32/LLD/CRYPv1/hal_crypto_lld.c index b9d742e99..49720726b 100644 --- a/os/hal/ports/STM32/LLD/CRYPv1/hal_crypto_lld.c +++ b/os/hal/ports/STM32/LLD/CRYPv1/hal_crypto_lld.c @@ -1540,7 +1540,7 @@ cryerror_t cry_lld_SHA256_init(CRYDriver *cryp, SHA256Context *sha256ctxp) { sha256ctxp->last_size = 0U; /* Initializing operation.*/ - HASH->CR = /*HASH_CR_MDMAT |*/ HASH_CR_ALGO_1 | HASH_CR_ALGO_0 | + HASH->CR = /* HASH_CR_MDMAT |*/ HASH_CR_ALGO_1 | HASH_CR_ALGO_0 | HASH_CR_DATATYPE_1 | HASH_CR_INIT; return CRY_NOERROR; diff --git a/os/hal/ports/STM32/LLD/FDCANv1/hal_can_lld.c b/os/hal/ports/STM32/LLD/FDCANv1/hal_can_lld.c index 928c7e644..f0892870e 100644 --- a/os/hal/ports/STM32/LLD/FDCANv1/hal_can_lld.c +++ b/os/hal/ports/STM32/LLD/FDCANv1/hal_can_lld.c @@ -89,7 +89,6 @@ #define SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TMSA + \ (STM32_FDCAN_TM_NBR * SRAMCAN_TM_SIZE))) - #define TIMEOUT_INIT_MS 250U #define TIMEOUT_CSA_MS 250U @@ -389,7 +388,7 @@ void can_lld_transmit(CANDriver *canp, canmbx_t mailbox, const CANTxFrame *ctfp) /* Writing frame.*/ tx_address = canp->ram_base + ((SRAMCAN_TBSA + (put_index * SRAMCAN_TB_SIZE)) / sizeof (uint32_t)); - + *tx_address++ = ctfp->header32[0]; *tx_address++ = ctfp->header32[1]; for (unsigned i = 0U; i < dlc_to_bytes[ctfp->DLC]; i += 4U) { @@ -451,7 +450,7 @@ void can_lld_receive(CANDriver *canp, canmbx_t mailbox, CANRxFrame *crfp) { return; } } - + if (mailbox == 1U) { /* GET index RXF0, add it and the length to the rx_address.*/ get_index = (canp->fdcan->RXF0S & FDCAN_RXF0S_F0GI_Msk) >> FDCAN_RXF0S_F0GI_Pos; @@ -567,7 +566,7 @@ void can_lld_serve_interrupt(CANDriver *canp) { } /* Overflow events.*/ - if (((ir & FDCAN_IR_RF0L) != 0U) || ((ir & FDCAN_IR_RF1L) != 0U) ) { + if (((ir & FDCAN_IR_RF0L) != 0U) || ((ir & FDCAN_IR_RF1L) != 0U)) { _can_error_isr(canp, CAN_OVERFLOW_ERROR); } diff --git a/os/hal/ports/STM32/LLD/FDCANv1/hal_can_lld.h b/os/hal/ports/STM32/LLD/FDCANv1/hal_can_lld.h index 3a3bae1b9..081e79c5f 100644 --- a/os/hal/ports/STM32/LLD/FDCANv1/hal_can_lld.h +++ b/os/hal/ports/STM32/LLD/FDCANv1/hal_can_lld.h @@ -287,7 +287,6 @@ typedef struct { }; } CANRxStandardFilter; - /** * @brief CAN extended filter. * @note Accessing the frame data as word16 or word32 is not portable @@ -311,7 +310,6 @@ typedef struct { }; } CANRxExtendedFilter; - /** * @brief Type of a CAN configuration structure. */ diff --git a/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c b/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c index 16679c53a..c10fed90d 100644 --- a/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c +++ b/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c @@ -81,7 +81,7 @@ #define I2C_EV9_MASTER_ADD10 \ ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_ADD10)) - + #define I2C_EV5_MASTER_MODE_INVALID \ ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | (I2C_SR1_SB | \ I2C_SR1_STOPF))) @@ -284,7 +284,7 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) { break; case I2C_EV8_2_MASTER_BYTE_TRANSMITTED: /* Catches BTF event after the end of transmission.*/ - (void)dp->DR; /* clear BTF.*/ + (void)dp->DR; /* Clear BTF.*/ if (dmaStreamGetTransactionSize(i2cp->dmarx) > 0) { /* Starts "read after write" operation, LSB = 1 -> receive.*/ i2cp->addr |= 0x01; @@ -306,7 +306,7 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) { if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10)) (void)dp->SR2; - /* BERR flag doesn’t happen anymore in event handling */ + /* BERR flag doesn�t happen anymore in event handling */ #if 0 /* Errata 2.4.6 for STM32F40x, Spurious Bus Error detection in Master mode.*/ if (event & I2C_SR1_BERR) { diff --git a/os/hal/ports/STM32/LLD/MACv2/hal_mac_lld.c b/os/hal/ports/STM32/LLD/MACv2/hal_mac_lld.c index 1987973c1..454fdb918 100644 --- a/os/hal/ports/STM32/LLD/MACv2/hal_mac_lld.c +++ b/os/hal/ports/STM32/LLD/MACv2/hal_mac_lld.c @@ -279,7 +279,7 @@ OSAL_IRQ_HANDLER(STM32_ETH_HANDLER) { * @notapi */ void mac_lld_init(void) { - unsigned i,j; + unsigned i, j; macObjectInit(ÐD1); ETHD1.link_up = false; @@ -292,7 +292,7 @@ void mac_lld_init(void) { __eth_rd[i].rdes2 = 0; __eth_rd[i].rdes3 = STM32_RDES3_OWN | STM32_RDES3_IOC | STM32_RDES3_BUF1V; for (j = 0; j < BUFFER_SIZE; j++) { - __eth_rb[i][j] = 825373492; /* telltale "1234" */ + __eth_rb[i][j] = 825373492; /* Telltale "1234".*/ } } for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) { @@ -301,7 +301,7 @@ void mac_lld_init(void) { __eth_td[i].tdes2 = 0; __eth_td[i].tdes3 = 0; for (j = 0; j < BUFFER_SIZE; j++) { - __eth_tb[i][j] = 892745528; /* telltale "5678" */ + __eth_tb[i][j] = 892745528; /* Telltale "5678".*/ } } @@ -376,7 +376,7 @@ void mac_lld_start(MACDriver *macp) { /* MAC clocks activation and commanded reset procedure.*/ rccEnableETH(true); - + /* ISR vector enabled.*/ nvicEnableVector(STM32_ETH_NUMBER, STM32_MAC_ETH1_IRQ_PRIORITY); @@ -426,7 +426,6 @@ void mac_lld_start(MACDriver *macp) { ETH->DMACSR = ETH_DMACSR_NIS; ETH->DMACIER = ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE; - /* Check because errata on some devices. There should be no need to disable flushing because the TXFIFO should be empty on macStart().*/ #if !defined(STM32_MAC_DISABLE_TX_FLUSH) @@ -440,9 +439,8 @@ void mac_lld_start(MACDriver *macp) { ETH->MTLRQOMR = ETH_MTLRQOMR_DISTCPEF | ETH_MTLRQOMR_RSF; ETH->MTLTQOMR = ETH_MTLTQOMR_TSF; ETH->DMACTCR = ETH_DMACTCR_ST | ETH_DMACTCR_TPBL_1PBL; - ETH->DMACRCR = ETH_DMACRCR_SR | ETH_DMACRCR_RPBL_1PBL - | (STM32_MAC_BUFFERS_SIZE << ETH_DMACRCR_RBSZ_Pos - & ETH_DMACRCR_RBSZ); + ETH->DMACRCR = ETH_DMACRCR_SR | ETH_DMACRCR_RPBL_1PBL | + (STM32_MAC_BUFFERS_SIZE << ETH_DMACRCR_RBSZ_Pos & ETH_DMACRCR_RBSZ); } /** @@ -503,9 +501,9 @@ msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, return MSG_TIMEOUT; } - tdes->tdes0 = (uint32_t )__eth_tb[macp->tdindex]; - /* Marks the current descriptor as locked using a reserved bit.*/ - /*tdes->tdes0 |= STM32_TDES0_LOCKED; */ + tdes->tdes0 = (uint32_t)__eth_tb[macp->tdindex]; + /* Marks the current descriptor as locked using a reserved bit. + tdes->tdes0 |= STM32_TDES0_LOCKED; */ tdes->tdes1++; /* Next TX descriptor to use.*/ @@ -589,7 +587,7 @@ msg_t mac_lld_get_receive_descriptor(MACDriver *macp, && (rdes->rdes3 & STM32_RDES3_FD) && (rdes->rdes3 & STM32_RDES3_LD)) { /* Found a valid one.*/ rdp->offset = 0; - rdp->size = (rdes->rdes3 & STM32_RDES3_PL_MASK) -2; /* Lose CRC */ + rdp->size = (rdes->rdes3 & STM32_RDES3_PL_MASK) -2; /* Lose CRC.*/ rdp->physdesc = rdes; /* Reposition in ring.*/ macp->rdindex++; diff --git a/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c b/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c index 0f48d1fd0..126172599 100644 --- a/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c +++ b/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c @@ -510,12 +510,14 @@ static void otg_isoc_out_failed_handler(USBDriver *usbp) { for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) { if (((otgp->oe[ep].DOEPCTL & DOEPCTL_EPTYP_MASK) == DOEPCTL_EPTYP_ISO) && ((otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA) != 0)) { - /* Endpoint enabled -> ISOC OUT transfer failed */ - /* Disable endpoint */ +#if 0 + /* Endpoint enabled -> ISOC OUT transfer failed.*/ + /* Disable endpoint.*/ /* CHTODO:: Core stucks here */ - /*otgp->oe[ep].DOEPCTL |= (DOEPCTL_EPDIS | DOEPCTL_SNAK); + otgp->oe[ep].DOEPCTL |= (DOEPCTL_EPDIS | DOEPCTL_SNAK); while (otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA) - ;*/ + ; +#endif /* Prepare transfer for next frame.*/ _usb_isr_invoke_out_cb(usbp, ep); } @@ -1148,7 +1150,7 @@ void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { usbp->epc[ep]->out_maxsize; rxsize = (pcnt * usbp->epc[ep]->out_maxsize + 3U) & 0xFFFFFFFCU; - /*Setting up transaction parameters in DOEPTSIZ.*/ + /* Setting up transaction parameters in DOEPTSIZ.*/ usbp->otg->oe[ep].DOEPTSIZ = DOEPTSIZ_STUPCNT(3) | DOEPTSIZ_PKTCNT(pcnt) | DOEPTSIZ_XFRSIZ(rxsize); diff --git a/os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h b/os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h index 0ea731405..cb32d7e79 100644 --- a/os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h +++ b/os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h @@ -173,74 +173,74 @@ typedef struct { * @name GOTGCTL register bit definitions * @{ */ -#define GOTGCTL_BSVLD (1U<<19) /**< B-Session Valid. */ -#define GOTGCTL_ASVLD (1U<<18) /**< A-Session Valid. */ -#define GOTGCTL_DBCT (1U<<17) /**< Long/Short debounce time. */ -#define GOTGCTL_CIDSTS (1U<<16) /**< Connector ID status. */ -#define GOTGCTL_EHEN (1U<<12) -#define GOTGCTL_DHNPEN (1U<<11) /**< Device HNP enabled. */ -#define GOTGCTL_HSHNPEN (1U<<10) /**< Host Set HNP enable. */ -#define GOTGCTL_HNPRQ (1U<<9) /**< HNP request. */ -#define GOTGCTL_HNGSCS (1U<<8) /**< Host negotiation success. */ -#define GOTGCTL_BVALOVAL (1U<<7) -#define GOTGCTL_BVALOEN (1U<<6) -#define GOTGCTL_AVALOVAL (1U<<5) -#define GOTGCTL_AVALOEN (1U<<4) -#define GOTGCTL_VBVALOVAL (1U<<3) -#define GOTGCTL_VBVALOEN (1U<<2) -#define GOTGCTL_SRQ (1U<<1) /**< Session request. */ -#define GOTGCTL_SRQSCS (1U<<0) /**< Session request success. */ +#define GOTGCTL_BSVLD (1U << 19) /**< B-Session Valid. */ +#define GOTGCTL_ASVLD (1U << 18) /**< A-Session Valid. */ +#define GOTGCTL_DBCT (1U << 17) /**< Long/Short debounce time. */ +#define GOTGCTL_CIDSTS (1U << 16) /**< Connector ID status. */ +#define GOTGCTL_EHEN (1U << 12) +#define GOTGCTL_DHNPEN (1U << 11) /**< Device HNP enabled. */ +#define GOTGCTL_HSHNPEN (1U << 10) /**< Host Set HNP enable. */ +#define GOTGCTL_HNPRQ (1U << 9) /**< HNP request. */ +#define GOTGCTL_HNGSCS (1U << 8) /**< Host negotiation success. */ +#define GOTGCTL_BVALOVAL (1U << 7) +#define GOTGCTL_BVALOEN (1U << 6) +#define GOTGCTL_AVALOVAL (1U << 5) +#define GOTGCTL_AVALOEN (1U << 4) +#define GOTGCTL_VBVALOVAL (1U << 3) +#define GOTGCTL_VBVALOEN (1U << 2) +#define GOTGCTL_SRQ (1U << 1) /**< Session request. */ +#define GOTGCTL_SRQSCS (1U << 0) /**< Session request success. */ /** @} */ /** * @name GOTGINT register bit definitions * @{ */ -#define GOTGINT_DBCDNE (1U<<19) /**< Debounce done. */ -#define GOTGINT_ADTOCHG (1U<<18) /**< A-Device timeout change. */ -#define GOTGINT_HNGDET (1U<<17) /**< Host negotiation detected. */ -#define GOTGINT_HNSSCHG (1U<<9) /**< Host negotiation success +#define GOTGINT_DBCDNE (1U << 19) /**< Debounce done. */ +#define GOTGINT_ADTOCHG (1U << 18) /**< A-Device timeout change. */ +#define GOTGINT_HNGDET (1U << 17) /**< Host negotiation detected. */ +#define GOTGINT_HNSSCHG (1U << 9) /**< Host negotiation success status change. */ -#define GOTGINT_SRSSCHG (1U<<8) /**< Session request success +#define GOTGINT_SRSSCHG (1U << 8) /**< Session request success status change. */ -#define GOTGINT_SEDET (1U<<2) /**< Session end detected. */ +#define GOTGINT_SEDET (1U << 2) /**< Session end detected. */ /** @} */ /** * @name GAHBCFG register bit definitions * @{ */ -#define GAHBCFG_PTXFELVL (1U<<8) /**< Periodic TxFIFO empty +#define GAHBCFG_PTXFELVL (1U << 8) /**< Periodic TxFIFO empty level. */ -#define GAHBCFG_TXFELVL (1U<<7) /**< Non-periodic TxFIFO empty +#define GAHBCFG_TXFELVL (1U << 7) /**< Non-periodic TxFIFO empty level. */ -#define GAHBCFG_DMAEN (1U<<5) /**< DMA enable (HS only). */ -#define GAHBCFG_HBSTLEN_MASK (15U<<1) /**< Burst length/type mask (HS +#define GAHBCFG_DMAEN (1U << 5) /**< DMA enable (HS only). */ +#define GAHBCFG_HBSTLEN_MASK (15U << 1) /**< Burst length/type mask (HS only). */ -#define GAHBCFG_HBSTLEN(n) ((n)<<1) /**< Burst length/type (HS +#define GAHBCFG_HBSTLEN(n) ((n) << 1) /**< Burst length/type (HS only). */ -#define GAHBCFG_GINTMSK (1U<<0) /**< Global interrupt mask. */ +#define GAHBCFG_GINTMSK (1U << 0) /**< Global interrupt mask. */ /** @} */ /** * @name GUSBCFG register bit definitions * @{ */ -#define GUSBCFG_CTXPKT (1U<<31) /**< Corrupt Tx packet. */ -#define GUSBCFG_FDMOD (1U<<30) /**< Force Device Mode. */ -#define GUSBCFG_FHMOD (1U<<29) /**< Force Host Mode. */ -#define GUSBCFG_TRDT_MASK (15U<<10) /**< USB Turnaround time field +#define GUSBCFG_CTXPKT (1U << 31) /**< Corrupt Tx packet. */ +#define GUSBCFG_FDMOD (1U << 30) /**< Force Device Mode. */ +#define GUSBCFG_FHMOD (1U << 29) /**< Force Host Mode. */ +#define GUSBCFG_TRDT_MASK (15U << 10) /**< USB Turnaround time field mask. */ -#define GUSBCFG_TRDT(n) ((n)<<10) /**< USB Turnaround time field +#define GUSBCFG_TRDT(n) ((n) << 10) /**< USB Turnaround time field value. */ -#define GUSBCFG_HNPCAP (1U<<9) /**< HNP-Capable. */ -#define GUSBCFG_SRPCAP (1U<<8) /**< SRP-Capable. */ -#define GUSBCFG_PHYSEL (1U<<6) /**< USB 2.0 High-Speed PHY or +#define GUSBCFG_HNPCAP (1U << 9) /**< HNP-Capable. */ +#define GUSBCFG_SRPCAP (1U << 8) /**< SRP-Capable. */ +#define GUSBCFG_PHYSEL (1U << 6) /**< USB 2.0 High-Speed PHY or USB 1.1 Full-Speed serial transceiver Select. */ -#define GUSBCFG_TOCAL_MASK (7U<<0) /**< HS/FS timeout calibration +#define GUSBCFG_TOCAL_MASK (7U << 0) /**< HS/FS timeout calibration field mask. */ -#define GUSBCFG_TOCAL(n) ((n)<<0) /**< HS/FS timeout calibration +#define GUSBCFG_TOCAL(n) ((n) << 0) /**< HS/FS timeout calibration field value. */ /** @} */ @@ -248,102 +248,102 @@ typedef struct { * @name GRSTCTL register bit definitions * @{ */ -#define GRSTCTL_AHBIDL (1U<<31) /**< AHB Master Idle. */ -#define GRSTCTL_TXFNUM_MASK (31U<<6) /**< TxFIFO number field mask. */ -#define GRSTCTL_TXFNUM(n) ((n)<<6) /**< TxFIFO number field value. */ -#define GRSTCTL_TXFFLSH (1U<<5) /**< TxFIFO flush. */ -#define GRSTCTL_RXFFLSH (1U<<4) /**< RxFIFO flush. */ -#define GRSTCTL_FCRST (1U<<2) /**< Host frame counter reset. */ -#define GRSTCTL_HSRST (1U<<1) /**< HClk soft reset. */ -#define GRSTCTL_CSRST (1U<<0) /**< Core soft reset. */ +#define GRSTCTL_AHBIDL (1U << 31) /**< AHB Master Idle. */ +#define GRSTCTL_TXFNUM_MASK (31U << 6) /**< TxFIFO number field mask. */ +#define GRSTCTL_TXFNUM(n) ((n) << 6) /**< TxFIFO number field value. */ +#define GRSTCTL_TXFFLSH (1U << 5) /**< TxFIFO flush. */ +#define GRSTCTL_RXFFLSH (1U << 4) /**< RxFIFO flush. */ +#define GRSTCTL_FCRST (1U << 2) /**< Host frame counter reset. */ +#define GRSTCTL_HSRST (1U << 1) /**< HClk soft reset. */ +#define GRSTCTL_CSRST (1U << 0) /**< Core soft reset. */ /** @} */ /** * @name GINTSTS register bit definitions * @{ */ -#define GINTSTS_WKUPINT (1U<<31) /**< Resume/Remote wakeup +#define GINTSTS_WKUPINT (1U << 31) /**< Resume/Remote wakeup detected interrupt. */ -#define GINTSTS_SRQINT (1U<<30) /**< Session request/New session +#define GINTSTS_SRQINT (1U << 30) /**< Session request/New session detected interrupt. */ -#define GINTSTS_DISCINT (1U<<29) /**< Disconnect detected +#define GINTSTS_DISCINT (1U << 29) /**< Disconnect detected interrupt. */ -#define GINTSTS_CIDSCHG (1U<<28) /**< Connector ID status change.*/ -#define GINTSTS_PTXFE (1U<<26) /**< Periodic TxFIFO empty. */ -#define GINTSTS_HCINT (1U<<25) /**< Host channels interrupt. */ -#define GINTSTS_HPRTINT (1U<<24) /**< Host port interrupt. */ -#define GINTSTS_IPXFR (1U<<21) /**< Incomplete periodic +#define GINTSTS_CIDSCHG (1U << 28) /**< Connector ID status change.*/ +#define GINTSTS_PTXFE (1U << 26) /**< Periodic TxFIFO empty. */ +#define GINTSTS_HCINT (1U << 25) /**< Host channels interrupt. */ +#define GINTSTS_HPRTINT (1U << 24) /**< Host port interrupt. */ +#define GINTSTS_IPXFR (1U << 21) /**< Incomplete periodic transfer. */ -#define GINTSTS_IISOOXFR (1U<<21) /**< Incomplete isochronous OUT +#define GINTSTS_IISOOXFR (1U << 21) /**< Incomplete isochronous OUT transfer. */ -#define GINTSTS_IISOIXFR (1U<<20) /**< Incomplete isochronous IN +#define GINTSTS_IISOIXFR (1U << 20) /**< Incomplete isochronous IN transfer. */ -#define GINTSTS_OEPINT (1U<<19) /**< OUT endpoints interrupt. */ -#define GINTSTS_IEPINT (1U<<18) /**< IN endpoints interrupt. */ -#define GINTSTS_EOPF (1U<<15) /**< End of periodic frame +#define GINTSTS_OEPINT (1U << 19) /**< OUT endpoints interrupt. */ +#define GINTSTS_IEPINT (1U << 18) /**< IN endpoints interrupt. */ +#define GINTSTS_EOPF (1U << 15) /**< End of periodic frame interrupt. */ -#define GINTSTS_ISOODRP (1U<<14) /**< Isochronous OUT packet +#define GINTSTS_ISOODRP (1U << 14) /**< Isochronous OUT packet dropped interrupt. */ -#define GINTSTS_ENUMDNE (1U<<13) /**< Enumeration done. */ -#define GINTSTS_USBRST (1U<<12) /**< USB reset. */ -#define GINTSTS_USBSUSP (1U<<11) /**< USB suspend. */ -#define GINTSTS_ESUSP (1U<<10) /**< Early suspend. */ -#define GINTSTS_GONAKEFF (1U<<7) /**< Global OUT NAK effective. */ -#define GINTSTS_GINAKEFF (1U<<6) /**< Global IN non-periodic NAK +#define GINTSTS_ENUMDNE (1U << 13) /**< Enumeration done. */ +#define GINTSTS_USBRST (1U << 12) /**< USB reset. */ +#define GINTSTS_USBSUSP (1U << 11) /**< USB suspend. */ +#define GINTSTS_ESUSP (1U << 10) /**< Early suspend. */ +#define GINTSTS_GONAKEFF (1U << 7) /**< Global OUT NAK effective. */ +#define GINTSTS_GINAKEFF (1U << 6) /**< Global IN non-periodic NAK effective. */ -#define GINTSTS_NPTXFE (1U<<5) /**< Non-periodic TxFIFO empty. */ -#define GINTSTS_RXFLVL (1U<<4) /**< RxFIFO non-empty. */ -#define GINTSTS_SOF (1U<<3) /**< Start of frame. */ -#define GINTSTS_OTGINT (1U<<2) /**< OTG interrupt. */ -#define GINTSTS_MMIS (1U<<1) /**< Mode Mismatch interrupt. */ -#define GINTSTS_CMOD (1U<<0) /**< Current mode of operation. */ +#define GINTSTS_NPTXFE (1U << 5) /**< Non-periodic TxFIFO empty. */ +#define GINTSTS_RXFLVL (1U << 4) /**< RxFIFO non-empty. */ +#define GINTSTS_SOF (1U << 3) /**< Start of frame. */ +#define GINTSTS_OTGINT (1U << 2) /**< OTG interrupt. */ +#define GINTSTS_MMIS (1U << 1) /**< Mode Mismatch interrupt. */ +#define GINTSTS_CMOD (1U << 0) /**< Current mode of operation. */ /** @} */ /** * @name GINTMSK register bit definitions * @{ */ -#define GINTMSK_WKUM (1U<<31) /**< Resume/remote wakeup +#define GINTMSK_WKUM (1U << 31) /**< Resume/remote wakeup detected interrupt mask. */ -#define GINTMSK_SRQM (1U<<30) /**< Session request/New session +#define GINTMSK_SRQM (1U << 30) /**< Session request/New session detected interrupt mask. */ -#define GINTMSK_DISCM (1U<<29) /**< Disconnect detected +#define GINTMSK_DISCM (1U << 29) /**< Disconnect detected interrupt mask. */ -#define GINTMSK_CIDSCHGM (1U<<28) /**< Connector ID status change +#define GINTMSK_CIDSCHGM (1U << 28) /**< Connector ID status change mask. */ -#define GINTMSK_PTXFEM (1U<<26) /**< Periodic TxFIFO empty mask.*/ -#define GINTMSK_HCM (1U<<25) /**< Host channels interrupt +#define GINTMSK_PTXFEM (1U << 26) /**< Periodic TxFIFO empty mask.*/ +#define GINTMSK_HCM (1U << 25) /**< Host channels interrupt mask. */ -#define GINTMSK_HPRTM (1U<<24) /**< Host port interrupt mask. */ -#define GINTMSK_IPXFRM (1U<<21) /**< Incomplete periodic +#define GINTMSK_HPRTM (1U << 24) /**< Host port interrupt mask. */ +#define GINTMSK_IPXFRM (1U << 21) /**< Incomplete periodic transfer mask. */ -#define GINTMSK_IISOOXFRM (1U<<21) /**< Incomplete isochronous OUT +#define GINTMSK_IISOOXFRM (1U << 21) /**< Incomplete isochronous OUT transfer mask. */ -#define GINTMSK_IISOIXFRM (1U<<20) /**< Incomplete isochronous IN +#define GINTMSK_IISOIXFRM (1U << 20) /**< Incomplete isochronous IN transfer mask. */ -#define GINTMSK_OEPM (1U<<19) /**< OUT endpoints interrupt +#define GINTMSK_OEPM (1U << 19) /**< OUT endpoints interrupt mask. */ -#define GINTMSK_IEPM (1U<<18) /**< IN endpoints interrupt +#define GINTMSK_IEPM (1U << 18) /**< IN endpoints interrupt mask. */ -#define GINTMSK_EOPFM (1U<<15) /**< End of periodic frame +#define GINTMSK_EOPFM (1U << 15) /**< End of periodic frame interrupt mask. */ -#define GINTMSK_ISOODRPM (1U<<14) /**< Isochronous OUT packet +#define GINTMSK_ISOODRPM (1U << 14) /**< Isochronous OUT packet dropped interrupt mask. */ -#define GINTMSK_ENUMDNEM (1U<<13) /**< Enumeration done mask. */ -#define GINTMSK_USBRSTM (1U<<12) /**< USB reset mask. */ -#define GINTMSK_USBSUSPM (1U<<11) /**< USB suspend mask. */ -#define GINTMSK_ESUSPM (1U<<10) /**< Early suspend mask. */ -#define GINTMSK_GONAKEFFM (1U<<7) /**< Global OUT NAK effective +#define GINTMSK_ENUMDNEM (1U << 13) /**< Enumeration done mask. */ +#define GINTMSK_USBRSTM (1U << 12) /**< USB reset mask. */ +#define GINTMSK_USBSUSPM (1U << 11) /**< USB suspend mask. */ +#define GINTMSK_ESUSPM (1U << 10) /**< Early suspend mask. */ +#define GINTMSK_GONAKEFFM (1U << 7) /**< Global OUT NAK effective mask. */ -#define GINTMSK_GINAKEFFM (1U<<6) /**< Global non-periodic IN NAK +#define GINTMSK_GINAKEFFM (1U << 6) /**< Global non-periodic IN NAK effective mask. */ -#define GINTMSK_NPTXFEM (1U<<5) /**< Non-periodic TxFIFO empty +#define GINTMSK_NPTXFEM (1U << 5) /**< Non-periodic TxFIFO empty mask. */ -#define GINTMSK_RXFLVLM (1U<<4) /**< Receive FIFO non-empty +#define GINTMSK_RXFLVLM (1U << 4) /**< Receive FIFO non-empty mask. */ -#define GINTMSK_SOFM (1U<<3) /**< Start of (micro)frame mask.*/ -#define GINTMSK_OTGM (1U<<2) /**< OTG interrupt mask. */ -#define GINTMSK_MMISM (1U<<1) /**< Mode Mismatch interrupt +#define GINTMSK_SOFM (1U << 3) /**< Start of (micro)frame mask.*/ +#define GINTMSK_OTGM (1U << 2) /**< OTG interrupt mask. */ +#define GINTMSK_MMISM (1U << 1) /**< Mode Mismatch interrupt mask. */ /** @} */ @@ -351,66 +351,66 @@ typedef struct { * @name GRXSTSR register bit definitions * @{ */ -#define GRXSTSR_PKTSTS_MASK (15U<<17) /**< Packet status mask. */ -#define GRXSTSR_PKTSTS(n) ((n)<<17) /**< Packet status value. */ +#define GRXSTSR_PKTSTS_MASK (15U << 17) /**< Packet status mask. */ +#define GRXSTSR_PKTSTS(n) ((n) << 17) /**< Packet status value. */ #define GRXSTSR_OUT_GLOBAL_NAK GRXSTSR_PKTSTS(1) #define GRXSTSR_OUT_DATA GRXSTSR_PKTSTS(2) #define GRXSTSR_OUT_COMP GRXSTSR_PKTSTS(3) #define GRXSTSR_SETUP_COMP GRXSTSR_PKTSTS(4) #define GRXSTSR_SETUP_DATA GRXSTSR_PKTSTS(6) -#define GRXSTSR_DPID_MASK (3U<<15) /**< Data PID mask. */ -#define GRXSTSR_DPID(n) ((n)<<15) /**< Data PID value. */ -#define GRXSTSR_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ -#define GRXSTSR_BCNT(n) ((n)<<4) /**< Byte count value. */ -#define GRXSTSR_CHNUM_MASK (15U<<0) /**< Channel number mask. */ -#define GRXSTSR_CHNUM(n) ((n)<<0) /**< Channel number value. */ -#define GRXSTSR_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ -#define GRXSTSR_EPNUM(n) ((n)<<0) /**< Endpoint number value. */ +#define GRXSTSR_DPID_MASK (3U << 15) /**< Data PID mask. */ +#define GRXSTSR_DPID(n) ((n) << 15) /**< Data PID value. */ +#define GRXSTSR_BCNT_MASK (0x7FFU << 4) /**< Byte count mask. */ +#define GRXSTSR_BCNT(n) ((n) << 4) /**< Byte count value. */ +#define GRXSTSR_CHNUM_MASK (15U << 0) /**< Channel number mask. */ +#define GRXSTSR_CHNUM(n) ((n) << 0) /**< Channel number value. */ +#define GRXSTSR_EPNUM_MASK (15U << 0) /**< Endpoint number mask. */ +#define GRXSTSR_EPNUM(n) ((n) << 0) /**< Endpoint number value. */ /** @} */ /** * @name GRXSTSP register bit definitions * @{ */ -#define GRXSTSP_PKTSTS_MASK (15<<17) /**< Packet status mask. */ -#define GRXSTSP_PKTSTS(n) ((n)<<17) /**< Packet status value. */ +#define GRXSTSP_PKTSTS_MASK (15U << 17) /**< Packet status mask. */ +#define GRXSTSP_PKTSTS(n) ((n) << 17) /**< Packet status value. */ #define GRXSTSP_OUT_GLOBAL_NAK GRXSTSP_PKTSTS(1) #define GRXSTSP_OUT_DATA GRXSTSP_PKTSTS(2) #define GRXSTSP_OUT_COMP GRXSTSP_PKTSTS(3) #define GRXSTSP_SETUP_COMP GRXSTSP_PKTSTS(4) #define GRXSTSP_SETUP_DATA GRXSTSP_PKTSTS(6) -#define GRXSTSP_DPID_MASK (3U<<15) /**< Data PID mask. */ -#define GRXSTSP_DPID(n) ((n)<<15) /**< Data PID value. */ -#define GRXSTSP_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ +#define GRXSTSP_DPID_MASK (3U << 15) /**< Data PID mask. */ +#define GRXSTSP_DPID(n) ((n) << 15) /**< Data PID value. */ +#define GRXSTSP_BCNT_MASK (0x7FFU << 4) /**< Byte count mask. */ #define GRXSTSP_BCNT_OFF 4 /**< Byte count offset. */ -#define GRXSTSP_BCNT(n) ((n)<<4) /**< Byte count value. */ -#define GRXSTSP_CHNUM_MASK (15U<<0) /**< Channel number mask. */ -#define GRXSTSP_CHNUM(n) ((n)<<0) /**< Channel number value. */ -#define GRXSTSP_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ +#define GRXSTSP_BCNT(n) ((n) << 4) /**< Byte count value. */ +#define GRXSTSP_CHNUM_MASK (15U << 0) /**< Channel number mask. */ +#define GRXSTSP_CHNUM(n) ((n) << 0) /**< Channel number value. */ +#define GRXSTSP_EPNUM_MASK (15U << 0) /**< Endpoint number mask. */ #define GRXSTSP_EPNUM_OFF 0 /**< Endpoint number offset. */ -#define GRXSTSP_EPNUM(n) ((n)<<0) /**< Endpoint number value. */ +#define GRXSTSP_EPNUM(n) ((n) << 0) /**< Endpoint number value. */ /** @} */ /** * @name GRXFSIZ register bit definitions * @{ */ -#define GRXFSIZ_RXFD_MASK (0xFFFF<<0) /**< RxFIFO depth mask. */ -#define GRXFSIZ_RXFD(n) ((n)<<0) /**< RxFIFO depth value. */ +#define GRXFSIZ_RXFD_MASK (0xFFFFU << 0) /**< RxFIFO depth mask. */ +#define GRXFSIZ_RXFD(n) ((n) << 0) /**< RxFIFO depth value. */ /** @} */ /** * @name DIEPTXFx register bit definitions * @{ */ -#define DIEPTXF_INEPTXFD_MASK (0xFFFFU<<16)/**< IN endpoint TxFIFO depth - mask. */ -#define DIEPTXF_INEPTXFD(n) ((n)<<16) /**< IN endpoint TxFIFO depth - value. */ -#define DIEPTXF_INEPTXSA_MASK (0xFFFF<<0) /**< IN endpoint FIFOx transmit - RAM start address mask. */ -#define DIEPTXF_INEPTXSA(n) ((n)<<0) /**< IN endpoint FIFOx transmit - RAM start address value. */ +#define DIEPTXF_INEPTXFD_MASK (0xFFFFU << 16) /**< IN endpoint TxFIFO depth + mask. */ +#define DIEPTXF_INEPTXFD(n) ((n) << 16) /**< IN endpoint TxFIFO depth + value. */ +#define DIEPTXF_INEPTXSA_MASK (0xFFFFU << 0) /**< IN endpoint FIFOx transmit + RAM start address mask.*/ +#define DIEPTXF_INEPTXSA(n) ((n) << 0) /**< IN endpoint FIFOx transmit + RAM start address value.*/ /** @} */ /** @@ -418,42 +418,42 @@ typedef struct { * @{ */ /* Definitions for stepping 1.*/ -#define GCCFG_NOVBUSSENS (1U<<21) /**< VBUS sensing disable. */ -#define GCCFG_SOFOUTEN (1U<<20) /**< SOF output enable. */ -#define GCCFG_VBUSBSEN (1U<<19) /**< Enable the VBUS sensing "B" +#define GCCFG_NOVBUSSENS (1U << 21) /**< VBUS sensing disable. */ +#define GCCFG_SOFOUTEN (1U << 20) /**< SOF output enable. */ +#define GCCFG_VBUSBSEN (1U << 19) /**< Enable the VBUS sensing "B" device. */ -#define GCCFG_VBUSASEN (1U<<18) /**< Enable the VBUS sensing "A" +#define GCCFG_VBUSASEN (1U << 18) /**< Enable the VBUS sensing "A" device. */ /* Definitions for stepping 2.*/ -#define GCCFG_VBDEN (1U<<21) /**< VBUS sensing enable. */ -#define GCCFG_PWRDWN (1U<<16) /**< Power down. */ +#define GCCFG_VBDEN (1U << 21) /**< VBUS sensing enable. */ +#define GCCFG_PWRDWN (1U << 16) /**< Power down. */ /** @} */ /** * @name HPTXFSIZ register bit definitions * @{ */ -#define HPTXFSIZ_PTXFD_MASK (0xFFFFU<<16)/**< Host periodic TxFIFO - depth mask. */ -#define HPTXFSIZ_PTXFD(n) ((n)<<16) /**< Host periodic TxFIFO - depth value. */ -#define HPTXFSIZ_PTXSA_MASK (0xFFFFU<<0)/**< Host periodic TxFIFO - Start address mask. */ -#define HPTXFSIZ_PTXSA(n) ((n)<<0) /**< Host periodic TxFIFO - start address value. */ +#define HPTXFSIZ_PTXFD_MASK (0xFFFFU << 16) /**< Host periodic TxFIFO + depth mask. */ +#define HPTXFSIZ_PTXFD(n) ((n) << 16) /**< Host periodic TxFIFO + depth value. */ +#define HPTXFSIZ_PTXSA_MASK (0xFFFFU << 0) /**< Host periodic TxFIFO + Start address mask. */ +#define HPTXFSIZ_PTXSA(n) ((n) << 0) /**< Host periodic TxFIFO + start address value. */ /** @} */ /** * @name HCFG register bit definitions * @{ */ -#define HCFG_FSLSS (1U<<2) /**< FS- and LS-only support. */ -#define HCFG_FSLSPCS_MASK (3U<<0) /**< FS/LS PHY clock select +#define HCFG_FSLSS (1U << 2) /**< FS- and LS-only support. */ +#define HCFG_FSLSPCS_MASK (3U << 0) /**< FS/LS PHY clock select mask. */ -#define HCFG_FSLSPCS_48 (1U<<0) /**< PHY clock is running at +#define HCFG_FSLSPCS_48 (1U << 0) /**< PHY clock is running at 48 MHz. */ -#define HCFG_FSLSPCS_6 (2U<<0) /**< PHY clock is running at +#define HCFG_FSLSPCS_6 (2U << 0) /**< PHY clock is running at 6 MHz. */ /** @} */ @@ -461,186 +461,190 @@ typedef struct { * @name HFIR register bit definitions * @{ */ -#define HFIR_FRIVL_MASK (0xFFFFU<<0)/**< Frame interval mask. */ -#define HFIR_FRIVL(n) ((n)<<0) /**< Frame interval value. */ +#define HFIR_FRIVL_MASK (0xFFFFU << 0) /**< Frame interval mask. */ +#define HFIR_FRIVL(n) ((n) << 0) /**< Frame interval value. */ /** @} */ /** * @name HFNUM register bit definitions * @{ */ -#define HFNUM_FTREM_MASK (0xFFFFU<<16)/**< Frame time Remaining mask.*/ -#define HFNUM_FTREM(n) ((n)<<16) /**< Frame time Remaining value.*/ -#define HFNUM_FRNUM_MASK (0xFFFFU<<0)/**< Frame number mask. */ -#define HFNUM_FRNUM(n) ((n)<<0) /**< Frame number value. */ +#define HFNUM_FTREM_MASK (0xFFFFU << 16) /**< Frame time Remaining + mask. */ +#define HFNUM_FTREM(n) ((n) << 16) /**< Frame time Remaining + value. */ +#define HFNUM_FRNUM_MASK (0xFFFFU << 0) /**< Frame number mask. */ +#define HFNUM_FRNUM(n) ((n) << 0) /**< Frame number value. */ /** @} */ /** * @name HPTXSTS register bit definitions * @{ */ -#define HPTXSTS_PTXQTOP_MASK (0xFFU<<24) /**< Top of the periodic - transmit request queue - mask. */ -#define HPTXSTS_PTXQTOP(n) ((n)<<24) /**< Top of the periodic - transmit request queue - value. */ -#define HPTXSTS_PTXQSAV_MASK (0xFF<<16) /**< Periodic transmit request - queue Space Available - mask. */ -#define HPTXSTS_PTXQSAV(n) ((n)<<16) /**< Periodic transmit request - queue Space Available - value. */ -#define HPTXSTS_PTXFSAVL_MASK (0xFFFF<<0) /**< Periodic transmit Data - FIFO Space Available - mask. */ -#define HPTXSTS_PTXFSAVL(n) ((n)<<0) /**< Periodic transmit Data - FIFO Space Available - value. */ +#define HPTXSTS_PTXQTOP_MASK (0xFFU << 24) /**< Top of the periodic + transmit request queue + mask. */ +#define HPTXSTS_PTXQTOP(n) ((n) << 24) /**< Top of the periodic + transmit request queue + value. */ +#define HPTXSTS_PTXQSAV_MASK (0xFF<< 16) /**< Periodic transmit request + queue Space Available + mask. */ +#define HPTXSTS_PTXQSAV(n) ((n) << 16) /**< Periodic transmit request + queue Space Available + value. */ +#define HPTXSTS_PTXFSAVL_MASK (0xFFFF<< 0) /**< Periodic transmit Data + FIFO Space Available + mask. */ +#define HPTXSTS_PTXFSAVL(n) ((n) << 0) /**< Periodic transmit Data + FIFO Space Available + value. */ /** @} */ /** * @name HAINT register bit definitions * @{ */ -#define HAINT_HAINT_MASK (0xFFFFU<<0)/**< Channel interrupts mask. */ -#define HAINT_HAINT(n) ((n)<<0) /**< Channel interrupts value. */ +#define HAINT_HAINT_MASK (0xFFFFU << 0) /**< Channel interrupts + mask. */ +#define HAINT_HAINT(n) ((n) << 0) /**< Channel interrupts + value. */ /** @} */ /** * @name HAINTMSK register bit definitions * @{ */ -#define HAINTMSK_HAINTM_MASK (0xFFFFU<<0)/**< Channel interrupt mask - mask. */ -#define HAINTMSK_HAINTM(n) ((n)<<0) /**< Channel interrupt mask - value. */ +#define HAINTMSK_HAINTM_MASK (0xFFFFU << 0) /**< Channel interrupt mask + mask. */ +#define HAINTMSK_HAINTM(n) ((n) << 0) /**< Channel interrupt mask + value. */ /** @} */ /** * @name HPRT register bit definitions * @{ */ -#define HPRT_PSPD_MASK (3U<<17) /**< Port speed mask. */ -#define HPRT_PSPD_FS (1U<<17) /**< Full speed value. */ -#define HPRT_PSPD_LS (2U<<17) /**< Low speed value. */ -#define HPRT_PTCTL_MASK (15<<13) /**< Port Test control mask. */ -#define HPRT_PTCTL(n) ((n)<<13) /**< Port Test control value. */ -#define HPRT_PPWR (1U<<12) /**< Port power. */ -#define HPRT_PLSTS_MASK (3U<<11) /**< Port Line status mask. */ -#define HPRT_PLSTS_DM (1U<<11) /**< Logic level of D-. */ -#define HPRT_PLSTS_DP (1U<<10) /**< Logic level of D+. */ -#define HPRT_PRST (1U<<8) /**< Port reset. */ -#define HPRT_PSUSP (1U<<7) /**< Port suspend. */ -#define HPRT_PRES (1U<<6) /**< Port Resume. */ -#define HPRT_POCCHNG (1U<<5) /**< Port overcurrent change. */ -#define HPRT_POCA (1U<<4) /**< Port overcurrent active. */ -#define HPRT_PENCHNG (1U<<3) /**< Port enable/disable change.*/ -#define HPRT_PENA (1U<<2) /**< Port enable. */ -#define HPRT_PCDET (1U<<1) /**< Port Connect detected. */ -#define HPRT_PCSTS (1U<<0) /**< Port connect status. */ +#define HPRT_PSPD_MASK (3U << 17) /**< Port speed mask. */ +#define HPRT_PSPD_FS (1U << 17) /**< Full speed value. */ +#define HPRT_PSPD_LS (2U << 17) /**< Low speed value. */ +#define HPRT_PTCTL_MASK (15U << 13) /**< Port Test control mask. */ +#define HPRT_PTCTL(n) ((n) << 13) /**< Port Test control value. */ +#define HPRT_PPWR (1U << 12) /**< Port power. */ +#define HPRT_PLSTS_MASK (3U << 11) /**< Port Line status mask. */ +#define HPRT_PLSTS_DM (1U << 11) /**< Logic level of D-. */ +#define HPRT_PLSTS_DP (1U << 10) /**< Logic level of D+. */ +#define HPRT_PRST (1U << 8) /**< Port reset. */ +#define HPRT_PSUSP (1U << 7) /**< Port suspend. */ +#define HPRT_PRES (1U << 6) /**< Port Resume. */ +#define HPRT_POCCHNG (1U << 5) /**< Port overcurrent change. */ +#define HPRT_POCA (1U << 4) /**< Port overcurrent active. */ +#define HPRT_PENCHNG (1U << 3) /**< Port enable/disable change.*/ +#define HPRT_PENA (1U << 2) /**< Port enable. */ +#define HPRT_PCDET (1U << 1) /**< Port Connect detected. */ +#define HPRT_PCSTS (1U << 0) /**< Port connect status. */ /** @} */ /** * @name HCCHAR register bit definitions * @{ */ -#define HCCHAR_CHENA (1U<<31) /**< Channel enable. */ -#define HCCHAR_CHDIS (1U<<30) /**< Channel Disable. */ -#define HCCHAR_ODDFRM (1U<<29) /**< Odd frame. */ -#define HCCHAR_DAD_MASK (0x7FU<<22) /**< Device Address mask. */ -#define HCCHAR_DAD(n) ((n)<<22) /**< Device Address value. */ -#define HCCHAR_MCNT_MASK (3U<<20) /**< Multicount mask. */ -#define HCCHAR_MCNT(n) ((n)<<20) /**< Multicount value. */ -#define HCCHAR_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */ -#define HCCHAR_EPTYP(n) ((n)<<18) /**< Endpoint type value. */ -#define HCCHAR_EPTYP_CTL (0U<<18) /**< Control endpoint value. */ -#define HCCHAR_EPTYP_ISO (1U<<18) /**< Isochronous endpoint value.*/ -#define HCCHAR_EPTYP_BULK (2U<<18) /**< Bulk endpoint value. */ -#define HCCHAR_EPTYP_INTR (3U<<18) /**< Interrupt endpoint value. */ -#define HCCHAR_LSDEV (1U<<17) /**< Low-Speed device. */ -#define HCCHAR_EPDIR (1U<<15) /**< Endpoint direction. */ -#define HCCHAR_EPNUM_MASK (15U<<11) /**< Endpoint number mask. */ -#define HCCHAR_EPNUM(n) ((n)<<11) /**< Endpoint number value. */ -#define HCCHAR_MPS_MASK (0x7FFU<<0) /**< Maximum packet size mask. */ -#define HCCHAR_MPS(n) ((n)<<0) /**< Maximum packet size value. */ +#define HCCHAR_CHENA (1U << 31) /**< Channel enable. */ +#define HCCHAR_CHDIS (1U << 30) /**< Channel Disable. */ +#define HCCHAR_ODDFRM (1U << 29) /**< Odd frame. */ +#define HCCHAR_DAD_MASK (0x7FU << 22) /**< Device Address mask. */ +#define HCCHAR_DAD(n) ((n) << 22) /**< Device Address value. */ +#define HCCHAR_MCNT_MASK (3U << 20) /**< Multicount mask. */ +#define HCCHAR_MCNT(n) ((n) << 20) /**< Multicount value. */ +#define HCCHAR_EPTYP_MASK (3U << 18) /**< Endpoint type mask. */ +#define HCCHAR_EPTYP(n) ((n) << 18) /**< Endpoint type value. */ +#define HCCHAR_EPTYP_CTL (0U << 18) /**< Control endpoint value. */ +#define HCCHAR_EPTYP_ISO (1U << 18) /**< Isochronous endpoint value.*/ +#define HCCHAR_EPTYP_BULK (2U << 18) /**< Bulk endpoint value. */ +#define HCCHAR_EPTYP_INTR (3U << 18) /**< Interrupt endpoint value. */ +#define HCCHAR_LSDEV (1U << 17) /**< Low-Speed device. */ +#define HCCHAR_EPDIR (1U << 15) /**< Endpoint direction. */ +#define HCCHAR_EPNUM_MASK (15U << 11) /**< Endpoint number mask. */ +#define HCCHAR_EPNUM(n) ((n) << 11) /**< Endpoint number value. */ +#define HCCHAR_MPS_MASK (0x7FFU << 0) /**< Maximum packet size mask.*/ +#define HCCHAR_MPS(n) ((n) << 0) /**< Maximum packet size value. */ /** @} */ /** * @name HCINT register bit definitions * @{ */ -#define HCINT_DTERR (1U<<10) /**< Data toggle error. */ -#define HCINT_FRMOR (1U<<9) /**< Frame overrun. */ -#define HCINT_BBERR (1U<<8) /**< Babble error. */ -#define HCINT_TRERR (1U<<7) /**< Transaction Error. */ -#define HCINT_ACK (1U<<5) /**< ACK response +#define HCINT_DTERR (1U << 10) /**< Data toggle error. */ +#define HCINT_FRMOR (1U << 9) /**< Frame overrun. */ +#define HCINT_BBERR (1U << 8) /**< Babble error. */ +#define HCINT_TRERR (1U << 7) /**< Transaction Error. */ +#define HCINT_ACK (1U << 5) /**< ACK response received/transmitted interrupt. */ -#define HCINT_NAK (1U<<4) /**< NAK response received +#define HCINT_NAK (1U << 4) /**< NAK response received interrupt. */ -#define HCINT_STALL (1U<<3) /**< STALL response received +#define HCINT_STALL (1U << 3) /**< STALL response received interrupt. */ -#define HCINT_AHBERR (1U<<2) /**< AHB error interrupt. */ -#define HCINT_CHH (1U<<1) /**< Channel halted. */ -#define HCINT_XFRC (1U<<0) /**< Transfer completed. */ +#define HCINT_AHBERR (1U << 2) /**< AHB error interrupt. */ +#define HCINT_CHH (1U << 1) /**< Channel halted. */ +#define HCINT_XFRC (1U << 0) /**< Transfer completed. */ /** @} */ /** * @name HCINTMSK register bit definitions * @{ */ -#define HCINTMSK_DTERRM (1U<<10) /**< Data toggle error mask. */ -#define HCINTMSK_FRMORM (1U<<9) /**< Frame overrun mask. */ -#define HCINTMSK_BBERRM (1U<<8) /**< Babble error mask. */ -#define HCINTMSK_TRERRM (1U<<7) /**< Transaction error mask. */ -#define HCINTMSK_NYET (1U<<6) /**< NYET response received +#define HCINTMSK_DTERRM (1U << 10) /**< Data toggle error mask. */ +#define HCINTMSK_FRMORM (1U << 9) /**< Frame overrun mask. */ +#define HCINTMSK_BBERRM (1U << 8) /**< Babble error mask. */ +#define HCINTMSK_TRERRM (1U << 7) /**< Transaction error mask. */ +#define HCINTMSK_NYET (1U << 6) /**< NYET response received interrupt mask. */ -#define HCINTMSK_ACKM (1U<<5) /**< ACK Response +#define HCINTMSK_ACKM (1U << 5) /**< ACK Response received/transmitted interrupt mask. */ -#define HCINTMSK_NAKM (1U<<4) /**< NAK response received +#define HCINTMSK_NAKM (1U << 4) /**< NAK response received interrupt mask. */ -#define HCINTMSK_STALLM (1U<<3) /**< STALL response received +#define HCINTMSK_STALLM (1U << 3) /**< STALL response received interrupt mask. */ -#define HCINTMSK_AHBERRM (1U<<2) /**< AHB error interrupt mask. */ -#define HCINTMSK_CHHM (1U<<1) /**< Channel halted mask. */ -#define HCINTMSK_XFRCM (1U<<0) /**< Transfer completed mask. */ +#define HCINTMSK_AHBERRM (1U << 2) /**< AHB error interrupt mask. */ +#define HCINTMSK_CHHM (1U << 1) /**< Channel halted mask. */ +#define HCINTMSK_XFRCM (1U << 0) /**< Transfer completed mask. */ /** @} */ /** * @name HCTSIZ register bit definitions * @{ */ -#define HCTSIZ_DPID_MASK (3U<<29) /**< PID mask. */ -#define HCTSIZ_DPID_DATA0 (0U<<29) /**< DATA0. */ -#define HCTSIZ_DPID_DATA2 (1U<<29) /**< DATA2. */ -#define HCTSIZ_DPID_DATA1 (2U<<29) /**< DATA1. */ -#define HCTSIZ_DPID_MDATA (3U<<29) /**< MDATA. */ -#define HCTSIZ_DPID_SETUP (3U<<29) /**< SETUP. */ -#define HCTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */ -#define HCTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ -#define HCTSIZ_XFRSIZ_MASK (0x7FFFF<<0)/**< Transfer size mask. */ -#define HCTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ +#define HCTSIZ_DPID_MASK (3U << 29) /**< PID mask. */ +#define HCTSIZ_DPID_DATA0 (0U << 29) /**< DATA0. */ +#define HCTSIZ_DPID_DATA2 (1U << 29) /**< DATA2. */ +#define HCTSIZ_DPID_DATA1 (2U << 29) /**< DATA1. */ +#define HCTSIZ_DPID_MDATA (3U << 29) /**< MDATA. */ +#define HCTSIZ_DPID_SETUP (3U << 29) /**< SETUP. */ +#define HCTSIZ_PKTCNT_MASK (0x3FFU << 19) /**< Packet count mask. */ +#define HCTSIZ_PKTCNT(n) ((n) << 19) /**< Packet count value. */ +#define HCTSIZ_XFRSIZ_MASK (0x7FFFFU << 0) /**< Transfer size mask. */ +#define HCTSIZ_XFRSIZ(n) ((n) << 0) /**< Transfer size value. */ /** @} */ /** * @name DCFG register bit definitions * @{ */ -#define DCFG_PFIVL_MASK (3U<<11) /**< Periodic frame interval +#define DCFG_PFIVL_MASK (3U << 11) /**< Periodic frame interval mask. */ -#define DCFG_PFIVL(n) ((n)<<11) /**< Periodic frame interval +#define DCFG_PFIVL(n) ((n) << 11) /**< Periodic frame interval value. */ -#define DCFG_DAD_MASK (0x7FU<<4) /**< Device address mask. */ -#define DCFG_DAD(n) ((n)<<4) /**< Device address value. */ -#define DCFG_NZLSOHSK (1U<<2) /**< Non-Zero-Length status +#define DCFG_DAD_MASK (0x7FU << 4)/**< Device address mask. */ +#define DCFG_DAD(n) ((n) << 4) /**< Device address value. */ +#define DCFG_NZLSOHSK (1U << 2) /**< Non-Zero-Length status OUT handshake. */ -#define DCFG_DSPD_MASK (3U<<0) /**< Device speed mask. */ -#define DCFG_DSPD_HS (0U<<0) /**< High speed (USB 2.0). */ -#define DCFG_DSPD_HS_FS (1U<<0) /**< High speed (USB 2.0) in FS +#define DCFG_DSPD_MASK (3U << 0) /**< Device speed mask. */ +#define DCFG_DSPD_HS (0U << 0) /**< High speed (USB 2.0). */ +#define DCFG_DSPD_HS_FS (1U << 0) /**< High speed (USB 2.0) in FS mode. */ -#define DCFG_DSPD_FS11 (3U<<0) /**< Full speed (USB 1.1 +#define DCFG_DSPD_FS11 (3U << 0) /**< Full speed (USB 1.1 transceiver clock is 48 MHz). */ /** @} */ @@ -649,53 +653,53 @@ typedef struct { * @name DCTL register bit definitions * @{ */ -#define DCTL_POPRGDNE (1U<<11) /**< Power-on programming done. */ -#define DCTL_CGONAK (1U<<10) /**< Clear global OUT NAK. */ -#define DCTL_SGONAK (1U<<9) /**< Set global OUT NAK. */ -#define DCTL_CGINAK (1U<<8) /**< Clear global non-periodic +#define DCTL_POPRGDNE (1U << 11) /**< Power-on programming done. */ +#define DCTL_CGONAK (1U << 10) /**< Clear global OUT NAK. */ +#define DCTL_SGONAK (1U << 9) /**< Set global OUT NAK. */ +#define DCTL_CGINAK (1U << 8) /**< Clear global non-periodic IN NAK. */ -#define DCTL_SGINAK (1U<<7) /**< Set global non-periodic +#define DCTL_SGINAK (1U << 7) /**< Set global non-periodic IN NAK. */ -#define DCTL_TCTL_MASK (7U<<4) /**< Test control mask. */ -#define DCTL_TCTL(n) ((n)<<4 /**< Test control value. */ -#define DCTL_GONSTS (1U<<3) /**< Global OUT NAK status. */ -#define DCTL_GINSTS (1U<<2) /**< Global non-periodic IN +#define DCTL_TCTL_MASK (7U << 4) /**< Test control mask. */ +#define DCTL_TCTL(n) ((n) << 4 /**< Test control value. */ +#define DCTL_GONSTS (1U << 3) /**< Global OUT NAK status. */ +#define DCTL_GINSTS (1U << 2) /**< Global non-periodic IN NAK status. */ -#define DCTL_SDIS (1U<<1) /**< Soft disconnect. */ -#define DCTL_RWUSIG (1U<<0) /**< Remote wakeup signaling. */ +#define DCTL_SDIS (1U << 1) /**< Soft disconnect. */ +#define DCTL_RWUSIG (1U << 0) /**< Remote wakeup signaling. */ /** @} */ /** * @name DSTS register bit definitions * @{ */ -#define DSTS_FNSOF_MASK (0x3FFU<<8) /**< Frame number of the received - SOF mask. */ -#define DSTS_FNSOF(n) ((n)<<8) /**< Frame number of the received - SOF value. */ -#define DSTS_FNSOF_ODD (1U<<8) /**< Frame parity of the received - SOF value. */ -#define DSTS_EERR (1U<<3) /**< Erratic error. */ -#define DSTS_ENUMSPD_MASK (3U<<1) /**< Enumerated speed mask. */ -#define DSTS_ENUMSPD_FS_48 (3U<<1) /**< Full speed (PHY clock is - running at 48 MHz). */ -#define DSTS_ENUMSPD_HS_480 (0U<<1) /**< High speed. */ -#define DSTS_SUSPSTS (1U<<0) /**< Suspend status. */ +#define DSTS_FNSOF_MASK (0x3FFU << 8) /**< Frame number of the + received SOF mask. */ +#define DSTS_FNSOF(n) ((n) << 8) /**< Frame number of the + received SOF value. */ +#define DSTS_FNSOF_ODD (1U << 8) /**< Frame parity of the + received SOF value. */ +#define DSTS_EERR (1U << 3) /**< Erratic error. */ +#define DSTS_ENUMSPD_MASK (3U << 1) /**< Enumerated speed mask. */ +#define DSTS_ENUMSPD_FS_48 (3U << 1) /**< Full speed (PHY clock is + running at 48 MHz). */ +#define DSTS_ENUMSPD_HS_480 (0U << 1) /**< High speed. */ +#define DSTS_SUSPSTS (1U << 0) /**< Suspend status. */ /** @} */ /** * @name DIEPMSK register bit definitions * @{ */ -#define DIEPMSK_TXFEM (1U<<6) /**< Transmit FIFO empty mask. */ -#define DIEPMSK_INEPNEM (1U<<6) /**< IN endpoint NAK effective +#define DIEPMSK_TXFEM (1U << 6) /**< Transmit FIFO empty mask. */ +#define DIEPMSK_INEPNEM (1U << 6) /**< IN endpoint NAK effective mask. */ -#define DIEPMSK_ITTXFEMSK (1U<<4) /**< IN token received when +#define DIEPMSK_ITTXFEMSK (1U << 4) /**< IN token received when TxFIFO empty mask. */ -#define DIEPMSK_TOCM (1U<<3) /**< Timeout condition mask. */ -#define DIEPMSK_EPDM (1U<<1) /**< Endpoint disabled +#define DIEPMSK_TOCM (1U << 3) /**< Timeout condition mask. */ +#define DIEPMSK_EPDM (1U << 1) /**< Endpoint disabled interrupt mask. */ -#define DIEPMSK_XFRCM (1U<<0) /**< Transfer completed +#define DIEPMSK_XFRCM (1U << 0) /**< Transfer completed interrupt mask. */ /** @} */ @@ -703,12 +707,12 @@ typedef struct { * @name DOEPMSK register bit definitions * @{ */ -#define DOEPMSK_OTEPDM (1U<<4) /**< OUT token received when +#define DOEPMSK_OTEPDM (1U << 4) /**< OUT token received when endpoint disabled mask. */ -#define DOEPMSK_STUPM (1U<<3) /**< SETUP phase done mask. */ -#define DOEPMSK_EPDM (1U<<1) /**< Endpoint disabled +#define DOEPMSK_STUPM (1U << 3) /**< SETUP phase done mask. */ +#define DOEPMSK_EPDM (1U << 1) /**< Endpoint disabled interrupt mask. */ -#define DOEPMSK_XFRCM (1U<<0) /**< Transfer completed +#define DOEPMSK_XFRCM (1U << 0) /**< Transfer completed interrupt mask. */ /** @} */ @@ -716,161 +720,161 @@ typedef struct { * @name DAINT register bit definitions * @{ */ -#define DAINT_OEPINT_MASK (0xFFFFU<<16)/**< OUT endpoint interrupt - bits mask. */ -#define DAINT_OEPINT(n) ((n)<<16) /**< OUT endpoint interrupt - bits value. */ -#define DAINT_IEPINT_MASK (0xFFFFU<<0)/**< IN endpoint interrupt - bits mask. */ -#define DAINT_IEPINT(n) ((n)<<0) /**< IN endpoint interrupt - bits value. */ +#define DAINT_OEPINT_MASK (0xFFFFU << 16) /**< OUT endpoint interrupt + bits mask. */ +#define DAINT_OEPINT(n) ((n) << 16) /**< OUT endpoint interrupt + bits value. */ +#define DAINT_IEPINT_MASK (0xFFFFU << 0) /**< IN endpoint interrupt + bits mask. */ +#define DAINT_IEPINT(n) ((n) << 0) /**< IN endpoint interrupt + bits value. */ /** @} */ /** * @name DAINTMSK register bit definitions * @{ */ -#define DAINTMSK_OEPM_MASK (0xFFFFU<<16)/**< OUT EP interrupt mask - bits mask. */ -#define DAINTMSK_OEPM(n) (1U<<(16+(n)))/**< OUT EP interrupt mask - bits value. */ -#define DAINTMSK_IEPM_MASK (0xFFFFU<<0)/**< IN EP interrupt mask - bits mask. */ -#define DAINTMSK_IEPM(n) (1U<<(n)) /**< IN EP interrupt mask - bits value. */ +#define DAINTMSK_OEPM_MASK (0xFFFFU << 16) /**< OUT EP interrupt mask + bits mask. */ +#define DAINTMSK_OEPM(n) (1U <<(16+(n))) /**< OUT EP interrupt mask + bits value. */ +#define DAINTMSK_IEPM_MASK (0xFFFFU << 0) /**< IN EP interrupt mask + bits mask. */ +#define DAINTMSK_IEPM(n) (1U <<(n)) /**< IN EP interrupt mask + bits value. */ /** @} */ /** * @name DVBUSDIS register bit definitions * @{ */ -#define DVBUSDIS_VBUSDT_MASK (0xFFFFU<<0)/**< Device VBUS discharge - time mask. */ -#define DVBUSDIS_VBUSDT(n) ((n)<<0) /**< Device VBUS discharge - time value. */ +#define DVBUSDIS_VBUSDT_MASK (0xFFFFU << 0) /**< Device VBUS discharge + time mask. */ +#define DVBUSDIS_VBUSDT(n) ((n) << 0) /**< Device VBUS discharge + time value. */ /** @} */ /** * @name DVBUSPULSE register bit definitions * @{ */ -#define DVBUSPULSE_DVBUSP_MASK (0xFFFU<<0) /**< Device VBUSpulsing time - mask. */ -#define DVBUSPULSE_DVBUSP(n) ((n)<<0) /**< Device VBUS pulsing time - value. */ +#define DVBUSPULSE_DVBUSP_MASK (0xFFFU << 0) /**< Device VBUSpulsing time + mask. */ +#define DVBUSPULSE_DVBUSP(n) ((n) << 0) /**< Device VBUS pulsing time + value. */ /** @} */ /** * @name DIEPEMPMSK register bit definitions * @{ */ -#define DIEPEMPMSK_INEPTXFEM(n) (1U<<(n)) /**< IN EP Tx FIFO empty - interrupt mask bit. */ +#define DIEPEMPMSK_INEPTXFEM(n) (1U << (n)) /**< IN EP Tx FIFO empty + interrupt mask bit. */ /** @} */ /** * @name DIEPCTL register bit definitions * @{ */ -#define DIEPCTL_EPENA (1U<<31) /**< Endpoint enable. */ -#define DIEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */ -#define DIEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */ -#define DIEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */ -#define DIEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */ -#define DIEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */ -#define DIEPCTL_SNAK (1U<<27) /**< Set NAK. */ -#define DIEPCTL_CNAK (1U<<26) /**< Clear NAK. */ -#define DIEPCTL_TXFNUM_MASK (15U<<22) /**< TxFIFO number mask. */ -#define DIEPCTL_TXFNUM(n) ((n)<<22) /**< TxFIFO number value. */ -#define DIEPCTL_STALL (1U<<21) /**< STALL handshake. */ -#define DIEPCTL_SNPM (1U<<20) /**< Snoop mode. */ -#define DIEPCTL_EPTYP_MASK (3<<18) /**< Endpoint type mask. */ -#define DIEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */ -#define DIEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */ -#define DIEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */ -#define DIEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */ -#define DIEPCTL_NAKSTS (1U<<17) /**< NAK status. */ -#define DIEPCTL_EONUM (1U<<16) /**< Even/odd frame. */ -#define DIEPCTL_DPID (1U<<16) /**< Endpoint data PID. */ -#define DIEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */ -#define DIEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */ -#define DIEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */ +#define DIEPCTL_EPENA (1U << 31) /**< Endpoint enable. */ +#define DIEPCTL_EPDIS (1U << 30) /**< Endpoint disable. */ +#define DIEPCTL_SD1PID (1U << 29) /**< Set DATA1 PID. */ +#define DIEPCTL_SODDFRM (1U << 29) /**< Set odd frame. */ +#define DIEPCTL_SD0PID (1U << 28) /**< Set DATA0 PID. */ +#define DIEPCTL_SEVNFRM (1U << 28) /**< Set even frame. */ +#define DIEPCTL_SNAK (1U << 27) /**< Set NAK. */ +#define DIEPCTL_CNAK (1U << 26) /**< Clear NAK. */ +#define DIEPCTL_TXFNUM_MASK (15U << 22) /**< TxFIFO number mask. */ +#define DIEPCTL_TXFNUM(n) ((n) << 22) /**< TxFIFO number value. */ +#define DIEPCTL_STALL (1U << 21) /**< STALL handshake. */ +#define DIEPCTL_SNPM (1U << 20) /**< Snoop mode. */ +#define DIEPCTL_EPTYP_MASK (3U << 18) /**< Endpoint type mask. */ +#define DIEPCTL_EPTYP_CTRL (0U << 18) /**< Control. */ +#define DIEPCTL_EPTYP_ISO (1U << 18) /**< Isochronous. */ +#define DIEPCTL_EPTYP_BULK (2U << 18) /**< Bulk. */ +#define DIEPCTL_EPTYP_INTR (3U << 18) /**< Interrupt. */ +#define DIEPCTL_NAKSTS (1U << 17) /**< NAK status. */ +#define DIEPCTL_EONUM (1U << 16) /**< Even/odd frame. */ +#define DIEPCTL_DPID (1U << 16) /**< Endpoint data PID. */ +#define DIEPCTL_USBAEP (1U << 15) /**< USB active endpoint. */ +#define DIEPCTL_MPSIZ_MASK (0x3FFU << 0) /**< Maximum Packet size mask.*/ +#define DIEPCTL_MPSIZ(n) ((n) << 0) /**< Maximum Packet size value. */ /** @} */ /** * @name DIEPINT register bit definitions * @{ */ -#define DIEPINT_TXFE (1U<<7) /**< Transmit FIFO empty. */ -#define DIEPINT_INEPNE (1U<<6) /**< IN endpoint NAK effective. */ -#define DIEPINT_ITTXFE (1U<<4) /**< IN Token received when +#define DIEPINT_TXFE (1U << 7) /**< Transmit FIFO empty. */ +#define DIEPINT_INEPNE (1U << 6) /**< IN endpoint NAK effective. */ +#define DIEPINT_ITTXFE (1U << 4) /**< IN Token received when TxFIFO is empty. */ -#define DIEPINT_TOC (1U<<3) /**< Timeout condition. */ -#define DIEPINT_EPDISD (1U<<1) /**< Endpoint disabled +#define DIEPINT_TOC (1U << 3) /**< Timeout condition. */ +#define DIEPINT_EPDISD (1U << 1) /**< Endpoint disabled interrupt. */ -#define DIEPINT_XFRC (1U<<0) /**< Transfer completed. */ +#define DIEPINT_XFRC (1U << 0) /**< Transfer completed. */ /** @} */ /** * @name DIEPTSIZ register bit definitions * @{ */ -#define DIEPTSIZ_MCNT_MASK (3U<<29) /**< Multi count mask. */ -#define DIEPTSIZ_MCNT(n) ((n)<<29) /**< Multi count value. */ -#define DIEPTSIZ_PKTCNT_MASK (0x3FF<<19) /**< Packet count mask. */ -#define DIEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ -#define DIEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */ -#define DIEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ +#define DIEPTSIZ_MCNT_MASK (3U << 29) /**< Multi count mask. */ +#define DIEPTSIZ_MCNT(n) ((n) << 29) /**< Multi count value. */ +#define DIEPTSIZ_PKTCNT_MASK (0x3FF<< 19) /**< Packet count mask. */ +#define DIEPTSIZ_PKTCNT(n) ((n) << 19) /**< Packet count value. */ +#define DIEPTSIZ_XFRSIZ_MASK (0x7FFFFU << 0) /**< Transfer size mask. */ +#define DIEPTSIZ_XFRSIZ(n) ((n) << 0) /**< Transfer size value. */ /** @} */ /** * @name DTXFSTS register bit definitions. * @{ */ -#define DTXFSTS_INEPTFSAV_MASK (0xFFFF<<0) /**< IN endpoint TxFIFO space - available. */ +#define DTXFSTS_INEPTFSAV_MASK (0xFFFFU << 0) /**< IN endpoint TxFIFO space + available. */ /** @} */ /** * @name DOEPCTL register bit definitions. * @{ */ -#define DOEPCTL_EPENA (1U<<31) /**< Endpoint enable. */ -#define DOEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */ -#define DOEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */ -#define DOEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */ -#define DOEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */ -#define DOEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */ -#define DOEPCTL_SNAK (1U<<27) /**< Set NAK. */ -#define DOEPCTL_CNAK (1U<<26) /**< Clear NAK. */ -#define DOEPCTL_STALL (1U<<21) /**< STALL handshake. */ -#define DOEPCTL_SNPM (1U<<20) /**< Snoop mode. */ -#define DOEPCTL_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */ -#define DOEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */ -#define DOEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */ -#define DOEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */ -#define DOEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */ -#define DOEPCTL_NAKSTS (1U<<17) /**< NAK status. */ -#define DOEPCTL_EONUM (1U<<16) /**< Even/odd frame. */ -#define DOEPCTL_DPID (1U<<16) /**< Endpoint data PID. */ -#define DOEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */ -#define DOEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */ -#define DOEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */ +#define DOEPCTL_EPENA (1U << 31) /**< Endpoint enable. */ +#define DOEPCTL_EPDIS (1U << 30) /**< Endpoint disable. */ +#define DOEPCTL_SD1PID (1U << 29) /**< Set DATA1 PID. */ +#define DOEPCTL_SODDFRM (1U << 29) /**< Set odd frame. */ +#define DOEPCTL_SD0PID (1U << 28) /**< Set DATA0 PID. */ +#define DOEPCTL_SEVNFRM (1U << 28) /**< Set even frame. */ +#define DOEPCTL_SNAK (1U << 27) /**< Set NAK. */ +#define DOEPCTL_CNAK (1U << 26) /**< Clear NAK. */ +#define DOEPCTL_STALL (1U << 21) /**< STALL handshake. */ +#define DOEPCTL_SNPM (1U << 20) /**< Snoop mode. */ +#define DOEPCTL_EPTYP_MASK (3U << 18) /**< Endpoint type mask. */ +#define DOEPCTL_EPTYP_CTRL (0U << 18) /**< Control. */ +#define DOEPCTL_EPTYP_ISO (1U << 18) /**< Isochronous. */ +#define DOEPCTL_EPTYP_BULK (2U << 18) /**< Bulk. */ +#define DOEPCTL_EPTYP_INTR (3U << 18) /**< Interrupt. */ +#define DOEPCTL_NAKSTS (1U << 17) /**< NAK status. */ +#define DOEPCTL_EONUM (1U << 16) /**< Even/odd frame. */ +#define DOEPCTL_DPID (1U << 16) /**< Endpoint data PID. */ +#define DOEPCTL_USBAEP (1U << 15) /**< USB active endpoint. */ +#define DOEPCTL_MPSIZ_MASK (0x3FFU << 0)/**< Maximum Packet size mask. */ +#define DOEPCTL_MPSIZ(n) ((n) << 0) /**< Maximum Packet size value. */ /** @} */ /** * @name DOEPINT register bit definitions * @{ */ -#define DOEPINT_SETUP_RCVD (1U<<15) /**< SETUP packet received. */ -#define DOEPINT_B2BSTUP (1U<<6) /**< Back-to-back SETUP packets +#define DOEPINT_SETUP_RCVD (1U << 15) /**< SETUP packet received. */ +#define DOEPINT_B2BSTUP (1U << 6) /**< Back-to-back SETUP packets received. */ -#define DOEPINT_OTEPDIS (1U<<4) /**< OUT token received when +#define DOEPINT_OTEPDIS (1U << 4) /**< OUT token received when endpoint disabled. */ -#define DOEPINT_STUP (1U<<3) /**< SETUP phase done. */ -#define DOEPINT_EPDISD (1U<<1) /**< Endpoint disabled +#define DOEPINT_STUP (1U << 3) /**< SETUP phase done. */ +#define DOEPINT_EPDISD (1U << 1) /**< Endpoint disabled interrupt. */ -#define DOEPINT_XFRC (1U<<0) /**< Transfer completed +#define DOEPINT_XFRC (1U << 0) /**< Transfer completed interrupt. */ /** @} */ @@ -878,23 +882,23 @@ typedef struct { * @name DOEPTSIZ register bit definitions * @{ */ -#define DOEPTSIZ_RXDPID_MASK (3U<<29) /**< Received data PID mask. */ -#define DOEPTSIZ_RXDPID(n) ((n)<<29) /**< Received data PID value. */ -#define DOEPTSIZ_STUPCNT_MASK (3U<<29) /**< SETUP packet count mask. */ -#define DOEPTSIZ_STUPCNT(n) ((n)<<29) /**< SETUP packet count value. */ -#define DOEPTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */ -#define DOEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ -#define DOEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */ -#define DOEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ +#define DOEPTSIZ_RXDPID_MASK (3U << 29) /**< Received data PID mask. */ +#define DOEPTSIZ_RXDPID(n) ((n) << 29) /**< Received data PID value. */ +#define DOEPTSIZ_STUPCNT_MASK (3U << 29) /**< SETUP packet count mask. */ +#define DOEPTSIZ_STUPCNT(n) ((n) << 29) /**< SETUP packet count value. */ +#define DOEPTSIZ_PKTCNT_MASK (0x3FFU << 19) /**< Packet count mask. */ +#define DOEPTSIZ_PKTCNT(n) ((n) << 19) /**< Packet count value. */ +#define DOEPTSIZ_XFRSIZ_MASK (0x7FFFFU << 0) /**< Transfer size mask. */ +#define DOEPTSIZ_XFRSIZ(n) ((n) << 0) /**< Transfer size value. */ /** @} */ /** * @name PCGCCTL register bit definitions * @{ */ -#define PCGCCTL_PHYSUSP (1U<<4) /**< PHY Suspended. */ -#define PCGCCTL_GATEHCLK (1U<<1) /**< Gate HCLK. */ -#define PCGCCTL_STPPCLK (1U<<0) /**< Stop PCLK. */ +#define PCGCCTL_PHYSUSP (1U << 4) /**< PHY Suspended. */ +#define PCGCCTL_GATEHCLK (1U << 1) /**< Gate HCLK. */ +#define PCGCCTL_STPPCLK (1U << 0) /**< Stop PCLK. */ /** @} */ #if defined(STM32H7XX) || defined(__DOXYGEN__) diff --git a/os/hal/ports/STM32/LLD/RTCv3/hal_rtc_lld.h b/os/hal/ports/STM32/LLD/RTCv3/hal_rtc_lld.h index c280a1c58..a3d332f31 100644 --- a/os/hal/ports/STM32/LLD/RTCv3/hal_rtc_lld.h +++ b/os/hal/ports/STM32/LLD/RTCv3/hal_rtc_lld.h @@ -249,7 +249,6 @@ typedef struct hal_rtc_wakeup { /* Pointer to TAMPER registers block. */ \ TAMP_TypeDef *tamp - /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.h b/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.h index e7a841889..62ae010d5 100644 --- a/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.h +++ b/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.h @@ -319,7 +319,6 @@ #error "invalid DMA stream associated to SPI3 TX" #endif - #endif /* STM32_ADVANCED_DMA && !STM32_DMA_SUPPORTS_DMAMUX */ #if !defined(STM32_DMA_REQUIRED) diff --git a/os/hal/ports/STM32/LLD/SPIv2/hal_spi_v2_lld.c b/os/hal/ports/STM32/LLD/SPIv2/hal_spi_v2_lld.c index 6174ae357..fd1723335 100644 --- a/os/hal/ports/STM32/LLD/SPIv2/hal_spi_v2_lld.c +++ b/os/hal/ports/STM32/LLD/SPIv2/hal_spi_v2_lld.c @@ -277,7 +277,7 @@ static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) { * @return The operation status. */ static msg_t spi_lld_get_dma(SPIDriver *spip, uint32_t rxstream, - uint32_t txstream, uint32_t priority){ + uint32_t txstream, uint32_t priority) { spip->dmarx = dmaStreamAllocI(rxstream, priority, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, diff --git a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_v2_lld.c b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_v2_lld.c index f3cf3f61c..7ae5befaa 100644 --- a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_v2_lld.c +++ b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_v2_lld.c @@ -396,7 +396,7 @@ static void spi_lld_serve_interrupt(SPIDriver *spip) { * @return The operation status. */ static msg_t spi_lld_get_dma(SPIDriver *spip, uint32_t rxstream, - uint32_t txstream, uint32_t priority){ + uint32_t txstream, uint32_t priority) { spip->rx.dma = dmaStreamAllocI(rxstream, priority, (stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt, @@ -428,7 +428,7 @@ static msg_t spi_lld_get_dma(SPIDriver *spip, uint32_t rxstream, * @return The operation status. */ static msg_t spi_lld_get_bdma(SPIDriver *spip, uint32_t rxstream, - uint32_t txstream, uint32_t priority){ + uint32_t txstream, uint32_t priority) { spip->rx.bdma = bdmaStreamAllocI(rxstream, priority, (stm32_bdmaisr_t)spi_lld_serve_bdma_rx_interrupt, diff --git a/os/hal/ports/STM32/LLD/SYSTICKv1/hal_st_lld.h b/os/hal/ports/STM32/LLD/SYSTICKv1/hal_st_lld.h index 04a9e3d32..8fa861879 100644 --- a/os/hal/ports/STM32/LLD/SYSTICKv1/hal_st_lld.h +++ b/os/hal/ports/STM32/LLD/SYSTICKv1/hal_st_lld.h @@ -137,7 +137,7 @@ #if !defined(STM32_HAS_TIM22) #define STM32_HAS_TIM22 FALSE #endif -/**/ +/* End of checks to be removed.*/ #if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING @@ -684,7 +684,6 @@ extern "C" { /* Driver inline functions. */ /*===========================================================================*/ - #if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__) /** @@ -786,7 +785,6 @@ static inline bool st_lld_is_alarm_active(void) { */ static inline void st_lld_start_alarm_n(unsigned alarm, systime_t abstime) { - STM32_ST_TIM->CCR[alarm] = (uint32_t)abstime; STM32_ST_TIM->SR = 0; STM32_ST_TIM->DIER |= (STM32_TIM_DIER_CC1IE << alarm); diff --git a/os/hal/ports/STM32/LLD/SYSTICKv2/hal_st_lld.c b/os/hal/ports/STM32/LLD/SYSTICKv2/hal_st_lld.c index 087618ab6..806574513 100644 --- a/os/hal/ports/STM32/LLD/SYSTICKv2/hal_st_lld.c +++ b/os/hal/ports/STM32/LLD/SYSTICKv2/hal_st_lld.c @@ -1,153 +1,153 @@ -/* - ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SYSTICKv2/hal_st_lld.h - * @brief ST Driver subsystem low level driver code. - * - * @addtogroup ST - * @{ - */ - -#include "hal.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define ST_HANDLER STM32_RTC_ALARM_HANDLER -#define ST_NUMBER STM32_RTC_ALARM_NUMBER - -#define STM32_ST_RTC_PREDIVA (STM32_RTCCLK / OSAL_ST_FREQUENCY) - -/** - * Initialization for the RTC_PRER register. - */ -#define STM32_ST_RTC_PRER_BITS ((STM32_ST_RTC_PREDIVA - 1) << RTC_PRER_PREDIV_A_Pos) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if !defined(STM32_SYSTICK_SUPPRESS_ISR) -/** - * @brief Interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(ST_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - st_lld_serve_interrupt(); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ST driver initialization. - * - * @notapi - */ -void st_lld_init(void) { - - /* Enabling the stop mode during debug for RTC.*/ - DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_RTC_STOP; - - /* Enable RTC kernel clock.*/ - RCC->BDCR |= RCC_BDCR_RTCEN; - - /* Enable RTC APB bus clock.*/ - rccEnableAPB1R1(RCC_APB1ENR1_RTCAPBEN, true); - - /* Disable RTC write protection.*/ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Disable all alarms and interrupts.*/ - RTC->CR &= ~(RTC_CR_ALRAIE | RTC_CR_ALRBIE | RTC_CR_ALRAE | RTC_CR_ALRBE); - - /* Enter initialization mode.*/ - RTC->ICSR |= RTC_ICSR_INIT; - while ((RTC->ICSR & RTC_ICSR_INITF) == 0U) { - /* Waint for init flag.*/ - } - - /* Activate free running Binary mode.*/ - RTC->ICSR |= RTC_ICSR_BIN_0; - /* Set RTC prescaler.*/ - RTC->PRER = STM32_ST_RTC_PRER_BITS; - - /* Exit initialization mode.*/ - RTC->ICSR &= ~RTC_ICSR_INIT; - - /* Wait for shadow reg. update.*/ - while ((RTC->ICSR & RTC_ICSR_RSF) == 0U) { - // wait RSF flag - } - - /* Compare all Sub Seconds 32 bits for RTC Alarm A.*/ - RTC->ALRMASSR = (32UL << RTC_ALRMASSR_MASKSS_Pos); - - /* EXTI enable.*/ - extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI), EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); - /* IRQ enable.*/ - nvicEnableVector(ST_NUMBER, STM32_ST_IRQ_PRIORITY); - -} - -/** - * @brief IRQ handling code. - */ -void st_lld_serve_interrupt(void) { - - uint32_t isr; - - /* Get and clear the RTC interrupts. */ - isr = RTC->MISR; - RTC->SCR = isr; - - if ((isr & RTC_MISR_ALRAMF) != 0U) { - - osalSysLockFromISR(); - osalOsTimerHandlerI(); - osalSysUnlockFromISR(); - } - -} - -/** @} */ +/* + ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SYSTICKv2/hal_st_lld.h + * @brief ST Driver subsystem low level driver code. + * + * @addtogroup ST + * @{ + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define ST_HANDLER STM32_RTC_ALARM_HANDLER +#define ST_NUMBER STM32_RTC_ALARM_NUMBER + +#define STM32_ST_RTC_PREDIVA (STM32_RTCCLK / OSAL_ST_FREQUENCY) + +/** + * Initialization for the RTC_PRER register. + */ +#define STM32_ST_RTC_PRER_BITS ((STM32_ST_RTC_PREDIVA - 1) << RTC_PRER_PREDIV_A_Pos) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if !defined(STM32_SYSTICK_SUPPRESS_ISR) +/** + * @brief Interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(ST_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + st_lld_serve_interrupt(); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ST driver initialization. + * + * @notapi + */ +void st_lld_init(void) { + + /* Enabling the stop mode during debug for RTC.*/ + DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_RTC_STOP; + + /* Enable RTC kernel clock.*/ + RCC->BDCR |= RCC_BDCR_RTCEN; + + /* Enable RTC APB bus clock.*/ + rccEnableAPB1R1(RCC_APB1ENR1_RTCAPBEN, true); + + /* Disable RTC write protection.*/ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Disable all alarms and interrupts.*/ + RTC->CR &= ~(RTC_CR_ALRAIE | RTC_CR_ALRBIE | RTC_CR_ALRAE | RTC_CR_ALRBE); + + /* Enter initialization mode.*/ + RTC->ICSR |= RTC_ICSR_INIT; + while ((RTC->ICSR & RTC_ICSR_INITF) == 0U) { + /* Waint for init flag.*/ + } + + /* Activate free running Binary mode.*/ + RTC->ICSR |= RTC_ICSR_BIN_0; + /* Set RTC prescaler.*/ + RTC->PRER = STM32_ST_RTC_PRER_BITS; + + /* Exit initialization mode.*/ + RTC->ICSR &= ~RTC_ICSR_INIT; + + /* Wait for shadow reg. update.*/ + while ((RTC->ICSR & RTC_ICSR_RSF) == 0U) { + /* Wait RSF flag.*/ + } + + /* Compare all Sub Seconds 32 bits for RTC Alarm A.*/ + RTC->ALRMASSR = (32UL << RTC_ALRMASSR_MASKSS_Pos); + + /* EXTI enable.*/ + extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI), EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); + /* IRQ enable.*/ + nvicEnableVector(ST_NUMBER, STM32_ST_IRQ_PRIORITY); + +} + +/** + * @brief IRQ handling code. + */ +void st_lld_serve_interrupt(void) { + + uint32_t isr; + + /* Get and clear the RTC interrupts. */ + isr = RTC->MISR; + RTC->SCR = isr; + + if ((isr & RTC_MISR_ALRAMF) != 0U) { + + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); + } + +} + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/SYSTICKv2/hal_st_lld.h b/os/hal/ports/STM32/LLD/SYSTICKv2/hal_st_lld.h index 88b89ded1..b3709d62d 100644 --- a/os/hal/ports/STM32/LLD/SYSTICKv2/hal_st_lld.h +++ b/os/hal/ports/STM32/LLD/SYSTICKv2/hal_st_lld.h @@ -1,219 +1,217 @@ -/* - ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SYSTICKv2/hal_st_lld.h - * @brief RTC V3 based ST Driver subsystem low level driver header. - * - * @addtogroup ST - * @{ - */ - -#ifndef HAL_RTC_ST_LLD_H -#define HAL_RTC_ST_LLD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief RTC SSR registry initial value. - */ -#define STM32_RTC_SSR_INIT_VALUE 0xFFFFFFFFUL - -/* Requires services from the EXTI driver.*/ -#if !defined(STM32_EXTI_REQUIRED) -#define STM32_EXTI_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief SysTick timer IRQ priority. - */ -#if !defined(STM32_ST_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ST_IRQ_PRIORITY 8 -#endif - -/** - * @brief RTC binary mode attribute default value. - */ -#if !defined(STM32_RTC_HAS_BINARY_MODE) || defined(__DOXYGEN__) -#define STM32_RTC_HAS_BINARY_MODE FALSE -#endif - -/** - * @brief RTC mixed mode attribute default value. - */ -#if !defined(STM32_RTC_HAS_MIXED_MODE) || defined(__DOXYGEN__) -#define STM32_RTC_HAS_MIXED_MODE FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if OSAL_ST_MODE != OSAL_ST_MODE_FREERUNNING -#error "ST based on RTC supports only free running mode. Change CH_CFG_ST_TIMEDELTA to enable tick-less mode." -#endif - -#if STM32_HAS_RTC == FALSE -#error "RTC not present in the selected device" -#endif - -#if HAL_USE_RTC == TRUE -#error "ST requires RTC but it is already used" -#endif - -#if STM32_RTC_HAS_BINARY_MODE == FALSE -#error "RTC does not support binary mode" -#endif - - -#if (OSAL_ST_RESOLUTION != 32) -#error "ST based on RTC requires 32bits resolution. Set CH_CFG_ST_RESOLUTION to 32." -#endif - -#if (STM32_RTCCLK % OSAL_ST_FREQUENCY) != 0 -#error "the selected ST frequency is not obtainable because integer rounding" -#endif - -#if (STM32_RTCCLK / OSAL_ST_FREQUENCY) > 128 -#error "the selected ST frequency is not obtainable because RTC Prescaler A limits" -#endif - -/** - * @brief ST Deep Sleep support attrubute. - */ -#define STM32_ST_DEEP_SLEEP_SUPPORT TRUE - -/** - * @brief ST Alarms number. - */ -#define ST_LLD_NUM_ALARMS 1 - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void st_lld_init(void); - void st_lld_serve_interrupt(void); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Driver inline functions. */ -/*===========================================================================*/ - -/** - * @brief Returns the time counter value. - * - * @return The counter value. - * - * @notapi - */ -static inline systime_t st_lld_get_counter(void) { - - return (systime_t)(STM32_RTC_SSR_INIT_VALUE - RTC->SSR); -} - -/** - * @brief Starts the alarm. - * @note Makes sure that no spurious alarms are triggered after - * this call. - * - * @param[in] abstime the time to be set for the first alarm - * - * @notapi - */ -static inline void st_lld_start_alarm(systime_t abstime) { - - /* Disable RTC Alarm A.*/ - RTC->CR &= ~(RTC_CR_ALRAE | RTC_CR_ALRAIE); - - /* Set alarm time.*/ - RTC->ALRABINR = (STM32_RTC_SSR_INIT_VALUE - (uint32_t)abstime); - - /* Enabel RTC Alarm A.*/ - RTC->CR |= (RTC_CR_ALRAE | RTC_CR_ALRAIE); -} - -/** - * @brief Sets the alarm time. - * - * @param[in] abstime the time to be set for the next alarm - * - * @notapi - */ -static inline void st_lld_set_alarm(systime_t abstime) { - - st_lld_start_alarm(abstime); -} - - -/** - * @brief Determines if the alarm is active. - * - * @return The alarm status. - * @retval false if the alarm is not active. - * @retval true is the alarm is active - * - * @notapi - */ -static inline bool st_lld_is_alarm_active(void) { - - return (bool)((RTC->CR & RTC_CR_ALRAE) != 0); -} - -/** - * @brief Stops the alarm interrupt. - * - * @notapi - */ -static inline void st_lld_stop_alarm(void) { - - RTC->CR &= ~(RTC_CR_ALRAE | RTC_CR_ALRAIE); -} - -/** - * @brief Returns the current alarm time. - * - * @return The currently set alarm time. - * - * @notapi - */ -static inline systime_t st_lld_get_alarm(void) { - - return (systime_t)(STM32_RTC_SSR_INIT_VALUE - RTC->ALRABINR); -} - -#endif /* HAL_RTC_ST_LLD_H */ - -/** @} */ +/* + ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SYSTICKv2/hal_st_lld.h + * @brief RTC V3 based ST Driver subsystem low level driver header. + * + * @addtogroup ST + * @{ + */ + +#ifndef HAL_RTC_ST_LLD_H +#define HAL_RTC_ST_LLD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief RTC SSR registry initial value. + */ +#define STM32_RTC_SSR_INIT_VALUE 0xFFFFFFFFUL + +/* Requires services from the EXTI driver.*/ +#if !defined(STM32_EXTI_REQUIRED) +#define STM32_EXTI_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SysTick timer IRQ priority. + */ +#if !defined(STM32_ST_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ST_IRQ_PRIORITY 8 +#endif + +/** + * @brief RTC binary mode attribute default value. + */ +#if !defined(STM32_RTC_HAS_BINARY_MODE) || defined(__DOXYGEN__) +#define STM32_RTC_HAS_BINARY_MODE FALSE +#endif + +/** + * @brief RTC mixed mode attribute default value. + */ +#if !defined(STM32_RTC_HAS_MIXED_MODE) || defined(__DOXYGEN__) +#define STM32_RTC_HAS_MIXED_MODE FALSE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if OSAL_ST_MODE != OSAL_ST_MODE_FREERUNNING +#error "ST based on RTC supports only free running mode. Change CH_CFG_ST_TIMEDELTA to enable tick-less mode." +#endif + +#if STM32_HAS_RTC == FALSE +#error "RTC not present in the selected device" +#endif + +#if HAL_USE_RTC == TRUE +#error "ST requires RTC but it is already used" +#endif + +#if STM32_RTC_HAS_BINARY_MODE == FALSE +#error "RTC does not support binary mode" +#endif + +#if (OSAL_ST_RESOLUTION != 32) +#error "ST based on RTC requires 32bits resolution. Set CH_CFG_ST_RESOLUTION to 32." +#endif + +#if (STM32_RTCCLK % OSAL_ST_FREQUENCY) != 0 +#error "the selected ST frequency is not obtainable because integer rounding" +#endif + +#if (STM32_RTCCLK / OSAL_ST_FREQUENCY) > 128 +#error "the selected ST frequency is not obtainable because RTC Prescaler A limits" +#endif + +/** + * @brief ST Deep Sleep support attrubute. + */ +#define STM32_ST_DEEP_SLEEP_SUPPORT TRUE + +/** + * @brief ST Alarms number. + */ +#define ST_LLD_NUM_ALARMS 1 + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void st_lld_init(void); + void st_lld_serve_interrupt(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Driver inline functions. */ +/*===========================================================================*/ + +/** + * @brief Returns the time counter value. + * + * @return The counter value. + * + * @notapi + */ +static inline systime_t st_lld_get_counter(void) { + + return (systime_t)(STM32_RTC_SSR_INIT_VALUE - RTC->SSR); +} + +/** + * @brief Starts the alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * + * @param[in] abstime the time to be set for the first alarm + * + * @notapi + */ +static inline void st_lld_start_alarm(systime_t abstime) { + + /* Disable RTC Alarm A.*/ + RTC->CR &= ~(RTC_CR_ALRAE | RTC_CR_ALRAIE); + + /* Set alarm time.*/ + RTC->ALRABINR = (STM32_RTC_SSR_INIT_VALUE - (uint32_t)abstime); + + /* Enabel RTC Alarm A.*/ + RTC->CR |= (RTC_CR_ALRAE | RTC_CR_ALRAIE); +} + +/** + * @brief Sets the alarm time. + * + * @param[in] abstime the time to be set for the next alarm + * + * @notapi + */ +static inline void st_lld_set_alarm(systime_t abstime) { + + st_lld_start_alarm(abstime); +} + +/** + * @brief Determines if the alarm is active. + * + * @return The alarm status. + * @retval false if the alarm is not active. + * @retval true is the alarm is active + * + * @notapi + */ +static inline bool st_lld_is_alarm_active(void) { + + return (bool)((RTC->CR & RTC_CR_ALRAE) != 0); +} + +/** + * @brief Stops the alarm interrupt. + * + * @notapi + */ +static inline void st_lld_stop_alarm(void) { + + RTC->CR &= ~(RTC_CR_ALRAE | RTC_CR_ALRAIE); +} + +/** + * @brief Returns the current alarm time. + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t st_lld_get_alarm(void) { + + return (systime_t)(STM32_RTC_SSR_INIT_VALUE - RTC->ALRABINR); +} + +#endif /* HAL_RTC_ST_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.c b/os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.c index e5d49a421..c611b0872 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.c @@ -377,7 +377,6 @@ msg_t sio_lld_start(SIODriver *siop) { siop->sync_rx = NULL; siop->sync_tx = NULL; siop->sync_txend = NULL; -// siop->events = 0U; #endif } @@ -387,7 +386,6 @@ msg_t sio_lld_start(SIODriver *siop) { return HAL_RET_SUCCESS; } - /** * @brief Deactivates the SIO peripheral. * diff --git a/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c b/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c index e6754676e..07dc3dae5 100644 --- a/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c @@ -385,7 +385,6 @@ msg_t sio_lld_start(SIODriver *siop) { siop->sync_rx = NULL; siop->sync_tx = NULL; siop->sync_txend = NULL; -// siop->events = 0U; #endif } @@ -395,7 +394,6 @@ msg_t sio_lld_start(SIODriver *siop) { return HAL_RET_SUCCESS; } - /** * @brief Deactivates the SIO peripheral. * diff --git a/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c b/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c index 4435be1a3..68b55a676 100644 --- a/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c +++ b/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c @@ -539,8 +539,8 @@ void usb_lld_reset(USBDriver *usbp) { STM32_USB->BTABLE = BTABLE_ADDR; STM32_USB->ISTR = 0; STM32_USB->DADDR = DADDR_EF; - cntr = /*CNTR_ESOFM | */ CNTR_RESETM | CNTR_SUSPM | - CNTR_WKUPM | /*CNTR_ERRM | CNTR_PMAOVRM |*/ CNTR_CTRM; + cntr = /* CNTR_ESOFM | */ CNTR_RESETM | CNTR_SUSPM | + CNTR_WKUPM | /* CNTR_ERRM | CNTR_PMAOVRM |*/ CNTR_CTRM; /* The SOF interrupt is only enabled if a callback is defined for this service because it is an high rate source.*/ if (usbp->config->sof_cb != NULL) diff --git a/os/hal/ports/STM32/STM32F4xx/hal_efl_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_efl_lld.c index b8a6bdf9d..b204e22ea 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_efl_lld.c +++ b/os/hal/ports/STM32/STM32F4xx/hal_efl_lld.c @@ -1,820 +1,820 @@ -/* - ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_efl_lld.c - * @brief STM32F4xx Embedded Flash subsystem low level driver source. - * - * @addtogroup HAL_EFL - * @{ - */ - -#include - -#include "hal.h" - -#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define STM32_FLASH_LINE_SIZE (1 << STM32_FLASH_PSIZE) -#define STM32_FLASH_LINE_MASK (STM32_FLASH_LINE_SIZE - 1U) - -#define FLASH_PDKEY1 0x04152637U -#define FLASH_PDKEY2 0xFAFBFCFDU - -#define FLASH_KEY1 0x45670123U -#define FLASH_KEY2 0xCDEF89ABU - -#define FLASH_OPTKEY1 0x08192A3BU -#define FLASH_OPTKEY2 0x4C5D6E7FU - -#if !defined(FLASH_SR_OPERR) -#define FLASH_SR_OPERR FLASH_SR_SOP -#endif - -#if !defined(STM32_FLASH_DUAL_BANK_PERMANENT) -#define STM32_FLASH_DUAL_BANK_PERMANENT FALSE -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief EFL1 driver identifier. - */ -EFlashDriver EFLD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -#if defined(STM32F413xx) || defined(STM32F412xx) || defined(STM32F40_41xxx) \ - || defined(__DOXYGEN__) - -/* Sector table for 1.5M device. */ -static const flash_sector_descriptor_t efl_lld_sect1[STM32_FLASH1_SECTORS_TOTAL] = { - { 0, 16384}, /* Sector 0. */ - { 1 * 16384, 16384}, /* Sector 1. */ - { 2 * 16384, 16384}, /* Sector 2. */ - { 3 * 16384, 16384}, /* Sector 3. */ - { 4 * 16384, 65536}, /* Sector 4. */ - { 4 * 16384 + 65536, 131072}, /* Sector 5. */ - { 4 * 16384 + 65536 + 1 * 131072, 131072}, /* Sector 6. */ - { 4 * 16384 + 65536 + 2 * 131072, 131072}, /* Sector 7. */ - { 4 * 16384 + 65536 + 3 * 131072, 131072}, /* Sector 8. */ - { 4 * 16384 + 65536 + 4 * 131072, 131072}, /* Sector 9. */ - { 4 * 16384 + 65536 + 5 * 131072, 131072}, /* Sector 10. */ - { 4 * 16384 + 65536 + 6 * 131072, 131072}, /* Sector 11. */ - { 4 * 16384 + 65536 + 7 * 131072, 131072}, /* Sector 12. */ - { 4 * 16384 + 65536 + 8 * 131072, 131072}, /* Sector 13. */ - { 4 * 16384 + 65536 + 9 * 131072, 131072}, /* Sector 14. */ - { 4 * 16384 + 65536 + 10 * 131072, 131072} /* Sector 15. */ -}; - -/* Sector table for 1M device. */ -static const flash_sector_descriptor_t efl_lld_sect2[STM32_FLASH2_SECTORS_TOTAL] = { - { 0, 16384}, /* Sector 0. */ - { 1 * 16384, 16384}, /* Sector 1. */ - { 2 * 16384, 16384}, /* Sector 2. */ - { 3 * 16384, 16384}, /* Sector 3. */ - { 4 * 16384, 65536}, /* Sector 4. */ - { 4 * 16384 + 65536, 131072}, /* Sector 5. */ - { 4 * 16384 + 65536 + 1 * 131072, 131072}, /* Sector 6. */ - { 4 * 16384 + 65536 + 2 * 131072, 131072}, /* Sector 7. */ - { 4 * 16384 + 65536 + 3 * 131072, 131072}, /* Sector 8. */ - { 4 * 16384 + 65536 + 4 * 131072, 131072}, /* Sector 9. */ - { 4 * 16384 + 65536 + 5 * 131072, 131072}, /* Sector 10. */ - { 4 * 16384 + 65536 + 6 * 131072, 131072} /* Sector 11. */ -}; - -/* The descriptors for 1.5M device. */ -static const flash_descriptor_t efl_lld_size1[STM32_FLASH_NUMBER_OF_BANKS] = { - { /* Single bank organisation. */ - .attributes = FLASH_ATTR_ERASED_IS_ONE | - FLASH_ATTR_MEMORY_MAPPED, - .page_size = STM32_FLASH_LINE_SIZE, - .sectors_count = STM32_FLASH1_SECTORS_TOTAL, - .sectors = efl_lld_sect1, - .sectors_size = 0, - .address = (uint8_t *)FLASH_BASE, - .size = STM32_FLASH1_SIZE * STM32_FLASH_SIZE_SCALE - } -}; - -/* The descriptors for 1M device. */ -static const flash_descriptor_t efl_lld_size2[STM32_FLASH_NUMBER_OF_BANKS] = { - { /* Single bank organisation. */ - .attributes = FLASH_ATTR_ERASED_IS_ONE | - FLASH_ATTR_MEMORY_MAPPED, - .page_size = STM32_FLASH_LINE_SIZE, - .sectors_count = STM32_FLASH2_SECTORS_TOTAL, - .sectors = efl_lld_sect2, - .sectors_size = 0, - .address = (uint8_t *)FLASH_BASE, - .size = STM32_FLASH2_SIZE * STM32_FLASH_SIZE_SCALE - } -}; - -/* Table describing possible flash sizes and descriptors for this device. */ -static const efl_lld_size_t efl_lld_flash_sizes[] = { - { - .desc = efl_lld_size1 - }, - { - .desc = efl_lld_size2 - } -}; -#elif defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ - defined(__DOXYGEN__) - -/* Sector table for 1M device in SBM. */ -static const flash_sector_descriptor_t efl_lld_sect_1m_sbm[STM32_FLASH_SECTORS_TOTAL_1M_SBM] = { - { 0, 16384}, /* Sector 0. */ - { 1 * 16384, 16384}, /* Sector 1. */ - { 2 * 16384, 16384}, /* Sector 2. */ - { 3 * 16384, 16384}, /* Sector 3. */ - { 4 * 16384, 65536}, /* Sector 4. */ - { 4 * 16384 + 1 * 65536, 131072}, /* Sector 5. */ - { 4 * 16384 + 1 * 65536 + 1 * 131072, 131072}, /* Sector 6. */ - { 4 * 16384 + 1 * 65536 + 2 * 131072, 131072}, /* Sector 7. */ - { 4 * 16384 + 1 * 65536 + 3 * 131072, 131072}, /* Sector 8. */ - { 4 * 16384 + 1 * 65536 + 4 * 131072, 131072}, /* Sector 9. */ - { 4 * 16384 + 1 * 65536 + 5 * 131072, 131072}, /* Sector 10. */ - { 4 * 16384 + 1 * 65536 + 6 * 131072, 131072} /* Sector 11. */ -}; - -/* Sector table for 1M device in DBM. */ -static const flash_sector_descriptor_t efl_lld_sect_1m_dbm[STM32_FLASH_SECTORS_TOTAL_1M_DBM] = { - { 0, 16384}, /* Sector 0. */ - { 1 * 16384, 16384}, /* Sector 1. */ - { 2 * 16384, 16384}, /* Sector 2. */ - { 3 * 16384, 16384}, /* Sector 3. */ - { 4 * 16384, 65536}, /* Sector 4. */ - { 4 * 16384 + 1 * 65536, 131072}, /* Sector 5. */ - { 4 * 16384 + 1 * 65536 + 1 * 131072, 131072}, /* Sector 6. */ - { 4 * 16384 + 1 * 65536 + 2 * 131072, 131072}, /* Sector 7. */ - { 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */ - { 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */ - { 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */ - { 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */ - { 4 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 12. */ - { 5 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 13. */ - { 6 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 14. */ - { 7 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 15. */ - { 8 * 16384 + 1 * 65536 + 3 * 131072, 65536}, /* Sector 16. */ - { 8 * 16384 + 2 * 65536 + 3 * 131072, 131072}, /* Sector 17. */ - { 8 * 16384 + 2 * 65536 + 4 * 131072, 131072}, /* Sector 18. */ - { 8 * 16384 + 2 * 65536 + 5 * 131072, 131072} /* Sector 19. */ -}; - -/* Sector table for 2M device banks. */ -static const flash_sector_descriptor_t efl_lld_sect_2m[STM32_FLASH_SECTORS_TOTAL_2M] = { - { 0, 16384}, /* Sector 0. */ - { 1 * 16384, 16384}, /* Sector 1. */ - { 2 * 16384, 16384}, /* Sector 2. */ - { 3 * 16384, 16384}, /* Sector 3. */ - { 4 * 16384, 65536}, /* Sector 4. */ - { 4 * 16384 + 1 * 65536, 131072}, /* Sector 5. */ - { 4 * 16384 + 1 * 65536 + 1 * 131072, 131072}, /* Sector 6. */ - { 4 * 16384 + 1 * 65536 + 2 * 131072, 131072}, /* Sector 7. */ - { 4 * 16384 + 1 * 65536 + 3 * 131072, 131072}, /* Sector 8. */ - { 4 * 16384 + 1 * 65536 + 4 * 131072, 131072}, /* Sector 9. */ - { 4 * 16384 + 1 * 65536 + 5 * 131072, 131072}, /* Sector 10. */ - { 4 * 16384 + 1 * 65536 + 6 * 131072, 131072}, /* Sector 11. */ - { 4 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 12. */ - { 5 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 13. */ - { 6 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 14. */ - { 7 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 15. */ - { 8 * 16384 + 1 * 65536 + 7 * 131072, 65536}, /* Sector 16. */ - { 8 * 16384 + 2 * 65536 + 7 * 131072, 131072}, /* Sector 17. */ - { 8 * 16384 + 2 * 65536 + 8 * 131072, 131072}, /* Sector 18. */ - { 8 * 16384 + 2 * 65536 + 9 * 131072, 131072}, /* Sector 19. */ - { 8 * 16384 + 2 * 65536 + 10 * 131072, 131072}, /* Sector 20. */ - { 8 * 16384 + 2 * 65536 + 11 * 131072, 131072}, /* Sector 21. */ - { 8 * 16384 + 2 * 65536 + 12 * 131072, 131072}, /* Sector 22. */ - { 8 * 16384 + 2 * 65536 + 13 * 131072, 131072} /* Sector 23. */ -}; - -/* The descriptors for 1M device. */ -static const flash_descriptor_t efl_lld_size_1m[STM32_FLASH_NUMBER_OF_BANKS] = { - { /* Bank 1 (SBM) organisation. */ - .attributes = FLASH_ATTR_ERASED_IS_ONE | - FLASH_ATTR_MEMORY_MAPPED, - .page_size = STM32_FLASH_LINE_SIZE, - .sectors_count = STM32_FLASH_SECTORS_TOTAL_1M_SBM, - .sectors = efl_lld_sect_1m_sbm, - .sectors_size = 0, - .address = (uint8_t *)FLASH_BASE, - .size = STM32_FLASH_SIZE_1M * STM32_FLASH_SIZE_SCALE - }, - { /* Bank 1 & 2 (DBM) organisation. */ - .attributes = FLASH_ATTR_ERASED_IS_ONE | - FLASH_ATTR_MEMORY_MAPPED, - .page_size = STM32_FLASH_LINE_SIZE, - .sectors_count = STM32_FLASH_SECTORS_TOTAL_1M_DBM, - .sectors = efl_lld_sect_1m_dbm, - .sectors_size = 0, - .address = (uint8_t *)FLASH_BASE, - .size = STM32_FLASH_SIZE_1M * STM32_FLASH_SIZE_SCALE - } -}; - -/* The descriptors for 2M device. */ -static const flash_descriptor_t efl_lld_size_2m[STM32_FLASH_NUMBER_OF_BANKS] = { - { /* Dual bank organisation. */ - .attributes = FLASH_ATTR_ERASED_IS_ONE | - FLASH_ATTR_MEMORY_MAPPED, - .page_size = STM32_FLASH_LINE_SIZE, - .sectors_count = STM32_FLASH_SECTORS_TOTAL_2M, - .sectors = efl_lld_sect_2m, - .sectors_size = 0, - .address = (uint8_t *)FLASH_BASE, - .size = STM32_FLASH_SIZE_2M * STM32_FLASH_SIZE_SCALE - }, - { /* Dual bank organisation. */ - .attributes = FLASH_ATTR_ERASED_IS_ONE | - FLASH_ATTR_MEMORY_MAPPED, - .page_size = STM32_FLASH_LINE_SIZE, - .sectors_count = STM32_FLASH_SECTORS_TOTAL_2M, - .sectors = efl_lld_sect_2m, - .sectors_size = 0, - .address = (uint8_t *)FLASH_BASE, - .size = STM32_FLASH_SIZE_2M * STM32_FLASH_SIZE_SCALE - } -}; - -/* Table describing possible flash sizes and descriptors for this device. */ -static const efl_lld_size_t efl_lld_flash_sizes[] = { - { - .desc = efl_lld_size_1m - }, - { - .desc = efl_lld_size_2m - } -}; -#else -#error "This EFL driver does not support the selected device" -#endif - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static inline void stm32_flash_lock(EFlashDriver *eflp) { - - eflp->flash->CR |= FLASH_CR_LOCK; -} - -static inline void stm32_flash_unlock(EFlashDriver *eflp) { - - eflp->flash->KEYR |= FLASH_KEY1; - eflp->flash->KEYR |= FLASH_KEY2; -} - -static inline void stm32_flash_enable_pgm(EFlashDriver *eflp) { - - /* Set parallelism. */ - eflp->flash->CR &= ~FLASH_CR_PSIZE; - eflp->flash->CR |= STM32_FLASH_PSIZE << FLASH_CR_PSIZE_Pos; - - /* Enable programming. */ - eflp->flash->CR |= FLASH_CR_PG; -} - -static inline void stm32_flash_disable_pgm(EFlashDriver *eflp) { - - eflp->flash->CR &= ~FLASH_CR_PG; -} - -static inline void stm32_flash_clear_status(EFlashDriver *eflp) { - - eflp->flash->SR = 0x0000FFFFU; -} - -static inline void stm32_flash_wait_busy(EFlashDriver *eflp) { - - /* Wait for busy bit clear.*/ - while ((eflp->flash->SR & FLASH_SR_BSY) != 0U) { - } -} - -static inline size_t stm32_flash_get_size(void) { - return *(uint16_t*)((uint32_t) STM32_FLASH_SIZE_REGISTER) * STM32_FLASH_SIZE_SCALE; -} - -static inline bool stm32_flash_dual_bank(EFlashDriver *eflp) { - -#if STM32_FLASH_NUMBER_OF_BANKS > 1 - return ((eflp->flash->OPTCR & FLASH_OPTCR_DB1M) != 0U || STM32_FLASH_DUAL_BANK_PERMANENT); -#endif - (void)eflp; - return false; -} - -static inline flash_error_t stm32_flash_check_errors(EFlashDriver *eflp) { - uint32_t sr = eflp->flash->SR; - - /* Clearing error conditions.*/ - eflp->flash->SR = sr & 0x0000FFFFU; - - /* Some errors are only caught by assertion.*/ - osalDbgAssert((sr & 0) == 0U, "unexpected flash error"); - - /* Decoding relevant errors.*/ - if ((sr & FLASH_SR_WRPERR) != 0U) { - return FLASH_ERROR_HW_FAILURE; - } - - if ((sr & (FLASH_SR_PGAERR | FLASH_SR_PGPERR | FLASH_SR_OPERR)) != 0U) { - return eflp->state == FLASH_PGM ? FLASH_ERROR_PROGRAM : FLASH_ERROR_ERASE; - } - - return FLASH_NO_ERROR; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level Embedded Flash driver initialization. - * - * @notapi - */ -void efl_lld_init(void) { - - /* Driver initialization.*/ - eflObjectInit(&EFLD1); - EFLD1.flash = FLASH; - /* Find the size of the flash and set descriptor reference. */ - uint8_t i; - for (i = 0; i < (sizeof(efl_lld_flash_sizes) / sizeof(efl_lld_size_t)); i++) { - if (efl_lld_flash_sizes[i].desc->size == stm32_flash_get_size()) { - EFLD1.descriptor = efl_lld_flash_sizes[i].desc; - if (stm32_flash_dual_bank(&EFLD1)) { - /* Point to the dual bank descriptor. */ - EFLD1.descriptor++; - } - return; - } - } - osalDbgAssert(false, "invalid flash configuration"); -} - -/** - * @brief Configures and activates the Embedded Flash peripheral. - * - * @param[in] eflp pointer to a @p EFlashDriver structure - * - * @notapi - */ -void efl_lld_start(EFlashDriver *eflp) { - stm32_flash_unlock(eflp); - FLASH->CR = 0x00000000U; -} - -/** - * @brief Deactivates the Embedded Flash peripheral. - * - * @param[in] eflp pointer to a @p EFlashDriver structure - * - * @notapi - */ -void efl_lld_stop(EFlashDriver *eflp) { - - stm32_flash_lock(eflp); -} - -/** - * @brief Gets the flash descriptor structure. - * - * @param[in] ip pointer to a @p EFlashDriver instance - * @return A flash device descriptor. - * @retval Pointer to single bank if DBM not enabled. - * @retval Pointer to bank1 if DBM enabled. - * - * @notapi - */ -const flash_descriptor_t *efl_lld_get_descriptor(void *instance) { - EFlashDriver *devp = (EFlashDriver *)instance; - return devp->descriptor; -} - -/** - * @brief Read operation. - * - * @param[in] ip pointer to a @p EFlashDriver instance - * @param[in] offset offset within full flash address space - * @param[in] n number of bytes to be read - * @param[out] rp pointer to the data buffer - * @return An error code. - * @retval FLASH_NO_ERROR if there is no erase operation in progress. - * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. - * @retval FLASH_ERROR_READ if the read operation failed. - * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. - * - * @notapi - */ -flash_error_t efl_lld_read(void *instance, flash_offset_t offset, - size_t n, uint8_t *rp) { - EFlashDriver *devp = (EFlashDriver *)instance; - flash_error_t err = FLASH_NO_ERROR; - - osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U)); - - const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); - osalDbgCheck((size_t)offset + n <= (size_t)bank->size); - osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), - "invalid state"); - - /* No reading while erasing.*/ - if (devp->state == FLASH_ERASE) { - return FLASH_BUSY_ERASING; - } - - /* FLASH_READ state while the operation is performed.*/ - devp->state = FLASH_READ; - - /* Clearing error status bits.*/ - stm32_flash_clear_status(devp); - - /* Actual read implementation.*/ - memcpy((void *)rp, (const void *)efl_lld_get_descriptor(instance)->address - + offset, n); - -#if defined(FLASH_CR_RDERR) - /* Checking for errors after reading.*/ - if ((devp->flash->SR & FLASH_SR_RDERR) != 0U) { - err = FLASH_ERROR_READ; - } -#endif - - /* Ready state again.*/ - devp->state = FLASH_READY; - - return err; - -} - -/** - * @brief Program operation. - * @note Successive write operations are possible without the need of - * an erase when changing bits from one to zero. Writing one requires - * an erase operation. - * - * @param[in] ip pointer to a @p EFlashDriver instance - * @param[in] offset offset within full flash address space - * @param[in] n number of bytes to be programmed - * @param[in] pp pointer to the data buffer - * @return An error code. - * @retval FLASH_NO_ERROR if there is no erase operation in progress. - * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. - * @retval FLASH_ERROR_PROGRAM if the program operation failed. - * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. - * - * @notapi - */ -flash_error_t efl_lld_program(void *instance, flash_offset_t offset, - size_t n, const uint8_t *pp) { - EFlashDriver *devp = (EFlashDriver *)instance; - const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); - flash_error_t err = FLASH_NO_ERROR; - - osalDbgCheck((instance != NULL) && (pp != NULL) && (n > 0U)); - osalDbgCheck((size_t)offset + n <= (size_t)bank->size); - osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), - "invalid state"); - - /* No programming while erasing.*/ - if (devp->state == FLASH_ERASE) { - return FLASH_BUSY_ERASING; - } - - /* FLASH_PGM state while the operation is performed.*/ - devp->state = FLASH_PGM; - - /* Clearing error status bits.*/ - stm32_flash_clear_status(devp); - - /* Enabling PGM mode in the controller.*/ - stm32_flash_enable_pgm(devp); - - /* Actual program implementation.*/ - while (n > 0U) { - volatile uint32_t *address; - - /* Create an array of sufficient size to hold line(s). */ - union { - uint32_t w[STM32_FLASH_LINE_SIZE / sizeof(uint32_t)]; - uint16_t h[STM32_FLASH_LINE_SIZE / sizeof(uint16_t)]; - uint8_t b[STM32_FLASH_LINE_SIZE / sizeof(uint8_t)]; - } line; - - /* Unwritten bytes are initialized to all ones.*/ - uint8_t i; - for (i = 0; i < bank->page_size; i++) { - line.b[i] = 0xFF; - } - - /* Programming address aligned to flash lines.*/ - address = (volatile uint32_t *)(bank->address + - (offset & ~STM32_FLASH_LINE_MASK)); - - /* Copying data inside the prepared line(s).*/ - do { - line.b[offset & STM32_FLASH_LINE_MASK] = *pp; - offset++; - n--; - pp++; - } - while ((n > 0U) & ((offset & STM32_FLASH_LINE_MASK) != 0U)); - - /* Programming line according to parallelism.*/ - switch (STM32_FLASH_LINE_SIZE) { - case 1: - address[0] = line.b[0]; - break; - - case 2: - address[0] = line.h[0]; - break; - - case 4: - address[0] = line.w[0]; - break; - - case 8: - address[0] = line.w[0]; - address[1] = line.w[1]; - break; - - default: - osalDbgAssert(false, "invalid line size"); - break; - } - - stm32_flash_wait_busy(devp); - err = stm32_flash_check_errors(devp); - if (err != FLASH_NO_ERROR) { - break; - } - } - - /* Disabling PGM mode in the controller.*/ - stm32_flash_disable_pgm(devp); - - /* Ready state again.*/ - devp->state = FLASH_READY; - - return err; -} - -/** - * @brief Starts a whole-device erase operation. - * @note This function only erases the unused bank if in dual bank mode. The - * currently in use bank is not allowed since it is normally where the - * currently running program is executing from. - * Sectors on the in-use bank can be individually erased. - * - * @param[in] ip pointer to a @p EFlashDriver instance - * @return An error code. - * @retval FLASH_NO_ERROR if there is no erase operation in progress. - * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. - * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. - * - * @notapi - */ -flash_error_t efl_lld_start_erase_all(void *instance) { - EFlashDriver *devp = (EFlashDriver *)instance; - - osalDbgCheck(instance != NULL); - osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), - "invalid state"); - - /* No erasing while erasing.*/ - if (devp->state == FLASH_ERASE) { - return FLASH_BUSY_ERASING; - } - -#if defined(FLASH_CR_MER2) - /* If dual bank is active then mass erase bank2. */ - if (stm32_flash_dual_bank(devp)) { - - /* FLASH_ERASE state while the operation is performed.*/ - devp->state = FLASH_ERASE; - - /* Clearing error status bits.*/ - stm32_flash_clear_status(devp); - - /* Erase the currently unused bank, based on Flash Bank Mode */ - if ((SYSCFG->MEMRMP & SYSCFG_MEMRMP_UFB_MODE) != 0U) { - /* Bank 2 in use, erase Bank 1 */ - devp->flash->CR |= FLASH_CR_MER; - } - else { - /* Bank 1 in use, erase Bank 2 */ - devp->flash->CR |= FLASH_CR_MER2; - } - devp->flash->CR |= FLASH_CR_STRT; - return FLASH_NO_ERROR; - } -#endif - - /* Mass erase not allowed. */ - return FLASH_ERROR_UNIMPLEMENTED; -} - -/** - * @brief Starts an sector erase operation. - * - * @param[in] ip pointer to a @p EFlashDriver instance - * @param[in] sector sector to be erased - * this is an index within the total sectors - * in a flash bank - * @return An error code. - * @retval FLASH_NO_ERROR if there is no erase operation in progress. - * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. - * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. - * - * @notapi - */ -flash_error_t efl_lld_start_erase_sector(void *instance, - flash_sector_t sector) { - EFlashDriver *devp = (EFlashDriver *)instance; - const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); - osalDbgCheck(instance != NULL); - osalDbgCheck(sector < bank->sectors_count); - osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), - "invalid state"); - - /* No erasing while erasing.*/ - if (devp->state == FLASH_ERASE) { - return FLASH_BUSY_ERASING; - } - - /* FLASH_PGM state while the operation is performed.*/ - devp->state = FLASH_ERASE; - - /* Clearing error status bits.*/ - stm32_flash_clear_status(devp); - - /* Enable sector erase.*/ - devp->flash->CR |= FLASH_CR_SER; - - /* Mask off the sector and parallelism selection bits.*/ - devp->flash->CR &= ~FLASH_CR_SNB; - devp->flash->CR &= ~FLASH_CR_PSIZE; - -#if defined(FLASH_CR_MER2) - /* Adjust sector value for dual-bank devices - * For STM32F42x_43x devices (dual-bank), FLASH_CR_SNB values jump to 0b10000 - * for sectors 12 and up. - */ - if (sector >= 12) { - sector -= 12; - sector |= 0x10U; - } -#endif - - /* Set sector and parallelism. */ - devp->flash->CR |= (sector << FLASH_CR_SNB_Pos) | - (STM32_FLASH_PSIZE << FLASH_CR_PSIZE_Pos); - - /* Start the erase.*/ - devp->flash->CR |= FLASH_CR_STRT; - - return FLASH_NO_ERROR; -} - -/** - * @brief Queries the driver for erase operation progress. - * - * @param[in] instance pointer to a @p EFlashDriver instance - * @param[out] msec recommended time, in milliseconds, that - * should be spent before calling this - * function again, can be @p NULL - * @return An error code. - * @retval FLASH_NO_ERROR if there is no erase operation in progress. - * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. - * @retval FLASH_ERROR_ERASE if the erase operation failed. - * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. - * - * @api - */ -flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) { - EFlashDriver *devp = (EFlashDriver *)instance; - flash_error_t err; - - /* If there is an erase in progress then the device must be checked.*/ - if (devp->state == FLASH_ERASE) { - - /* Checking for operation in progress.*/ - if ((devp->flash->SR & FLASH_SR_BSY) == 0U) { - - /* Disabling the various erase control bits.*/ - devp->flash->CR &= ~(FLASH_CR_MER | -#if defined(FLASH_CR_MER2) - FLASH_CR_MER2 | -#endif - FLASH_CR_SER); - - /* No operation in progress, checking for errors.*/ - err = stm32_flash_check_errors(devp); - - /* Back to ready state.*/ - devp->state = FLASH_READY; - } - else { - /* Recommended time before polling again. This is a simplified - implementation.*/ - if (msec != NULL) { - *msec = (uint32_t)STM32_FLASH_WAIT_TIME_MS; - } - - err = FLASH_BUSY_ERASING; - } - } - else { - err = FLASH_NO_ERROR; - } - - return err; -} - -/** - * @brief Returns the erase state of a sector. - * - * @param[in] ip pointer to a @p EFlashDriver instance - * @param[in] sector sector to be verified - * @return An error code. - * @retval FLASH_NO_ERROR if the sector is erased. - * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. - * @retval FLASH_ERROR_VERIFY if the verify operation failed. - * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. - * - * @notapi - */ -flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) { - EFlashDriver *devp = (EFlashDriver *)instance; - uint32_t *address; - const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); - flash_error_t err = FLASH_NO_ERROR; - unsigned i; - - osalDbgCheck(instance != NULL); - osalDbgCheck(sector < bank->sectors_count); - osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), - "invalid state"); - - /* No verifying while erasing.*/ - if (devp->state == FLASH_ERASE) { - return FLASH_BUSY_ERASING; - } - - /* Address of the sector in the bank.*/ - address = (uint32_t *)(bank->address + - flashGetSectorOffset(getBaseFlash(devp), sector)); - - /* FLASH_READ state while the operation is performed.*/ - devp->state = FLASH_READ; - - /* Scanning the sector space.*/ - uint32_t sector_size = flashGetSectorSize(getBaseFlash(devp), sector); - for (i = 0U; i < sector_size / sizeof(uint32_t); i++) { - if (*address != 0xFFFFFFFFU) { - err = FLASH_ERROR_VERIFY; - break; - } - address++; - } - - /* Ready state again.*/ - devp->state = FLASH_READY; - - return err; -} - -#endif /* HAL_USE_EFL == TRUE */ - -/** @} */ +/* + ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_efl_lld.c + * @brief STM32F4xx Embedded Flash subsystem low level driver source. + * + * @addtogroup HAL_EFL + * @{ + */ + +#include + +#include "hal.h" + +#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define STM32_FLASH_LINE_SIZE (1 << STM32_FLASH_PSIZE) +#define STM32_FLASH_LINE_MASK (STM32_FLASH_LINE_SIZE - 1U) + +#define FLASH_PDKEY1 0x04152637U +#define FLASH_PDKEY2 0xFAFBFCFDU + +#define FLASH_KEY1 0x45670123U +#define FLASH_KEY2 0xCDEF89ABU + +#define FLASH_OPTKEY1 0x08192A3BU +#define FLASH_OPTKEY2 0x4C5D6E7FU + +#if !defined(FLASH_SR_OPERR) +#define FLASH_SR_OPERR FLASH_SR_SOP +#endif + +#if !defined(STM32_FLASH_DUAL_BANK_PERMANENT) +#define STM32_FLASH_DUAL_BANK_PERMANENT FALSE +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EFL1 driver identifier. + */ +EFlashDriver EFLD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +#if defined(STM32F413xx) || defined(STM32F412xx) || \ + defined(STM32F40_41xxx) || defined(__DOXYGEN__) + +/* Sector table for 1.5M device. */ +static const flash_sector_descriptor_t efl_lld_sect1[STM32_FLASH1_SECTORS_TOTAL] = { + { 0, 16384}, /* Sector 0. */ + { 1 * 16384, 16384}, /* Sector 1. */ + { 2 * 16384, 16384}, /* Sector 2. */ + { 3 * 16384, 16384}, /* Sector 3. */ + { 4 * 16384, 65536}, /* Sector 4. */ + { 4 * 16384 + 65536, 131072}, /* Sector 5. */ + { 4 * 16384 + 65536 + 1 * 131072, 131072}, /* Sector 6. */ + { 4 * 16384 + 65536 + 2 * 131072, 131072}, /* Sector 7. */ + { 4 * 16384 + 65536 + 3 * 131072, 131072}, /* Sector 8. */ + { 4 * 16384 + 65536 + 4 * 131072, 131072}, /* Sector 9. */ + { 4 * 16384 + 65536 + 5 * 131072, 131072}, /* Sector 10. */ + { 4 * 16384 + 65536 + 6 * 131072, 131072}, /* Sector 11. */ + { 4 * 16384 + 65536 + 7 * 131072, 131072}, /* Sector 12. */ + { 4 * 16384 + 65536 + 8 * 131072, 131072}, /* Sector 13. */ + { 4 * 16384 + 65536 + 9 * 131072, 131072}, /* Sector 14. */ + { 4 * 16384 + 65536 + 10 * 131072, 131072} /* Sector 15. */ +}; + +/* Sector table for 1M device. */ +static const flash_sector_descriptor_t efl_lld_sect2[STM32_FLASH2_SECTORS_TOTAL] = { + { 0, 16384}, /* Sector 0. */ + { 1 * 16384, 16384}, /* Sector 1. */ + { 2 * 16384, 16384}, /* Sector 2. */ + { 3 * 16384, 16384}, /* Sector 3. */ + { 4 * 16384, 65536}, /* Sector 4. */ + { 4 * 16384 + 65536, 131072}, /* Sector 5. */ + { 4 * 16384 + 65536 + 1 * 131072, 131072}, /* Sector 6. */ + { 4 * 16384 + 65536 + 2 * 131072, 131072}, /* Sector 7. */ + { 4 * 16384 + 65536 + 3 * 131072, 131072}, /* Sector 8. */ + { 4 * 16384 + 65536 + 4 * 131072, 131072}, /* Sector 9. */ + { 4 * 16384 + 65536 + 5 * 131072, 131072}, /* Sector 10. */ + { 4 * 16384 + 65536 + 6 * 131072, 131072} /* Sector 11. */ +}; + +/* The descriptors for 1.5M device. */ +static const flash_descriptor_t efl_lld_size1[STM32_FLASH_NUMBER_OF_BANKS] = { + { /* Single bank organisation. */ + .attributes = FLASH_ATTR_ERASED_IS_ONE | + FLASH_ATTR_MEMORY_MAPPED, + .page_size = STM32_FLASH_LINE_SIZE, + .sectors_count = STM32_FLASH1_SECTORS_TOTAL, + .sectors = efl_lld_sect1, + .sectors_size = 0, + .address = (uint8_t *)FLASH_BASE, + .size = STM32_FLASH1_SIZE * STM32_FLASH_SIZE_SCALE + } +}; + +/* The descriptors for 1M device. */ +static const flash_descriptor_t efl_lld_size2[STM32_FLASH_NUMBER_OF_BANKS] = { + { /* Single bank organisation. */ + .attributes = FLASH_ATTR_ERASED_IS_ONE | + FLASH_ATTR_MEMORY_MAPPED, + .page_size = STM32_FLASH_LINE_SIZE, + .sectors_count = STM32_FLASH2_SECTORS_TOTAL, + .sectors = efl_lld_sect2, + .sectors_size = 0, + .address = (uint8_t *)FLASH_BASE, + .size = STM32_FLASH2_SIZE * STM32_FLASH_SIZE_SCALE + } +}; + +/* Table describing possible flash sizes and descriptors for this device. */ +static const efl_lld_size_t efl_lld_flash_sizes[] = { + { + .desc = efl_lld_size1 + }, + { + .desc = efl_lld_size2 + } +}; +#elif defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ + defined(__DOXYGEN__) + +/* Sector table for 1M device in SBM. */ +static const flash_sector_descriptor_t efl_lld_sect_1m_sbm[STM32_FLASH_SECTORS_TOTAL_1M_SBM] = { + { 0, 16384}, /* Sector 0. */ + { 1 * 16384, 16384}, /* Sector 1. */ + { 2 * 16384, 16384}, /* Sector 2. */ + { 3 * 16384, 16384}, /* Sector 3. */ + { 4 * 16384, 65536}, /* Sector 4. */ + { 4 * 16384 + 1 * 65536, 131072}, /* Sector 5. */ + { 4 * 16384 + 1 * 65536 + 1 * 131072, 131072}, /* Sector 6. */ + { 4 * 16384 + 1 * 65536 + 2 * 131072, 131072}, /* Sector 7. */ + { 4 * 16384 + 1 * 65536 + 3 * 131072, 131072}, /* Sector 8. */ + { 4 * 16384 + 1 * 65536 + 4 * 131072, 131072}, /* Sector 9. */ + { 4 * 16384 + 1 * 65536 + 5 * 131072, 131072}, /* Sector 10. */ + { 4 * 16384 + 1 * 65536 + 6 * 131072, 131072} /* Sector 11. */ +}; + +/* Sector table for 1M device in DBM. */ +static const flash_sector_descriptor_t efl_lld_sect_1m_dbm[STM32_FLASH_SECTORS_TOTAL_1M_DBM] = { + { 0, 16384}, /* Sector 0. */ + { 1 * 16384, 16384}, /* Sector 1. */ + { 2 * 16384, 16384}, /* Sector 2. */ + { 3 * 16384, 16384}, /* Sector 3. */ + { 4 * 16384, 65536}, /* Sector 4. */ + { 4 * 16384 + 1 * 65536, 131072}, /* Sector 5. */ + { 4 * 16384 + 1 * 65536 + 1 * 131072, 131072}, /* Sector 6. */ + { 4 * 16384 + 1 * 65536 + 2 * 131072, 131072}, /* Sector 7. */ + { 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */ + { 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */ + { 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */ + { 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */ + { 4 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 12. */ + { 5 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 13. */ + { 6 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 14. */ + { 7 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 15. */ + { 8 * 16384 + 1 * 65536 + 3 * 131072, 65536}, /* Sector 16. */ + { 8 * 16384 + 2 * 65536 + 3 * 131072, 131072}, /* Sector 17. */ + { 8 * 16384 + 2 * 65536 + 4 * 131072, 131072}, /* Sector 18. */ + { 8 * 16384 + 2 * 65536 + 5 * 131072, 131072} /* Sector 19. */ +}; + +/* Sector table for 2M device banks. */ +static const flash_sector_descriptor_t efl_lld_sect_2m[STM32_FLASH_SECTORS_TOTAL_2M] = { + { 0, 16384}, /* Sector 0. */ + { 1 * 16384, 16384}, /* Sector 1. */ + { 2 * 16384, 16384}, /* Sector 2. */ + { 3 * 16384, 16384}, /* Sector 3. */ + { 4 * 16384, 65536}, /* Sector 4. */ + { 4 * 16384 + 1 * 65536, 131072}, /* Sector 5. */ + { 4 * 16384 + 1 * 65536 + 1 * 131072, 131072}, /* Sector 6. */ + { 4 * 16384 + 1 * 65536 + 2 * 131072, 131072}, /* Sector 7. */ + { 4 * 16384 + 1 * 65536 + 3 * 131072, 131072}, /* Sector 8. */ + { 4 * 16384 + 1 * 65536 + 4 * 131072, 131072}, /* Sector 9. */ + { 4 * 16384 + 1 * 65536 + 5 * 131072, 131072}, /* Sector 10. */ + { 4 * 16384 + 1 * 65536 + 6 * 131072, 131072}, /* Sector 11. */ + { 4 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 12. */ + { 5 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 13. */ + { 6 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 14. */ + { 7 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 15. */ + { 8 * 16384 + 1 * 65536 + 7 * 131072, 65536}, /* Sector 16. */ + { 8 * 16384 + 2 * 65536 + 7 * 131072, 131072}, /* Sector 17. */ + { 8 * 16384 + 2 * 65536 + 8 * 131072, 131072}, /* Sector 18. */ + { 8 * 16384 + 2 * 65536 + 9 * 131072, 131072}, /* Sector 19. */ + { 8 * 16384 + 2 * 65536 + 10 * 131072, 131072}, /* Sector 20. */ + { 8 * 16384 + 2 * 65536 + 11 * 131072, 131072}, /* Sector 21. */ + { 8 * 16384 + 2 * 65536 + 12 * 131072, 131072}, /* Sector 22. */ + { 8 * 16384 + 2 * 65536 + 13 * 131072, 131072} /* Sector 23. */ +}; + +/* The descriptors for 1M device. */ +static const flash_descriptor_t efl_lld_size_1m[STM32_FLASH_NUMBER_OF_BANKS] = { + { /* Bank 1 (SBM) organisation. */ + .attributes = FLASH_ATTR_ERASED_IS_ONE | + FLASH_ATTR_MEMORY_MAPPED, + .page_size = STM32_FLASH_LINE_SIZE, + .sectors_count = STM32_FLASH_SECTORS_TOTAL_1M_SBM, + .sectors = efl_lld_sect_1m_sbm, + .sectors_size = 0, + .address = (uint8_t *)FLASH_BASE, + .size = STM32_FLASH_SIZE_1M * STM32_FLASH_SIZE_SCALE + }, + { /* Bank 1 & 2 (DBM) organisation. */ + .attributes = FLASH_ATTR_ERASED_IS_ONE | + FLASH_ATTR_MEMORY_MAPPED, + .page_size = STM32_FLASH_LINE_SIZE, + .sectors_count = STM32_FLASH_SECTORS_TOTAL_1M_DBM, + .sectors = efl_lld_sect_1m_dbm, + .sectors_size = 0, + .address = (uint8_t *)FLASH_BASE, + .size = STM32_FLASH_SIZE_1M * STM32_FLASH_SIZE_SCALE + } +}; + +/* The descriptors for 2M device. */ +static const flash_descriptor_t efl_lld_size_2m[STM32_FLASH_NUMBER_OF_BANKS] = { + { /* Dual bank organisation. */ + .attributes = FLASH_ATTR_ERASED_IS_ONE | + FLASH_ATTR_MEMORY_MAPPED, + .page_size = STM32_FLASH_LINE_SIZE, + .sectors_count = STM32_FLASH_SECTORS_TOTAL_2M, + .sectors = efl_lld_sect_2m, + .sectors_size = 0, + .address = (uint8_t *)FLASH_BASE, + .size = STM32_FLASH_SIZE_2M * STM32_FLASH_SIZE_SCALE + }, + { /* Dual bank organisation. */ + .attributes = FLASH_ATTR_ERASED_IS_ONE | + FLASH_ATTR_MEMORY_MAPPED, + .page_size = STM32_FLASH_LINE_SIZE, + .sectors_count = STM32_FLASH_SECTORS_TOTAL_2M, + .sectors = efl_lld_sect_2m, + .sectors_size = 0, + .address = (uint8_t *)FLASH_BASE, + .size = STM32_FLASH_SIZE_2M * STM32_FLASH_SIZE_SCALE + } +}; + +/* Table describing possible flash sizes and descriptors for this device. */ +static const efl_lld_size_t efl_lld_flash_sizes[] = { + { + .desc = efl_lld_size_1m + }, + { + .desc = efl_lld_size_2m + } +}; +#else +#error "This EFL driver does not support the selected device" +#endif + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void stm32_flash_lock(EFlashDriver *eflp) { + + eflp->flash->CR |= FLASH_CR_LOCK; +} + +static inline void stm32_flash_unlock(EFlashDriver *eflp) { + + eflp->flash->KEYR |= FLASH_KEY1; + eflp->flash->KEYR |= FLASH_KEY2; +} + +static inline void stm32_flash_enable_pgm(EFlashDriver *eflp) { + + /* Set parallelism. */ + eflp->flash->CR &= ~FLASH_CR_PSIZE; + eflp->flash->CR |= STM32_FLASH_PSIZE << FLASH_CR_PSIZE_Pos; + + /* Enable programming. */ + eflp->flash->CR |= FLASH_CR_PG; +} + +static inline void stm32_flash_disable_pgm(EFlashDriver *eflp) { + + eflp->flash->CR &= ~FLASH_CR_PG; +} + +static inline void stm32_flash_clear_status(EFlashDriver *eflp) { + + eflp->flash->SR = 0x0000FFFFU; +} + +static inline void stm32_flash_wait_busy(EFlashDriver *eflp) { + + /* Wait for busy bit clear.*/ + while ((eflp->flash->SR & FLASH_SR_BSY) != 0U) { + } +} + +static inline size_t stm32_flash_get_size(void) { + return *(uint16_t*)((uint32_t) STM32_FLASH_SIZE_REGISTER) * STM32_FLASH_SIZE_SCALE; +} + +static inline bool stm32_flash_dual_bank(EFlashDriver *eflp) { + +#if STM32_FLASH_NUMBER_OF_BANKS > 1 + return ((eflp->flash->OPTCR & FLASH_OPTCR_DB1M) != 0U || STM32_FLASH_DUAL_BANK_PERMANENT); +#endif + (void)eflp; + return false; +} + +static inline flash_error_t stm32_flash_check_errors(EFlashDriver *eflp) { + uint32_t sr = eflp->flash->SR; + + /* Clearing error conditions.*/ + eflp->flash->SR = sr & 0x0000FFFFU; + + /* Some errors are only caught by assertion.*/ + osalDbgAssert((sr & 0) == 0U, "unexpected flash error"); + + /* Decoding relevant errors.*/ + if ((sr & FLASH_SR_WRPERR) != 0U) { + return FLASH_ERROR_HW_FAILURE; + } + + if ((sr & (FLASH_SR_PGAERR | FLASH_SR_PGPERR | FLASH_SR_OPERR)) != 0U) { + return eflp->state == FLASH_PGM ? FLASH_ERROR_PROGRAM : FLASH_ERROR_ERASE; + } + + return FLASH_NO_ERROR; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level Embedded Flash driver initialization. + * + * @notapi + */ +void efl_lld_init(void) { + + /* Driver initialization.*/ + eflObjectInit(&EFLD1); + EFLD1.flash = FLASH; + /* Find the size of the flash and set descriptor reference. */ + uint8_t i; + for (i = 0; i < (sizeof(efl_lld_flash_sizes) / sizeof(efl_lld_size_t)); i++) { + if (efl_lld_flash_sizes[i].desc->size == stm32_flash_get_size()) { + EFLD1.descriptor = efl_lld_flash_sizes[i].desc; + if (stm32_flash_dual_bank(&EFLD1)) { + /* Point to the dual bank descriptor. */ + EFLD1.descriptor++; + } + return; + } + } + osalDbgAssert(false, "invalid flash configuration"); +} + +/** + * @brief Configures and activates the Embedded Flash peripheral. + * + * @param[in] eflp pointer to a @p EFlashDriver structure + * + * @notapi + */ +void efl_lld_start(EFlashDriver *eflp) { + stm32_flash_unlock(eflp); + FLASH->CR = 0x00000000U; +} + +/** + * @brief Deactivates the Embedded Flash peripheral. + * + * @param[in] eflp pointer to a @p EFlashDriver structure + * + * @notapi + */ +void efl_lld_stop(EFlashDriver *eflp) { + + stm32_flash_lock(eflp); +} + +/** + * @brief Gets the flash descriptor structure. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @return A flash device descriptor. + * @retval Pointer to single bank if DBM not enabled. + * @retval Pointer to bank1 if DBM enabled. + * + * @notapi + */ +const flash_descriptor_t *efl_lld_get_descriptor(void *instance) { + EFlashDriver *devp = (EFlashDriver *)instance; + return devp->descriptor; +} + +/** + * @brief Read operation. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] offset offset within full flash address space + * @param[in] n number of bytes to be read + * @param[out] rp pointer to the data buffer + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_READ if the read operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_read(void *instance, flash_offset_t offset, + size_t n, uint8_t *rp) { + EFlashDriver *devp = (EFlashDriver *)instance; + flash_error_t err = FLASH_NO_ERROR; + + osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U)); + + const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); + osalDbgCheck((size_t)offset + n <= (size_t)bank->size); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No reading while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* FLASH_READ state while the operation is performed.*/ + devp->state = FLASH_READ; + + /* Clearing error status bits.*/ + stm32_flash_clear_status(devp); + + /* Actual read implementation.*/ + memcpy((void *)rp, (const void *)efl_lld_get_descriptor(instance)->address + + offset, n); + +#if defined(FLASH_CR_RDERR) + /* Checking for errors after reading.*/ + if ((devp->flash->SR & FLASH_SR_RDERR) != 0U) { + err = FLASH_ERROR_READ; + } +#endif + + /* Ready state again.*/ + devp->state = FLASH_READY; + + return err; + +} + +/** + * @brief Program operation. + * @note Successive write operations are possible without the need of + * an erase when changing bits from one to zero. Writing one requires + * an erase operation. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] offset offset within full flash address space + * @param[in] n number of bytes to be programmed + * @param[in] pp pointer to the data buffer + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_PROGRAM if the program operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_program(void *instance, flash_offset_t offset, + size_t n, const uint8_t *pp) { + EFlashDriver *devp = (EFlashDriver *)instance; + const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); + flash_error_t err = FLASH_NO_ERROR; + + osalDbgCheck((instance != NULL) && (pp != NULL) && (n > 0U)); + osalDbgCheck((size_t)offset + n <= (size_t)bank->size); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No programming while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* FLASH_PGM state while the operation is performed.*/ + devp->state = FLASH_PGM; + + /* Clearing error status bits.*/ + stm32_flash_clear_status(devp); + + /* Enabling PGM mode in the controller.*/ + stm32_flash_enable_pgm(devp); + + /* Actual program implementation.*/ + while (n > 0U) { + volatile uint32_t *address; + + /* Create an array of sufficient size to hold line(s). */ + union { + uint32_t w[STM32_FLASH_LINE_SIZE / sizeof(uint32_t)]; + uint16_t h[STM32_FLASH_LINE_SIZE / sizeof(uint16_t)]; + uint8_t b[STM32_FLASH_LINE_SIZE / sizeof(uint8_t)]; + } line; + + /* Unwritten bytes are initialized to all ones.*/ + uint8_t i; + for (i = 0; i < bank->page_size; i++) { + line.b[i] = 0xFF; + } + + /* Programming address aligned to flash lines.*/ + address = (volatile uint32_t *)(bank->address + + (offset & ~STM32_FLASH_LINE_MASK)); + + /* Copying data inside the prepared line(s).*/ + do { + line.b[offset & STM32_FLASH_LINE_MASK] = *pp; + offset++; + n--; + pp++; + } + while ((n > 0U) & ((offset & STM32_FLASH_LINE_MASK) != 0U)); + + /* Programming line according to parallelism.*/ + switch (STM32_FLASH_LINE_SIZE) { + case 1: + address[0] = line.b[0]; + break; + + case 2: + address[0] = line.h[0]; + break; + + case 4: + address[0] = line.w[0]; + break; + + case 8: + address[0] = line.w[0]; + address[1] = line.w[1]; + break; + + default: + osalDbgAssert(false, "invalid line size"); + break; + } + + stm32_flash_wait_busy(devp); + err = stm32_flash_check_errors(devp); + if (err != FLASH_NO_ERROR) { + break; + } + } + + /* Disabling PGM mode in the controller.*/ + stm32_flash_disable_pgm(devp); + + /* Ready state again.*/ + devp->state = FLASH_READY; + + return err; +} + +/** + * @brief Starts a whole-device erase operation. + * @note This function only erases the unused bank if in dual bank mode. The + * currently in use bank is not allowed since it is normally where the + * currently running program is executing from. + * Sectors on the in-use bank can be individually erased. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_start_erase_all(void *instance) { + EFlashDriver *devp = (EFlashDriver *)instance; + + osalDbgCheck(instance != NULL); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No erasing while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + +#if defined(FLASH_CR_MER2) + /* If dual bank is active then mass erase bank2. */ + if (stm32_flash_dual_bank(devp)) { + + /* FLASH_ERASE state while the operation is performed.*/ + devp->state = FLASH_ERASE; + + /* Clearing error status bits.*/ + stm32_flash_clear_status(devp); + + /* Erase the currently unused bank, based on Flash Bank Mode */ + if ((SYSCFG->MEMRMP & SYSCFG_MEMRMP_UFB_MODE) != 0U) { + /* Bank 2 in use, erase Bank 1 */ + devp->flash->CR |= FLASH_CR_MER; + } + else { + /* Bank 1 in use, erase Bank 2 */ + devp->flash->CR |= FLASH_CR_MER2; + } + devp->flash->CR |= FLASH_CR_STRT; + return FLASH_NO_ERROR; + } +#endif + + /* Mass erase not allowed. */ + return FLASH_ERROR_UNIMPLEMENTED; +} + +/** + * @brief Starts an sector erase operation. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] sector sector to be erased + * this is an index within the total sectors + * in a flash bank + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_start_erase_sector(void *instance, + flash_sector_t sector) { + EFlashDriver *devp = (EFlashDriver *)instance; + const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); + osalDbgCheck(instance != NULL); + osalDbgCheck(sector < bank->sectors_count); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No erasing while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* FLASH_PGM state while the operation is performed.*/ + devp->state = FLASH_ERASE; + + /* Clearing error status bits.*/ + stm32_flash_clear_status(devp); + + /* Enable sector erase.*/ + devp->flash->CR |= FLASH_CR_SER; + + /* Mask off the sector and parallelism selection bits.*/ + devp->flash->CR &= ~FLASH_CR_SNB; + devp->flash->CR &= ~FLASH_CR_PSIZE; + +#if defined(FLASH_CR_MER2) + /* Adjust sector value for dual-bank devices + * For STM32F42x_43x devices (dual-bank), FLASH_CR_SNB values jump to 0b10000 + * for sectors 12 and up. + */ + if (sector >= 12) { + sector -= 12; + sector |= 0x10U; + } +#endif + + /* Set sector and parallelism. */ + devp->flash->CR |= (sector << FLASH_CR_SNB_Pos) | + (STM32_FLASH_PSIZE << FLASH_CR_PSIZE_Pos); + + /* Start the erase.*/ + devp->flash->CR |= FLASH_CR_STRT; + + return FLASH_NO_ERROR; +} + +/** + * @brief Queries the driver for erase operation progress. + * + * @param[in] instance pointer to a @p EFlashDriver instance + * @param[out] msec recommended time, in milliseconds, that + * should be spent before calling this + * function again, can be @p NULL + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_ERASE if the erase operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @api + */ +flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) { + EFlashDriver *devp = (EFlashDriver *)instance; + flash_error_t err; + + /* If there is an erase in progress then the device must be checked.*/ + if (devp->state == FLASH_ERASE) { + + /* Checking for operation in progress.*/ + if ((devp->flash->SR & FLASH_SR_BSY) == 0U) { + + /* Disabling the various erase control bits.*/ + devp->flash->CR &= ~(FLASH_CR_MER | +#if defined(FLASH_CR_MER2) + FLASH_CR_MER2 | +#endif + FLASH_CR_SER); + + /* No operation in progress, checking for errors.*/ + err = stm32_flash_check_errors(devp); + + /* Back to ready state.*/ + devp->state = FLASH_READY; + } + else { + /* Recommended time before polling again. This is a simplified + implementation.*/ + if (msec != NULL) { + *msec = (uint32_t)STM32_FLASH_WAIT_TIME_MS; + } + + err = FLASH_BUSY_ERASING; + } + } + else { + err = FLASH_NO_ERROR; + } + + return err; +} + +/** + * @brief Returns the erase state of a sector. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] sector sector to be verified + * @return An error code. + * @retval FLASH_NO_ERROR if the sector is erased. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_VERIFY if the verify operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) { + EFlashDriver *devp = (EFlashDriver *)instance; + uint32_t *address; + const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); + flash_error_t err = FLASH_NO_ERROR; + unsigned i; + + osalDbgCheck(instance != NULL); + osalDbgCheck(sector < bank->sectors_count); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No verifying while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* Address of the sector in the bank.*/ + address = (uint32_t *)(bank->address + + flashGetSectorOffset(getBaseFlash(devp), sector)); + + /* FLASH_READ state while the operation is performed.*/ + devp->state = FLASH_READ; + + /* Scanning the sector space.*/ + uint32_t sector_size = flashGetSectorSize(getBaseFlash(devp), sector); + for (i = 0U; i < sector_size / sizeof(uint32_t); i++) { + if (*address != 0xFFFFFFFFU) { + err = FLASH_ERROR_VERIFY; + break; + } + address++; + } + + /* Ready state again.*/ + devp->state = FLASH_READY; + + return err; +} + +#endif /* HAL_USE_EFL == TRUE */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F4xx/hal_efl_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_efl_lld.h index 40ee5e346..1f3fd1a7a 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_efl_lld.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_efl_lld.h @@ -1,158 +1,158 @@ -/* - ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_efl_lld.h - * @brief STM32F4xx Embedded Flash subsystem low level driver header. - * - * @addtogroup HAL_EFL - * @{ - */ - -#ifndef HAL_EFL_LLD_H -#define HAL_EFL_LLD_H - -#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name STM32F412/413 EFL driver configuration options - * @{ - */ -/** - * @brief Suggested wait time during erase operations polling. - */ -#if !defined(STM32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__) -#define STM32_FLASH_WAIT_TIME_MS 5 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if defined(STM32F413xx) || defined(STM32F412xx) || defined(STM32F40_41xxx) \ - || defined(__DOXYGEN__) - -/* Flash size register. */ -#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22 -#define STM32_FLASH_SIZE_SCALE 1024U - -/* - * Device flash size... - * - */ -#define STM32_FLASH_NUMBER_OF_BANKS 1 -#define STM32_FLASH1_SIZE 1536U -#define STM32_FLASH2_SIZE 1024U -#define STM32_FLASH1_SECTORS_TOTAL 16 -#define STM32_FLASH2_SECTORS_TOTAL 12 - -#elif defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ - defined(__DOXYGEN__) - -/* Flash size register. */ -#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22 -#define STM32_FLASH_SIZE_SCALE 1024U - -/* - * Device flash size is: - * 1M for STM32F4x7/4x9 suffix G devices - * 2M for STM32F4x7/4x9 suffix I devices. - * - * For 1M devices SBM is organised as 16K x 4 + 64K + 128K x 7 sectors. - * For 1M devices DBM is organised as 16K x 4 + 64K + 128K x 3 sectors per bank. - * - * For 2M devices are organised as 16K x 4 + 64K + 128K x 7 sectors per bank. - */ -#define STM32_FLASH_NUMBER_OF_BANKS 2 -#define STM32_FLASH_SIZE_1M 1024U -#define STM32_FLASH_SIZE_2M 2048U -#define STM32_FLASH_SECTORS_TOTAL_1M_SBM 12 -#define STM32_FLASH_SECTORS_TOTAL_1M_DBM 20 -#define STM32_FLASH_SECTORS_TOTAL_2M 24 -#else -#error "This EFL driver does not support the selected device" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/* A flash size declaration. */ -typedef struct { - const flash_descriptor_t* desc; -} efl_lld_size_t; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Low level fields of the embedded flash driver structure. - */ -#define efl_lld_driver_fields \ - /* Flash registers.*/ \ - FLASH_TypeDef *flash; \ - const flash_descriptor_t *descriptor; - -/** - * @brief Low level fields of the embedded flash configuration structure. - */ -#define efl_lld_config_fields \ - /* Dummy configuration, it is not needed.*/ \ - uint32_t dummy - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern EFlashDriver EFLD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void efl_lld_init(void); - void efl_lld_start(EFlashDriver *eflp); - void efl_lld_stop(EFlashDriver *eflp); - const flash_descriptor_t *efl_lld_get_descriptor(void *instance); - flash_error_t efl_lld_read(void *instance, flash_offset_t offset, - size_t n, uint8_t *rp); - flash_error_t efl_lld_program(void *instance, flash_offset_t offset, - size_t n, const uint8_t *pp); - flash_error_t efl_lld_start_erase_all(void *instance); - flash_error_t efl_lld_start_erase_sector(void *instance, - flash_sector_t sector); - flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec); - flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EFL == TRUE */ - -#endif /* HAL_EFL_LLD_H */ - -/** @} */ +/* + ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_efl_lld.h + * @brief STM32F4xx Embedded Flash subsystem low level driver header. + * + * @addtogroup HAL_EFL + * @{ + */ + +#ifndef HAL_EFL_LLD_H +#define HAL_EFL_LLD_H + +#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name STM32F412/413 EFL driver configuration options + * @{ + */ +/** + * @brief Suggested wait time during erase operations polling. + */ +#if !defined(STM32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__) +#define STM32_FLASH_WAIT_TIME_MS 5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if defined(STM32F413xx) || defined(STM32F412xx) || \ + defined(STM32F40_41xxx) || defined(__DOXYGEN__) + +/* Flash size register. */ +#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22 +#define STM32_FLASH_SIZE_SCALE 1024U + +/* + * Device flash size... + * + */ +#define STM32_FLASH_NUMBER_OF_BANKS 1 +#define STM32_FLASH1_SIZE 1536U +#define STM32_FLASH2_SIZE 1024U +#define STM32_FLASH1_SECTORS_TOTAL 16 +#define STM32_FLASH2_SECTORS_TOTAL 12 + +#elif defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ + defined(__DOXYGEN__) + +/* Flash size register. */ +#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22 +#define STM32_FLASH_SIZE_SCALE 1024U + +/* + * Device flash size is: + * 1M for STM32F4x7/4x9 suffix G devices + * 2M for STM32F4x7/4x9 suffix I devices. + * + * For 1M devices SBM is organised as 16K x 4 + 64K + 128K x 7 sectors. + * For 1M devices DBM is organised as 16K x 4 + 64K + 128K x 3 sectors per bank. + * + * For 2M devices are organised as 16K x 4 + 64K + 128K x 7 sectors per bank. + */ +#define STM32_FLASH_NUMBER_OF_BANKS 2 +#define STM32_FLASH_SIZE_1M 1024U +#define STM32_FLASH_SIZE_2M 2048U +#define STM32_FLASH_SECTORS_TOTAL_1M_SBM 12 +#define STM32_FLASH_SECTORS_TOTAL_1M_DBM 20 +#define STM32_FLASH_SECTORS_TOTAL_2M 24 +#else +#error "This EFL driver does not support the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/* A flash size declaration. */ +typedef struct { + const flash_descriptor_t* desc; +} efl_lld_size_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level fields of the embedded flash driver structure. + */ +#define efl_lld_driver_fields \ + /* Flash registers.*/ \ + FLASH_TypeDef *flash; \ + const flash_descriptor_t *descriptor; + +/** + * @brief Low level fields of the embedded flash configuration structure. + */ +#define efl_lld_config_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint32_t dummy + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EFlashDriver EFLD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void efl_lld_init(void); + void efl_lld_start(EFlashDriver *eflp); + void efl_lld_stop(EFlashDriver *eflp); + const flash_descriptor_t *efl_lld_get_descriptor(void *instance); + flash_error_t efl_lld_read(void *instance, flash_offset_t offset, + size_t n, uint8_t *rp); + flash_error_t efl_lld_program(void *instance, flash_offset_t offset, + size_t n, const uint8_t *pp); + flash_error_t efl_lld_start_erase_all(void *instance); + flash_error_t efl_lld_start_erase_sector(void *instance, + flash_sector_t sector); + flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec); + flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EFL == TRUE */ + +#endif /* HAL_EFL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32G0xx/hal_efl_lld.c b/os/hal/ports/STM32/STM32G0xx/hal_efl_lld.c index 20af8885e..8fec8a9c3 100644 --- a/os/hal/ports/STM32/STM32G0xx/hal_efl_lld.c +++ b/os/hal/ports/STM32/STM32G0xx/hal_efl_lld.c @@ -193,8 +193,8 @@ void efl_lld_init(void) { /* Find the size of the flash and set descriptor reference. */ uint8_t i; for (i = 0; i < (sizeof(efl_lld_flash_sizes) / sizeof(efl_lld_size_t)); i++) { - if (efl_lld_flash_sizes[i].desc->size == stm32_flash_get_size()) { - EFLD1.descriptor = efl_lld_flash_sizes[i].desc; + if (efl_lld_flash_sizes[i].desc->size == stm32_flash_get_size()) { + EFLD1.descriptor = efl_lld_flash_sizes[i].desc; if (stm32_flash_dual_bank(&EFLD1)) { /* Point to the dual bank descriptor. */ EFLD1.descriptor++; diff --git a/os/hal/ports/STM32/STM32G0xx/hal_efl_lld.h b/os/hal/ports/STM32/STM32G0xx/hal_efl_lld.h index 19f4b83ca..68ad481e4 100644 --- a/os/hal/ports/STM32/STM32G0xx/hal_efl_lld.h +++ b/os/hal/ports/STM32/STM32G0xx/hal_efl_lld.h @@ -51,8 +51,8 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if defined(STM32G070xx) || defined(STM32G071xx) || \ - defined(STM32G081xx) || \ +#if defined(STM32G070xx) || defined(STM32G071xx) || \ + defined(STM32G081xx) || \ defined(__DOXYGEN__) /* Flash size register. */ diff --git a/os/hal/ports/STM32/STM32G0xx/hal_lld.c b/os/hal/ports/STM32/STM32G0xx/hal_lld.c index c27d9c164..68eb18084 100644 --- a/os/hal/ports/STM32/STM32G0xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32G0xx/hal_lld.c @@ -354,7 +354,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { /* PLL VCO frequency.*/ pllvcoclk = (pllselclk / (halfreq_t)pllmdiv) * (halfreq_t)pllndiv; - if((pllvcoclk < slp->pllvco_min) || (pllvcoclk > slp->pllvco_max)) { + if ((pllvcoclk < slp->pllvco_min) || (pllvcoclk > slp->pllvco_max)) { return true; } @@ -363,7 +363,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLPEN) != 0U) { pllpclk = pllvcoclk / pllpdiv; - if((pllpclk < slp->pllp_min) || (pllpclk > slp->pllp_max)) { + if ((pllpclk < slp->pllp_min) || (pllpclk > slp->pllp_max)) { return true; } } @@ -373,7 +373,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLQEN) != 0U) { pllqclk = pllvcoclk / pllqdiv; - if((pllqclk < slp->pllq_min) || (pllqclk > slp->pllq_max)) { + if ((pllqclk < slp->pllq_min) || (pllqclk > slp->pllq_max)) { return true; } } @@ -383,14 +383,14 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLREN) != 0U) { pllrclk = pllvcoclk / pllrdiv; - if((pllrclk < slp->pllr_min) || (pllrclk > slp->pllr_max)) { + if ((pllrclk < slp->pllr_min) || (pllrclk > slp->pllr_max)) { return true; } } } /* SYSCLK frequency.*/ - switch(ccp->rcc_cfgr & RCC_CFGR_SW_Msk) { + switch (ccp->rcc_cfgr & RCC_CFGR_SW_Msk) { case RCC_CFGR_SW_HSI: sysclk = hsisysclk; break; @@ -427,7 +427,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { } /* MCO clock.*/ - switch(ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) { + switch (ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) { case STM32_MCOSEL_NOCLOCK: mcoclk = 0U; break; diff --git a/os/hal/ports/STM32/STM32G0xx/hal_lld.h b/os/hal/ports/STM32/STM32G0xx/hal_lld.h index 900cc755a..d04b75648 100644 --- a/os/hal/ports/STM32/STM32G0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32G0xx/hal_lld.h @@ -288,7 +288,6 @@ #define STM32_ADCSEL_HSI16 (2U << 30U) /**< ADC source is HSI16. */ /** @} */ - /** * @name RCC_CCIPR2 register bits definitions * @{ @@ -1569,7 +1568,6 @@ #elif STM32_RNGSEL == STM32_RNGSEL_PLLQCLK #define STM32_RNGCLK (hal_lld_get_clock_point(CLK_PLLQCLK) / STM32_RNGDIV_VALUE) - #else #error "invalid source selected for RNG clock" #endif diff --git a/os/hal/ports/STM32/STM32G0xx/stm32_registry.h b/os/hal/ports/STM32/STM32G0xx/stm32_registry.h index b959fde13..0a14805e0 100644 --- a/os/hal/ports/STM32/STM32G0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32G0xx/stm32_registry.h @@ -95,7 +95,6 @@ #define STM32_RCC_HAS_PLL TRUE #define STM32_RCC_PLL_HAS_P TRUE -/*#define STM32_RCC_PLL_HAS_Q TRUE*/ /* Varies, see below.*/ #define STM32_RCC_PLL_HAS_R TRUE #define STM32_RCC_HAS_PLLSAI1 FALSE diff --git a/os/hal/ports/STM32/STM32G4xx/hal_lld.c b/os/hal/ports/STM32/STM32G4xx/hal_lld.c index 803bffaa1..15cc86e43 100644 --- a/os/hal/ports/STM32/STM32G4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32G4xx/hal_lld.c @@ -364,7 +364,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { /* PLL VCO frequency.*/ pllvcoclk = (pllselclk / (halfreq_t)pllmdiv) * (halfreq_t)pllndiv; - if((pllvcoclk < slp->pllvco_min) || (pllvcoclk > slp->pllvco_max)) { + if ((pllvcoclk < slp->pllvco_min) || (pllvcoclk > slp->pllvco_max)) { return true; } @@ -384,7 +384,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLPEN) != 0U) { pllpclk = pllvcoclk / pllpdiv; - if((pllpclk < slp->pllp_min) || (pllpclk > slp->pllp_max)) { + if ((pllpclk < slp->pllp_min) || (pllpclk > slp->pllp_max)) { return true; } } @@ -394,7 +394,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLQEN) != 0U) { pllqclk = pllvcoclk / pllqdiv; - if((pllqclk < slp->pllq_min) || (pllqclk > slp->pllq_max)) { + if ((pllqclk < slp->pllq_min) || (pllqclk > slp->pllq_max)) { return true; } } @@ -404,14 +404,14 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLREN) != 0U) { pllrclk = pllvcoclk / pllrdiv; - if((pllrclk < slp->pllr_min) || (pllrclk > slp->pllr_max)) { + if ((pllrclk < slp->pllr_min) || (pllrclk > slp->pllr_max)) { return true; } } } /* SYSCLK frequency.*/ - switch(ccp->rcc_cfgr & RCC_CFGR_SW_Msk) { + switch (ccp->rcc_cfgr & RCC_CFGR_SW_Msk) { case RCC_CFGR_SW_HSI: sysclk = hsi16clk; break; @@ -451,7 +451,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { } /* MCO clock.*/ - switch(ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) { + switch (ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) { case STM32_MCOSEL_NOCLOCK: mcoclk = 0U; break; diff --git a/os/hal/ports/STM32/STM32G4xx/stm32_registry.h b/os/hal/ports/STM32/STM32G4xx/stm32_registry.h index 50ef60fff..392dfd289 100644 --- a/os/hal/ports/STM32/STM32G4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32G4xx/stm32_registry.h @@ -166,7 +166,6 @@ #define STM32_EXTI_IMR1_MASK 0x1F840000U #define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU - /* Flash attributes.*/ #define STM32_FLASH_NUMBER_OF_BANKS 2 @@ -381,7 +380,6 @@ #define STM32_EXTI_IMR1_MASK 0x1F840000U #define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU - /* Flash attributes.*/ #define STM32_FLASH_NUMBER_OF_BANKS 2 @@ -596,7 +594,6 @@ #define STM32_EXTI_IMR1_MASK 0x1F840000U #define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU - /* Flash attributes.*/ #define STM32_FLASH_NUMBER_OF_BANKS 2 diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h index 8fd193c66..c338e4069 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h @@ -1296,35 +1296,35 @@ #error "Using a wrong mcuconf.h file, STM32H7xx_MCUCONF not defined" #endif -#if defined(STM32H750xx)&& !defined(STM32H750_MCUCONF) +#if defined(STM32H750xx) && !defined(STM32H750_MCUCONF) #error "Using a wrong mcuconf.h file, STM32H750_MCUCONF not defined" #endif -#if defined(STM32H742xx)&& !defined(STM32H742_MCUCONF) +#if defined(STM32H742xx) && !defined(STM32H742_MCUCONF) #error "Using a wrong mcuconf.h file, STM32H742_MCUCONF not defined" #endif -#if defined(STM32H743xx)&& !defined(STM32H743_MCUCONF) +#if defined(STM32H743xx) && !defined(STM32H743_MCUCONF) #error "Using a wrong mcuconf.h file, STM32H743_MCUCONF not defined" #endif -#if defined(STM32H753xx)&& !defined(STM32H753_MCUCONF) +#if defined(STM32H753xx) && !defined(STM32H753_MCUCONF) #error "Using a wrong mcuconf.h file, STM32H753_MCUCONF not defined" #endif -#if defined(STM32H745xx)&& !defined(STM32H745_MCUCONF) +#if defined(STM32H745xx) && !defined(STM32H745_MCUCONF) #error "Using a wrong mcuconf.h file, STM32H745_MCUCONF not defined" #endif -#if defined(STM32H755xx)&& !defined(STM32H755_MCUCONF) +#if defined(STM32H755xx) && !defined(STM32H755_MCUCONF) #error "Using a wrong mcuconf.h file, STM32H755_MCUCONF not defined" #endif -#if defined(STM32H747xx)&& !defined(STM32H747_MCUCONF) +#if defined(STM32H747xx) && !defined(STM32H747_MCUCONF) #error "Using a wrong mcuconf.h file, STM32H747_MCUCONF not defined" #endif -#if defined(STM32H757xx)&& !defined(STM32H757_MCUCONF) +#if defined(STM32H757xx) && !defined(STM32H757_MCUCONF) #error "Using a wrong mcuconf.h file, STM32H757_MCUCONF not defined" #endif diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h index 7784ffc4c..3ac41a1fd 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h @@ -574,7 +574,6 @@ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE TRUE - /*===========================================================================*/ /* STM32L052xx, STM32L062xx, STM32L053xx, STM32L063xx. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/STM32L4xx+/hal_efl_lld.c b/os/hal/ports/STM32/STM32L4xx+/hal_efl_lld.c index b9a7ed067..9d102c48c 100644 --- a/os/hal/ports/STM32/STM32L4xx+/hal_efl_lld.c +++ b/os/hal/ports/STM32/STM32L4xx+/hal_efl_lld.c @@ -1,631 +1,631 @@ -/* - ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_efl_lld.c - * @brief STM32L4R/Snxx Embedded Flash subsystem low level driver source. - * - * @addtogroup HAL_EFL - * @{ - */ - -#include - -#include "hal.h" - -#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define STM32_FLASH_LINE_SIZE 8U -#define STM32_FLASH_LINE_MASK (STM32_FLASH_LINE_SIZE - 1U) - -#define FLASH_PDKEY1 0x04152637U -#define FLASH_PDKEY2 0xFAFBFCFDU - -#define FLASH_KEY1 0x45670123U -#define FLASH_KEY2 0xCDEF89ABU - -#define FLASH_OPTKEY1 0x08192A3BU -#define FLASH_OPTKEY2 0x4C5D6E7FU - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief EFL1 driver identifier. - */ -EFlashDriver EFLD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/* The descriptors for 1M device. */ -static const flash_descriptor_t efl_lld_size1[STM32_FLASH_NUMBER_OF_BANKS] = { - { /* Bank 1 (SBM) organisation. */ - .attributes = FLASH_ATTR_ERASED_IS_ONE | - FLASH_ATTR_MEMORY_MAPPED | - FLASH_ATTR_ECC_CAPABLE | - FLASH_ATTR_ECC_ZERO_LINE_CAPABLE, - .page_size = STM32_FLASH_LINE_SIZE, - .sectors_count = STM32_FLASH_SECTORS_TOTAL_1M, - .sectors = NULL, - .sectors_size = STM32_FLASH_SECTOR_SIZE_1M, - .address = (uint8_t *)FLASH_BASE, - .size = STM32_FLASH_SIZE_1M * STM32_FLASH_SIZE_SCALE - }, - { /* Bank 1 & 2 (DBM) organisation. */ - .attributes = FLASH_ATTR_ERASED_IS_ONE | - FLASH_ATTR_MEMORY_MAPPED | - FLASH_ATTR_ECC_CAPABLE | - FLASH_ATTR_ECC_ZERO_LINE_CAPABLE, - .page_size = STM32_FLASH_LINE_SIZE, - .sectors_count = (STM32_FLASH_SECTORS_TOTAL_1M * 2), - .sectors = NULL, - .sectors_size = STM32_FLASH_DUAL_SECTOR_SIZE_1M, - .address = (uint8_t *)FLASH_BASE, - .size = STM32_FLASH_SIZE_1M * STM32_FLASH_SIZE_SCALE - } -}; - -/* The descriptors for 2M device. */ -static const flash_descriptor_t efl_lld_size2[STM32_FLASH_NUMBER_OF_BANKS] = { - { /* Bank 1 (SBM) organisation. */ - .attributes = FLASH_ATTR_ERASED_IS_ONE | - FLASH_ATTR_MEMORY_MAPPED | - FLASH_ATTR_ECC_CAPABLE | - FLASH_ATTR_ECC_ZERO_LINE_CAPABLE, - .page_size = STM32_FLASH_LINE_SIZE, - .sectors_count = STM32_FLASH_SECTORS_TOTAL_2M, - .sectors = NULL, - .sectors_size = STM32_FLASH_SECTOR_SIZE_2M, - .address = (uint8_t *)FLASH_BASE, - .size = STM32_FLASH_SIZE_2M * STM32_FLASH_SIZE_SCALE - }, - { /* Bank 1 & 2 (DBM) organisation. */ - .attributes = FLASH_ATTR_ERASED_IS_ONE | - FLASH_ATTR_MEMORY_MAPPED | - FLASH_ATTR_ECC_CAPABLE | - FLASH_ATTR_ECC_ZERO_LINE_CAPABLE, - .page_size = STM32_FLASH_LINE_SIZE, - .sectors_count = (STM32_FLASH_SECTORS_TOTAL_2M * 2), - .sectors = NULL, - .sectors_size = STM32_FLASH_DUAL_SECTOR_SIZE_2M, - .address = (uint8_t *)FLASH_BASE, - .size = STM32_FLASH_SIZE_2M * STM32_FLASH_SIZE_SCALE - } -}; - -/* Table describing possible flash sizes and descriptors for this device. */ -static const efl_lld_size_t efl_lld_flash_sizes[] = { - { - .desc = efl_lld_size1 - }, - { - .desc = efl_lld_size2 - } -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static inline void stm32_flash_lock(EFlashDriver *eflp) { - - eflp->flash->CR |= FLASH_CR_LOCK; -} - -static inline void stm32_flash_unlock(EFlashDriver *eflp) { - - eflp->flash->KEYR |= FLASH_KEY1; - eflp->flash->KEYR |= FLASH_KEY2; -} - -static inline void stm32_flash_enable_pgm(EFlashDriver *eflp) { - - eflp->flash->CR |= FLASH_CR_PG; -} - -static inline void stm32_flash_disable_pgm(EFlashDriver *eflp) { - - eflp->flash->CR &= ~FLASH_CR_PG; -} - -static inline void stm32_flash_clear_status(EFlashDriver *eflp) { - - eflp->flash->SR = 0x0000FFFFU; -} - -static inline void stm32_flash_wait_busy(EFlashDriver *eflp) { - - /* Wait for busy bit clear.*/ - while ((eflp->flash->SR & FLASH_SR_BSY) != 0U) { - } -} - -static inline size_t stm32_flash_get_size(void) { - return *(uint16_t*)((uint32_t) STM32_FLASH_SIZE_REGISTER) * STM32_FLASH_SIZE_SCALE; -} - -static inline bool stm32_flash_dual_bank(EFlashDriver *eflp) { - -#if STM32_FLASH_NUMBER_OF_BANKS > 1 - return ((eflp->flash->OPTR & (FLASH_OPTR_DBANK | FLASH_OPTR_DB1M)) != 0U); -#endif - return false; -} - -static inline flash_error_t stm32_flash_check_errors(EFlashDriver *eflp) { - uint32_t sr = eflp->flash->SR; - - /* Clearing error conditions.*/ - eflp->flash->SR = sr & 0x0000FFFFU; - - /* Some errors are only caught by assertion.*/ - osalDbgAssert((sr & (FLASH_SR_FASTERR | - FLASH_SR_MISERR | - FLASH_SR_SIZERR)) == 0U, "unexpected flash error"); - - /* Decoding relevant errors.*/ - if ((sr & FLASH_SR_WRPERR) != 0U) { - return FLASH_ERROR_HW_FAILURE; - } - - if ((sr & (FLASH_SR_PGAERR | FLASH_SR_PROGERR | FLASH_SR_OPERR)) != 0U) { - return eflp->state == FLASH_PGM ? FLASH_ERROR_PROGRAM : FLASH_ERROR_ERASE; - } - - return FLASH_NO_ERROR; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level Embedded Flash driver initialization. - * - * @notapi - */ -void efl_lld_init(void) { - - /* Driver initialization.*/ - eflObjectInit(&EFLD1); - EFLD1.flash = FLASH; - /* Find the size of the flash and set descriptor reference. */ - uint8_t i; - for (i = 0; i < (sizeof(efl_lld_flash_sizes) / sizeof(efl_lld_size_t)); i++) { - if (efl_lld_flash_sizes[i].desc->size == stm32_flash_get_size()) { - EFLD1.descriptor = efl_lld_flash_sizes[i].desc; - if (stm32_flash_dual_bank(&EFLD1)) { - /* Point to the dual bank descriptor. */ - EFLD1.descriptor++; - } - return; - } - } - osalDbgAssert(false, "invalid flash configuration"); -} - -/** - * @brief Configures and activates the Embedded Flash peripheral. - * - * @param[in] eflp pointer to a @p EFlashDriver structure - * - * @notapi - */ -void efl_lld_start(EFlashDriver *eflp) { - stm32_flash_unlock(eflp); - FLASH->CR = 0x00000000U; -} - -/** - * @brief Deactivates the Embedded Flash peripheral. - * - * @param[in] eflp pointer to a @p EFlashDriver structure - * - * @notapi - */ -void efl_lld_stop(EFlashDriver *eflp) { - - stm32_flash_lock(eflp); -} - -/** - * @brief Gets the flash descriptor structure. - * - * @param[in] ip pointer to a @p EFlashDriver instance - * @return A flash device descriptor. - * @retval Pointer to single bank if DBM not enabled. - * @retval Pointer to bank1 if DBM enabled. - * - * @notapi - */ -const flash_descriptor_t *efl_lld_get_descriptor(void *instance) { - EFlashDriver *devp = (EFlashDriver *)instance; - return devp->descriptor; -} - -/** - * @brief Read operation. - * - * @param[in] ip pointer to a @p EFlashDriver instance - * @param[in] offset offset within full flash address space - * @param[in] n number of bytes to be read - * @param[out] rp pointer to the data buffer - * @return An error code. - * @retval FLASH_NO_ERROR if there is no erase operation in progress. - * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. - * @retval FLASH_ERROR_READ if the read operation failed. - * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. - * - * @notapi - */ -flash_error_t efl_lld_read(void *instance, flash_offset_t offset, - size_t n, uint8_t *rp) { - EFlashDriver *devp = (EFlashDriver *)instance; - flash_error_t err = FLASH_NO_ERROR; - - osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U)); - - const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); - osalDbgCheck((size_t)offset + n <= (size_t)bank->size); - osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), - "invalid state"); - - /* No reading while erasing.*/ - if (devp->state == FLASH_ERASE) { - return FLASH_BUSY_ERASING; - } - - /* FLASH_READ state while the operation is performed.*/ - devp->state = FLASH_READ; - - /* Clearing error status bits.*/ - stm32_flash_clear_status(devp); - - /* Actual read implementation.*/ - memcpy((void *)rp, (const void *)efl_lld_get_descriptor(instance)->address - + offset, n); - - /* Checking for errors after reading.*/ - if ((devp->flash->SR & FLASH_SR_RDERR) != 0U) { - err = FLASH_ERROR_READ; - } - - /* Ready state again.*/ - devp->state = FLASH_READY; - - return err; - -} - -/** - * @brief Program operation. - * @note The device supports ECC. It is only possible to write erased - * pages once except when writing all zeroes to a location. - * - * @param[in] ip pointer to a @p EFlashDriver instance - * @param[in] offset offset within full flash address space - * @param[in] n number of bytes to be programmed - * @param[in] pp pointer to the data buffer - * @return An error code. - * @retval FLASH_NO_ERROR if there is no erase operation in progress. - * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. - * @retval FLASH_ERROR_PROGRAM if the program operation failed. - * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. - * - * @notapi - */ -flash_error_t efl_lld_program(void *instance, flash_offset_t offset, - size_t n, const uint8_t *pp) { - EFlashDriver *devp = (EFlashDriver *)instance; - const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); - flash_error_t err = FLASH_NO_ERROR; - - osalDbgCheck((instance != NULL) && (pp != NULL) && (n > 0U)); - osalDbgCheck((size_t)offset + n <= (size_t)bank->size); - osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), - "invalid state"); - - /* No programming while erasing.*/ - if (devp->state == FLASH_ERASE) { - return FLASH_BUSY_ERASING; - } - - /* FLASH_PGM state while the operation is performed.*/ - devp->state = FLASH_PGM; - - /* Clearing error status bits.*/ - stm32_flash_clear_status(devp); - - /* Enabling PGM mode in the controller.*/ - stm32_flash_enable_pgm(devp); - - /* Actual program implementation.*/ - while (n > 0U) { - volatile uint32_t *address; - - union { - uint32_t w[STM32_FLASH_LINE_SIZE / sizeof (uint32_t)]; - uint8_t b[STM32_FLASH_LINE_SIZE / sizeof (uint8_t)]; - } line; - - /* Unwritten bytes are initialized to all ones.*/ - line.w[0] = 0xFFFFFFFFU; - line.w[1] = 0xFFFFFFFFU; - - /* Programming address aligned to flash lines.*/ - address = (volatile uint32_t *)(bank->address + - (offset & ~STM32_FLASH_LINE_MASK)); - - /* Copying data inside the prepared line.*/ - do { - line.b[offset & STM32_FLASH_LINE_MASK] = *pp; - offset++; - n--; - pp++; - } - while ((n > 0U) & ((offset & STM32_FLASH_LINE_MASK) != 0U)); - - /* Programming line.*/ - address[0] = line.w[0]; - address[1] = line.w[1]; - stm32_flash_wait_busy(devp); - err = stm32_flash_check_errors(devp); - if (err != FLASH_NO_ERROR) { - break; - } - } - - /* Disabling PGM mode in the controller.*/ - stm32_flash_disable_pgm(devp); - - /* Ready state again.*/ - devp->state = FLASH_READY; - - return err; -} - -/** - * @brief Starts a whole-device erase operation. - * @note This function only erases bank 2 if it is present. Bank 1 is not - * allowed since it is normally where the primary program is located. - * Pages on bank 1 can be individually erased. - * - * @param[in] ip pointer to a @p EFlashDriver instance - * @return An error code. - * @retval FLASH_NO_ERROR if there is no erase operation in progress. - * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. - * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. - * - * @notapi - */ -flash_error_t efl_lld_start_erase_all(void *instance) { - EFlashDriver *devp = (EFlashDriver *)instance; - - osalDbgCheck(instance != NULL); - osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), - "invalid state"); - - /* No erasing while erasing.*/ - if (devp->state == FLASH_ERASE) { - return FLASH_BUSY_ERASING; - } - -#if defined(FLASH_CR_MER2) - /* If dual bank is active then mass erase bank2. */ - if (stm32_flash_dual_bank(devp)) { - - /* FLASH_ERASE state while the operation is performed.*/ - devp->state = FLASH_ERASE; - - /* Clearing error status bits.*/ - stm32_flash_clear_status(devp); - - devp->flash->CR |= FLASH_CR_MER2; - devp->flash->CR |= FLASH_CR_STRT; - return FLASH_NO_ERROR; - } -#endif - - /* Mass erase not allowed. */ - return FLASH_ERROR_UNIMPLEMENTED; -} - -/** - * @brief Starts an sector erase operation. - * - * @param[in] ip pointer to a @p EFlashDriver instance - * @param[in] sector sector to be erased - * this is an index within the total sectors - * in a flash bank - * @return An error code. - * @retval FLASH_NO_ERROR if there is no erase operation in progress. - * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. - * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. - * - * @notapi - */ -flash_error_t efl_lld_start_erase_sector(void *instance, - flash_sector_t sector) { - EFlashDriver *devp = (EFlashDriver *)instance; - const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); - osalDbgCheck(instance != NULL); - osalDbgCheck(sector < bank->sectors_count); - osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), - "invalid state"); - - /* No erasing while erasing.*/ - if (devp->state == FLASH_ERASE) { - return FLASH_BUSY_ERASING; - } - - /* FLASH_PGM state while the operation is performed.*/ - devp->state = FLASH_ERASE; - - /* Clearing error status bits.*/ - stm32_flash_clear_status(devp); - - /* Enable page erase.*/ - devp->flash->CR |= FLASH_CR_PER; - -#if defined(FLASH_CR_BKER) - /* If dual bank is active then setup relevant bank. */ - if (stm32_flash_dual_bank(devp)) { - if (sector < (bank->sectors_count / 2)) { - /* First bank.*/ - devp->flash->CR &= ~FLASH_CR_BKER; - } - else { - /* Second bank. Adjust sector index. */ - sector -= (bank->sectors_count / 2); - devp->flash->CR |= FLASH_CR_BKER; - } - } -#endif - - /* Mask off the page selection bits.*/ - devp->flash->CR &= ~FLASH_CR_PNB; - - /* Set the page selection bits.*/ - devp->flash->CR |= sector << FLASH_CR_PNB_Pos; - - /* Start the erase.*/ - devp->flash->CR |= FLASH_CR_STRT; - - return FLASH_NO_ERROR; -} - -/** - * @brief Queries the driver for erase operation progress. - * - * @param[in] ip pointer to a @p EFlashDriver instance - * @param[out] msec recommended time, in milliseconds, that - * should be spent before calling this - * function again, can be @p NULL - * @return An error code. - * @retval FLASH_NO_ERROR if there is no erase operation in progress. - * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. - * @retval FLASH_ERROR_ERASE if the erase operation failed. - * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. - * - * @api - */ -flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) { - EFlashDriver *devp = (EFlashDriver *)instance; - flash_error_t err; - - /* If there is an erase in progress then the device must be checked.*/ - if (devp->state == FLASH_ERASE) { - - /* Checking for operation in progress.*/ - if ((devp->flash->SR & FLASH_SR_BSY) == 0U) { - - /* Disabling the various erase control bits.*/ - devp->flash->CR &= ~(FLASH_CR_MER1 | -#if defined(FLASH_CR_MER2) - FLASH_CR_MER2 | -#endif - FLASH_CR_PER); - - /* No operation in progress, checking for errors.*/ - err = stm32_flash_check_errors(devp); - - /* Back to ready state.*/ - devp->state = FLASH_READY; - } - else { - /* Recommended time before polling again. This is a simplified - implementation.*/ - if (msec != NULL) { - *msec = (uint32_t)STM32_FLASH_WAIT_TIME_MS; - } - - err = FLASH_BUSY_ERASING; - } - } - else { - err = FLASH_NO_ERROR; - } - - return err; -} - -/** - * @brief Returns the erase state of a sector. - * - * @param[in] ip pointer to a @p EFlashDriver instance - * @param[in] sector sector to be verified - * @return An error code. - * @retval FLASH_NO_ERROR if the sector is erased. - * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. - * @retval FLASH_ERROR_VERIFY if the verify operation failed. - * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. - * - * @notapi - */ -flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) { - EFlashDriver *devp = (EFlashDriver *)instance; - uint32_t *address; - const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); - flash_error_t err = FLASH_NO_ERROR; - unsigned i; - - osalDbgCheck(instance != NULL); - osalDbgCheck(sector < bank->sectors_count); - osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), - "invalid state"); - - /* No verifying while erasing.*/ - if (devp->state == FLASH_ERASE) { - return FLASH_BUSY_ERASING; - } - - /* Address of the sector in the bank.*/ - address = (uint32_t *)(bank->address + - flashGetSectorOffset(getBaseFlash(devp), sector)); - - /* FLASH_READ state while the operation is performed.*/ - devp->state = FLASH_READ; - - /* Scanning the sector space.*/ - uint32_t sector_size = flashGetSectorSize(getBaseFlash(devp), sector); - for (i = 0U; i < sector_size / sizeof(uint32_t); i++) { - if (*address != 0xFFFFFFFFU) { - err = FLASH_ERROR_VERIFY; - break; - } - address++; - } - - /* Ready state again.*/ - devp->state = FLASH_READY; - - return err; -} - -#endif /* HAL_USE_EFL == TRUE */ - -/** @} */ +/* + ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_efl_lld.c + * @brief STM32L4R/Snxx Embedded Flash subsystem low level driver source. + * + * @addtogroup HAL_EFL + * @{ + */ + +#include + +#include "hal.h" + +#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define STM32_FLASH_LINE_SIZE 8U +#define STM32_FLASH_LINE_MASK (STM32_FLASH_LINE_SIZE - 1U) + +#define FLASH_PDKEY1 0x04152637U +#define FLASH_PDKEY2 0xFAFBFCFDU + +#define FLASH_KEY1 0x45670123U +#define FLASH_KEY2 0xCDEF89ABU + +#define FLASH_OPTKEY1 0x08192A3BU +#define FLASH_OPTKEY2 0x4C5D6E7FU + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EFL1 driver identifier. + */ +EFlashDriver EFLD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/* The descriptors for 1M device. */ +static const flash_descriptor_t efl_lld_size1[STM32_FLASH_NUMBER_OF_BANKS] = { + { /* Bank 1 (SBM) organisation. */ + .attributes = FLASH_ATTR_ERASED_IS_ONE | + FLASH_ATTR_MEMORY_MAPPED | + FLASH_ATTR_ECC_CAPABLE | + FLASH_ATTR_ECC_ZERO_LINE_CAPABLE, + .page_size = STM32_FLASH_LINE_SIZE, + .sectors_count = STM32_FLASH_SECTORS_TOTAL_1M, + .sectors = NULL, + .sectors_size = STM32_FLASH_SECTOR_SIZE_1M, + .address = (uint8_t *)FLASH_BASE, + .size = STM32_FLASH_SIZE_1M * STM32_FLASH_SIZE_SCALE + }, + { /* Bank 1 & 2 (DBM) organisation. */ + .attributes = FLASH_ATTR_ERASED_IS_ONE | + FLASH_ATTR_MEMORY_MAPPED | + FLASH_ATTR_ECC_CAPABLE | + FLASH_ATTR_ECC_ZERO_LINE_CAPABLE, + .page_size = STM32_FLASH_LINE_SIZE, + .sectors_count = (STM32_FLASH_SECTORS_TOTAL_1M * 2), + .sectors = NULL, + .sectors_size = STM32_FLASH_DUAL_SECTOR_SIZE_1M, + .address = (uint8_t *)FLASH_BASE, + .size = STM32_FLASH_SIZE_1M * STM32_FLASH_SIZE_SCALE + } +}; + +/* The descriptors for 2M device. */ +static const flash_descriptor_t efl_lld_size2[STM32_FLASH_NUMBER_OF_BANKS] = { + { /* Bank 1 (SBM) organisation. */ + .attributes = FLASH_ATTR_ERASED_IS_ONE | + FLASH_ATTR_MEMORY_MAPPED | + FLASH_ATTR_ECC_CAPABLE | + FLASH_ATTR_ECC_ZERO_LINE_CAPABLE, + .page_size = STM32_FLASH_LINE_SIZE, + .sectors_count = STM32_FLASH_SECTORS_TOTAL_2M, + .sectors = NULL, + .sectors_size = STM32_FLASH_SECTOR_SIZE_2M, + .address = (uint8_t *)FLASH_BASE, + .size = STM32_FLASH_SIZE_2M * STM32_FLASH_SIZE_SCALE + }, + { /* Bank 1 & 2 (DBM) organisation. */ + .attributes = FLASH_ATTR_ERASED_IS_ONE | + FLASH_ATTR_MEMORY_MAPPED | + FLASH_ATTR_ECC_CAPABLE | + FLASH_ATTR_ECC_ZERO_LINE_CAPABLE, + .page_size = STM32_FLASH_LINE_SIZE, + .sectors_count = (STM32_FLASH_SECTORS_TOTAL_2M * 2), + .sectors = NULL, + .sectors_size = STM32_FLASH_DUAL_SECTOR_SIZE_2M, + .address = (uint8_t *)FLASH_BASE, + .size = STM32_FLASH_SIZE_2M * STM32_FLASH_SIZE_SCALE + } +}; + +/* Table describing possible flash sizes and descriptors for this device. */ +static const efl_lld_size_t efl_lld_flash_sizes[] = { + { + .desc = efl_lld_size1 + }, + { + .desc = efl_lld_size2 + } +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void stm32_flash_lock(EFlashDriver *eflp) { + + eflp->flash->CR |= FLASH_CR_LOCK; +} + +static inline void stm32_flash_unlock(EFlashDriver *eflp) { + + eflp->flash->KEYR |= FLASH_KEY1; + eflp->flash->KEYR |= FLASH_KEY2; +} + +static inline void stm32_flash_enable_pgm(EFlashDriver *eflp) { + + eflp->flash->CR |= FLASH_CR_PG; +} + +static inline void stm32_flash_disable_pgm(EFlashDriver *eflp) { + + eflp->flash->CR &= ~FLASH_CR_PG; +} + +static inline void stm32_flash_clear_status(EFlashDriver *eflp) { + + eflp->flash->SR = 0x0000FFFFU; +} + +static inline void stm32_flash_wait_busy(EFlashDriver *eflp) { + + /* Wait for busy bit clear.*/ + while ((eflp->flash->SR & FLASH_SR_BSY) != 0U) { + } +} + +static inline size_t stm32_flash_get_size(void) { + return *(uint16_t*)((uint32_t) STM32_FLASH_SIZE_REGISTER) * STM32_FLASH_SIZE_SCALE; +} + +static inline bool stm32_flash_dual_bank(EFlashDriver *eflp) { + +#if STM32_FLASH_NUMBER_OF_BANKS > 1 + return ((eflp->flash->OPTR & (FLASH_OPTR_DBANK | FLASH_OPTR_DB1M)) != 0U); +#endif + return false; +} + +static inline flash_error_t stm32_flash_check_errors(EFlashDriver *eflp) { + uint32_t sr = eflp->flash->SR; + + /* Clearing error conditions.*/ + eflp->flash->SR = sr & 0x0000FFFFU; + + /* Some errors are only caught by assertion.*/ + osalDbgAssert((sr & (FLASH_SR_FASTERR | + FLASH_SR_MISERR | + FLASH_SR_SIZERR)) == 0U, "unexpected flash error"); + + /* Decoding relevant errors.*/ + if ((sr & FLASH_SR_WRPERR) != 0U) { + return FLASH_ERROR_HW_FAILURE; + } + + if ((sr & (FLASH_SR_PGAERR | FLASH_SR_PROGERR | FLASH_SR_OPERR)) != 0U) { + return eflp->state == FLASH_PGM ? FLASH_ERROR_PROGRAM : FLASH_ERROR_ERASE; + } + + return FLASH_NO_ERROR; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level Embedded Flash driver initialization. + * + * @notapi + */ +void efl_lld_init(void) { + + /* Driver initialization.*/ + eflObjectInit(&EFLD1); + EFLD1.flash = FLASH; + /* Find the size of the flash and set descriptor reference. */ + uint8_t i; + for (i = 0; i < (sizeof(efl_lld_flash_sizes) / sizeof(efl_lld_size_t)); i++) { + if (efl_lld_flash_sizes[i].desc->size == stm32_flash_get_size()) { + EFLD1.descriptor = efl_lld_flash_sizes[i].desc; + if (stm32_flash_dual_bank(&EFLD1)) { + /* Point to the dual bank descriptor. */ + EFLD1.descriptor++; + } + return; + } + } + osalDbgAssert(false, "invalid flash configuration"); +} + +/** + * @brief Configures and activates the Embedded Flash peripheral. + * + * @param[in] eflp pointer to a @p EFlashDriver structure + * + * @notapi + */ +void efl_lld_start(EFlashDriver *eflp) { + stm32_flash_unlock(eflp); + FLASH->CR = 0x00000000U; +} + +/** + * @brief Deactivates the Embedded Flash peripheral. + * + * @param[in] eflp pointer to a @p EFlashDriver structure + * + * @notapi + */ +void efl_lld_stop(EFlashDriver *eflp) { + + stm32_flash_lock(eflp); +} + +/** + * @brief Gets the flash descriptor structure. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @return A flash device descriptor. + * @retval Pointer to single bank if DBM not enabled. + * @retval Pointer to bank1 if DBM enabled. + * + * @notapi + */ +const flash_descriptor_t *efl_lld_get_descriptor(void *instance) { + EFlashDriver *devp = (EFlashDriver *)instance; + return devp->descriptor; +} + +/** + * @brief Read operation. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] offset offset within full flash address space + * @param[in] n number of bytes to be read + * @param[out] rp pointer to the data buffer + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_READ if the read operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_read(void *instance, flash_offset_t offset, + size_t n, uint8_t *rp) { + EFlashDriver *devp = (EFlashDriver *)instance; + flash_error_t err = FLASH_NO_ERROR; + + osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U)); + + const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); + osalDbgCheck((size_t)offset + n <= (size_t)bank->size); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No reading while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* FLASH_READ state while the operation is performed.*/ + devp->state = FLASH_READ; + + /* Clearing error status bits.*/ + stm32_flash_clear_status(devp); + + /* Actual read implementation.*/ + memcpy((void *)rp, (const void *)efl_lld_get_descriptor(instance)->address + + offset, n); + + /* Checking for errors after reading.*/ + if ((devp->flash->SR & FLASH_SR_RDERR) != 0U) { + err = FLASH_ERROR_READ; + } + + /* Ready state again.*/ + devp->state = FLASH_READY; + + return err; + +} + +/** + * @brief Program operation. + * @note The device supports ECC. It is only possible to write erased + * pages once except when writing all zeroes to a location. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] offset offset within full flash address space + * @param[in] n number of bytes to be programmed + * @param[in] pp pointer to the data buffer + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_PROGRAM if the program operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_program(void *instance, flash_offset_t offset, + size_t n, const uint8_t *pp) { + EFlashDriver *devp = (EFlashDriver *)instance; + const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); + flash_error_t err = FLASH_NO_ERROR; + + osalDbgCheck((instance != NULL) && (pp != NULL) && (n > 0U)); + osalDbgCheck((size_t)offset + n <= (size_t)bank->size); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No programming while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* FLASH_PGM state while the operation is performed.*/ + devp->state = FLASH_PGM; + + /* Clearing error status bits.*/ + stm32_flash_clear_status(devp); + + /* Enabling PGM mode in the controller.*/ + stm32_flash_enable_pgm(devp); + + /* Actual program implementation.*/ + while (n > 0U) { + volatile uint32_t *address; + + union { + uint32_t w[STM32_FLASH_LINE_SIZE / sizeof (uint32_t)]; + uint8_t b[STM32_FLASH_LINE_SIZE / sizeof (uint8_t)]; + } line; + + /* Unwritten bytes are initialized to all ones.*/ + line.w[0] = 0xFFFFFFFFU; + line.w[1] = 0xFFFFFFFFU; + + /* Programming address aligned to flash lines.*/ + address = (volatile uint32_t *)(bank->address + + (offset & ~STM32_FLASH_LINE_MASK)); + + /* Copying data inside the prepared line.*/ + do { + line.b[offset & STM32_FLASH_LINE_MASK] = *pp; + offset++; + n--; + pp++; + } + while ((n > 0U) & ((offset & STM32_FLASH_LINE_MASK) != 0U)); + + /* Programming line.*/ + address[0] = line.w[0]; + address[1] = line.w[1]; + stm32_flash_wait_busy(devp); + err = stm32_flash_check_errors(devp); + if (err != FLASH_NO_ERROR) { + break; + } + } + + /* Disabling PGM mode in the controller.*/ + stm32_flash_disable_pgm(devp); + + /* Ready state again.*/ + devp->state = FLASH_READY; + + return err; +} + +/** + * @brief Starts a whole-device erase operation. + * @note This function only erases bank 2 if it is present. Bank 1 is not + * allowed since it is normally where the primary program is located. + * Pages on bank 1 can be individually erased. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_start_erase_all(void *instance) { + EFlashDriver *devp = (EFlashDriver *)instance; + + osalDbgCheck(instance != NULL); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No erasing while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + +#if defined(FLASH_CR_MER2) + /* If dual bank is active then mass erase bank2. */ + if (stm32_flash_dual_bank(devp)) { + + /* FLASH_ERASE state while the operation is performed.*/ + devp->state = FLASH_ERASE; + + /* Clearing error status bits.*/ + stm32_flash_clear_status(devp); + + devp->flash->CR |= FLASH_CR_MER2; + devp->flash->CR |= FLASH_CR_STRT; + return FLASH_NO_ERROR; + } +#endif + + /* Mass erase not allowed. */ + return FLASH_ERROR_UNIMPLEMENTED; +} + +/** + * @brief Starts an sector erase operation. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] sector sector to be erased + * this is an index within the total sectors + * in a flash bank + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_start_erase_sector(void *instance, + flash_sector_t sector) { + EFlashDriver *devp = (EFlashDriver *)instance; + const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); + osalDbgCheck(instance != NULL); + osalDbgCheck(sector < bank->sectors_count); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No erasing while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* FLASH_PGM state while the operation is performed.*/ + devp->state = FLASH_ERASE; + + /* Clearing error status bits.*/ + stm32_flash_clear_status(devp); + + /* Enable page erase.*/ + devp->flash->CR |= FLASH_CR_PER; + +#if defined(FLASH_CR_BKER) + /* If dual bank is active then setup relevant bank. */ + if (stm32_flash_dual_bank(devp)) { + if (sector < (bank->sectors_count / 2)) { + /* First bank.*/ + devp->flash->CR &= ~FLASH_CR_BKER; + } + else { + /* Second bank. Adjust sector index. */ + sector -= (bank->sectors_count / 2); + devp->flash->CR |= FLASH_CR_BKER; + } + } +#endif + + /* Mask off the page selection bits.*/ + devp->flash->CR &= ~FLASH_CR_PNB; + + /* Set the page selection bits.*/ + devp->flash->CR |= sector << FLASH_CR_PNB_Pos; + + /* Start the erase.*/ + devp->flash->CR |= FLASH_CR_STRT; + + return FLASH_NO_ERROR; +} + +/** + * @brief Queries the driver for erase operation progress. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[out] msec recommended time, in milliseconds, that + * should be spent before calling this + * function again, can be @p NULL + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_ERASE if the erase operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @api + */ +flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) { + EFlashDriver *devp = (EFlashDriver *)instance; + flash_error_t err; + + /* If there is an erase in progress then the device must be checked.*/ + if (devp->state == FLASH_ERASE) { + + /* Checking for operation in progress.*/ + if ((devp->flash->SR & FLASH_SR_BSY) == 0U) { + + /* Disabling the various erase control bits.*/ + devp->flash->CR &= ~(FLASH_CR_MER1 | +#if defined(FLASH_CR_MER2) + FLASH_CR_MER2 | +#endif + FLASH_CR_PER); + + /* No operation in progress, checking for errors.*/ + err = stm32_flash_check_errors(devp); + + /* Back to ready state.*/ + devp->state = FLASH_READY; + } + else { + /* Recommended time before polling again. This is a simplified + implementation.*/ + if (msec != NULL) { + *msec = (uint32_t)STM32_FLASH_WAIT_TIME_MS; + } + + err = FLASH_BUSY_ERASING; + } + } + else { + err = FLASH_NO_ERROR; + } + + return err; +} + +/** + * @brief Returns the erase state of a sector. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] sector sector to be verified + * @return An error code. + * @retval FLASH_NO_ERROR if the sector is erased. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_VERIFY if the verify operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) { + EFlashDriver *devp = (EFlashDriver *)instance; + uint32_t *address; + const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); + flash_error_t err = FLASH_NO_ERROR; + unsigned i; + + osalDbgCheck(instance != NULL); + osalDbgCheck(sector < bank->sectors_count); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No verifying while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* Address of the sector in the bank.*/ + address = (uint32_t *)(bank->address + + flashGetSectorOffset(getBaseFlash(devp), sector)); + + /* FLASH_READ state while the operation is performed.*/ + devp->state = FLASH_READ; + + /* Scanning the sector space.*/ + uint32_t sector_size = flashGetSectorSize(getBaseFlash(devp), sector); + for (i = 0U; i < sector_size / sizeof(uint32_t); i++) { + if (*address != 0xFFFFFFFFU) { + err = FLASH_ERROR_VERIFY; + break; + } + address++; + } + + /* Ready state again.*/ + devp->state = FLASH_READY; + + return err; +} + +#endif /* HAL_USE_EFL == TRUE */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32L4xx+/hal_efl_lld.h b/os/hal/ports/STM32/STM32L4xx+/hal_efl_lld.h index 9ea940f71..a8db3ac88 100644 --- a/os/hal/ports/STM32/STM32L4xx+/hal_efl_lld.h +++ b/os/hal/ports/STM32/STM32L4xx+/hal_efl_lld.h @@ -1,159 +1,159 @@ -/* - ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_efl_lld.h - * @brief STM32L4+ Embedded Flash subsystem low level driver header. - * - * @addtogroup HAL_EFL - * @{ - */ - -#ifndef HAL_EFL_LLD_H -#define HAL_EFL_LLD_H - -#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name STM32L4xx configuration options - * @{ - */ -/** - * @brief Suggested wait time during erase operations polling. - */ -#if !defined(STM32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__) -#define STM32_FLASH_WAIT_TIME_MS 5 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || \ - defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ - defined(STM32L4S7xx) || defined(STM32L4S9xx) || defined(__DOXYGEN__) - -/* Flash size register. */ -#define STM32_FLASH_SIZE_REGISTER 0x1FFF75E0 -#define STM32_FLASH_SIZE_SCALE 1024U - -/* - * Device flash size is: - * 1M for STM32L4+ suffix G devices - * 2M for STM32L4+ suffix I devices. - * - * For 1M devices SBM is organised as 128 x 8K pages. - * For 1M devices DBM is organised as 128 x 4K pages per bank. - * - * For 2M devices SBM is organised as 256 x 8K pages. - * For 2M devices DBM is organised as 256 x 4K pages per bank. - */ - -#define STM32_FLASH_SIZE_1M 1024U -#define STM32_FLASH_SIZE_2M 2048U -#define STM32_FLASH_SECTORS_TOTAL_1M 128 -#define STM32_FLASH_SECTORS_TOTAL_2M 256 - -/* Single bank mode bank 1 for 1M device.*/ -#define STM32_FLASH_SECTOR_SIZE_1M ((STM32_FLASH_SIZE_1M \ - * STM32_FLASH_SIZE_SCALE) \ - / STM32_FLASH_SECTORS_TOTAL_1M) - -/* Dual bank mode banks 1 & 2 for 1M device.*/ -#define STM32_FLASH_DUAL_SECTOR_SIZE_1M (STM32_FLASH_SECTOR_SIZE_1M / 2) - -/* Single bank mode bank 1 for 2M device.*/ -#define STM32_FLASH_SECTOR_SIZE_2M ((STM32_FLASH_SIZE_2M \ - * STM32_FLASH_SIZE_SCALE) \ - / STM32_FLASH_SECTORS_TOTAL_2M) - -/* Dual bank mode banks 1 & 2 for 2M device.*/ -#define STM32_FLASH_DUAL_SECTOR_SIZE_2M (STM32_FLASH_SECTOR_SIZE_2M / 2) - -#else -#error "This EFL driver does not support the selected device" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/* A flash size declaration. */ -typedef struct { - const flash_descriptor_t* desc; -} efl_lld_size_t; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Low level fields of the embedded flash driver structure. - */ -#define efl_lld_driver_fields \ - /* Flash registers.*/ \ - FLASH_TypeDef *flash; \ - const flash_descriptor_t *descriptor; - -/** - * @brief Low level fields of the embedded flash configuration structure. - */ -#define efl_lld_config_fields \ - /* Dummy configuration, it is not needed.*/ \ - uint32_t dummy - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern EFlashDriver EFLD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void efl_lld_init(void); - void efl_lld_start(EFlashDriver *eflp); - void efl_lld_stop(EFlashDriver *eflp); - const flash_descriptor_t *efl_lld_get_descriptor(void *instance); - flash_error_t efl_lld_read(void *instance, flash_offset_t offset, - size_t n, uint8_t *rp); - flash_error_t efl_lld_program(void *instance, flash_offset_t offset, - size_t n, const uint8_t *pp); - flash_error_t efl_lld_start_erase_all(void *instance); - flash_error_t efl_lld_start_erase_sector(void *instance, - flash_sector_t sector); - flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec); - flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EFL == TRUE */ - -#endif /* HAL_EFL_LLD_H */ - -/** @} */ +/* + ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_efl_lld.h + * @brief STM32L4+ Embedded Flash subsystem low level driver header. + * + * @addtogroup HAL_EFL + * @{ + */ + +#ifndef HAL_EFL_LLD_H +#define HAL_EFL_LLD_H + +#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name STM32L4xx configuration options + * @{ + */ +/** + * @brief Suggested wait time during erase operations polling. + */ +#if !defined(STM32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__) +#define STM32_FLASH_WAIT_TIME_MS 5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || \ + defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) || defined(__DOXYGEN__) + +/* Flash size register. */ +#define STM32_FLASH_SIZE_REGISTER 0x1FFF75E0 +#define STM32_FLASH_SIZE_SCALE 1024U + +/* + * Device flash size is: + * 1M for STM32L4+ suffix G devices + * 2M for STM32L4+ suffix I devices. + * + * For 1M devices SBM is organised as 128 x 8K pages. + * For 1M devices DBM is organised as 128 x 4K pages per bank. + * + * For 2M devices SBM is organised as 256 x 8K pages. + * For 2M devices DBM is organised as 256 x 4K pages per bank. + */ + +#define STM32_FLASH_SIZE_1M 1024U +#define STM32_FLASH_SIZE_2M 2048U +#define STM32_FLASH_SECTORS_TOTAL_1M 128 +#define STM32_FLASH_SECTORS_TOTAL_2M 256 + +/* Single bank mode bank 1 for 1M device.*/ +#define STM32_FLASH_SECTOR_SIZE_1M ((STM32_FLASH_SIZE_1M \ + * STM32_FLASH_SIZE_SCALE) \ + / STM32_FLASH_SECTORS_TOTAL_1M) + +/* Dual bank mode banks 1 & 2 for 1M device.*/ +#define STM32_FLASH_DUAL_SECTOR_SIZE_1M (STM32_FLASH_SECTOR_SIZE_1M / 2) + +/* Single bank mode bank 1 for 2M device.*/ +#define STM32_FLASH_SECTOR_SIZE_2M ((STM32_FLASH_SIZE_2M \ + * STM32_FLASH_SIZE_SCALE) \ + / STM32_FLASH_SECTORS_TOTAL_2M) + +/* Dual bank mode banks 1 & 2 for 2M device.*/ +#define STM32_FLASH_DUAL_SECTOR_SIZE_2M (STM32_FLASH_SECTOR_SIZE_2M / 2) + +#else +#error "This EFL driver does not support the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/* A flash size declaration. */ +typedef struct { + const flash_descriptor_t* desc; +} efl_lld_size_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level fields of the embedded flash driver structure. + */ +#define efl_lld_driver_fields \ + /* Flash registers.*/ \ + FLASH_TypeDef *flash; \ + const flash_descriptor_t *descriptor; + +/** + * @brief Low level fields of the embedded flash configuration structure. + */ +#define efl_lld_config_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint32_t dummy + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EFlashDriver EFLD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void efl_lld_init(void); + void efl_lld_start(EFlashDriver *eflp); + void efl_lld_stop(EFlashDriver *eflp); + const flash_descriptor_t *efl_lld_get_descriptor(void *instance); + flash_error_t efl_lld_read(void *instance, flash_offset_t offset, + size_t n, uint8_t *rp); + flash_error_t efl_lld_program(void *instance, flash_offset_t offset, + size_t n, const uint8_t *pp); + flash_error_t efl_lld_start_erase_all(void *instance); + flash_error_t efl_lld_start_erase_sector(void *instance, + flash_sector_t sector); + flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec); + flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EFL == TRUE */ + +#endif /* HAL_EFL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c index a4d03859f..8f11b6e71 100644 --- a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c +++ b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c @@ -348,7 +348,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp, /* PLL VCO frequency.*/ vcoclk = (selclk / (halfreq_t)mdiv) * (halfreq_t)ndiv; - if((vcoclk < slp->pllvco_min) || (vcoclk > slp->pllvco_max)) { + if ((vcoclk < slp->pllvco_min) || (vcoclk > slp->pllvco_max)) { return true; } @@ -368,7 +368,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp, if ((cfgr & RCC_PLLCFGR_PLLPEN) != 0U) { pclk = vcoclk / pdiv; - if((pclk < slp->pllp_min) || (pclk > slp->pllp_max)) { + if ((pclk < slp->pllp_min) || (pclk > slp->pllp_max)) { return true; } } @@ -378,7 +378,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp, if ((cfgr & RCC_PLLCFGR_PLLQEN) != 0U) { qclk = vcoclk / qdiv; - if((qclk < slp->pllq_min) || (qclk > slp->pllq_max)) { + if ((qclk < slp->pllq_min) || (qclk > slp->pllq_max)) { return true; } } @@ -388,7 +388,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp, if ((cfgr & RCC_PLLCFGR_PLLREN) != 0U) { rclk = vcoclk / rdiv; - if((rclk < slp->pllr_min) || (rclk > slp->pllr_max)) { + if ((rclk < slp->pllr_min) || (rclk > slp->pllr_max)) { return true; } } @@ -502,7 +502,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { } /* SYSCLK frequency.*/ - switch(ccp->rcc_cfgr & RCC_CFGR_SW_Msk) { + switch (ccp->rcc_cfgr & RCC_CFGR_SW_Msk) { case RCC_CFGR_SW_MSI: sysclk = msiclk; break; @@ -545,7 +545,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { } /* MCO clock.*/ - switch(ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) { + switch (ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) { case STM32_MCOSEL_NOCLOCK: mcoclk = 0U; break; diff --git a/os/hal/ports/STM32/STM32L4xx+/stm32_isr.h b/os/hal/ports/STM32/STM32L4xx+/stm32_isr.h index 9e25c8689..b8ef5a62e 100644 --- a/os/hal/ports/STM32/STM32L4xx+/stm32_isr.h +++ b/os/hal/ports/STM32/STM32L4xx+/stm32_isr.h @@ -160,7 +160,6 @@ #define STM32_I2C4_ERROR_NUMBER 83 #define STM32_I2C4_EVENT_NUMBER 84 - /* * OCTOSPI unit. */ diff --git a/os/hal/ports/STM32/STM32L5xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L5xx/stm32_rcc.h index a0b8b8910..f5ae2d5d0 100644 --- a/os/hal/ports/STM32/STM32L5xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L5xx/stm32_rcc.h @@ -525,7 +525,7 @@ * * @api */ -#define rccResetGTZC() /*rccResetAHB1(RCC_AHB1RST_GTZCRST)*/ +#define rccResetGTZC() /* Disabled rccResetAHB1(RCC_AHB1RST_GTZCRST) */ /** @} */ /** diff --git a/os/hal/ports/STM32/STM32MP1xx/hal_lld.h b/os/hal/ports/STM32/STM32MP1xx/hal_lld.h index f81442529..c96468067 100644 --- a/os/hal/ports/STM32/STM32MP1xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32MP1xx/hal_lld.h @@ -238,7 +238,6 @@ #define STM32_HSI_ENABLED TRUE #endif - /** * @brief HSI divider setting. * @note This initialization is performed only if TZEN=0 or MCKPROT=0 diff --git a/os/hal/ports/STM32/STM32WBxx/hal_lld.c b/os/hal/ports/STM32/STM32WBxx/hal_lld.c index 5ea6166b7..ba52b8b6e 100644 --- a/os/hal/ports/STM32/STM32WBxx/hal_lld.c +++ b/os/hal/ports/STM32/STM32WBxx/hal_lld.c @@ -1,243 +1,243 @@ -/* - ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Ilya Kharin. -*/ - -/** - * @file STM32WBxx/hal_lld.c - * @brief STM32WBxx HAL subsystem low level driver source. - * - * @addtogroup HAL - * @{ - */ - -#include "hal.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief CMSIS system core clock variable. - */ -uint32_t SystemCoreClock = STM32_HCLK; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Safe setting of flash ACR register. - * - * @param[in] acr value for the ACR register - */ -__STATIC_INLINE void flash_set_acr(uint32_t acr) { - - FLASH->ACR = acr; - while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (acr & FLASH_ACR_LATENCY_Msk)) { - /* Waiting for flash wait states setup.*/ - } -} - -/** - * @brief Configures the PWR unit. - * @note CR1, CR2 and CR5 are not initialized inside this function. - */ -__STATIC_INLINE void hal_lld_set_static_pwr(void) { - /* Static PWR configurations.*/ - PWR->CR3 = STM32_PWR_CR3; - PWR->CR4 = STM32_PWR_CR4; - PWR->PUCRA = STM32_PWR_PUCRA; - PWR->PDCRA = STM32_PWR_PDCRA; - PWR->PUCRB = STM32_PWR_PUCRB; - PWR->PDCRB = STM32_PWR_PDCRB; - PWR->PUCRC = STM32_PWR_PUCRC; - PWR->PDCRC = STM32_PWR_PDCRC; - PWR->PUCRD = STM32_PWR_PUCRD; - PWR->PDCRD = STM32_PWR_PDCRD; - PWR->PUCRE = STM32_PWR_PUCRE; - PWR->PDCRE = STM32_PWR_PDCRE; - PWR->PUCRH = STM32_PWR_PUCRH; - PWR->PDCRH = STM32_PWR_PDCRH; -} - -/** - * @brief Initializes static muxes and dividers. - */ -__STATIC_INLINE void hal_lld_set_static_clocks(void) { - uint32_t ccipr; - - /* Clock-related settings (dividers, MCO etc).*/ - RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK | - STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; - - /* Waiting for PPRE2, PPRE1 and HPRE applied. */ - while ((RCC->CFGR & (RCC_CFGR_PPRE2F_Msk | RCC_CFGR_PPRE1F_Msk | - RCC_CFGR_HPREF_Msk)) != - (RCC_CFGR_PPRE2F | RCC_CFGR_PPRE1F | RCC_CFGR_HPREF)) - ; - - /* CCIPR2 register initialization, note, must take care of the _OFF - pseudo settings.*/ - ccipr = STM32_RNGSEL | STM32_ADCSEL | STM32_CLK48SEL | - STM32_LPTIM2SEL | STM32_LPTIM1SEL | STM32_I2C1SEL | - STM32_USART1SEL | STM32_LPUART1SEL; -#if STM32_SAI1SEL != STM32_SAI1SEL_OFF - ccipr |= STM32_SAI1SEL; -#endif - RCC->CCIPR = ccipr; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - * - * @notapi - */ -void hal_lld_init(void) { - - /* DMA subsystems initialization.*/ -#if defined(STM32_DMA_REQUIRED) - dmaInit(); -#endif - - /* NVIC initialization.*/ - nvicInit(); - - /* IRQ subsystem initialization.*/ - irqInit(); - - /* Programmable voltage detector enable.*/ -#if STM32_PVD_ENABLE - PWR->CR2 = PWR_CR2_PVDE | (STM32_PLS & STM32_PLS_MASK); -#else - PWR->CR2 = 0; -#endif /* STM32_PVD_ENABLE */ - - /* Enabling independent VDDUSB.*/ -#if HAL_USE_USB - PWR->CR2 |= PWR_CR2_USV; -#endif /* HAL_USE_USB */ -} - -/** - * @brief STM32WBxx clocks and PLL initialization. - * @note All the involved constants come from the file @p board.h. - * @note This function should be invoked just after the system reset. - * - * @special - */ -void stm32_clock_init(void) { - -#if !STM32_NO_INIT - /* Reset of all peripherals. - Note, GPIOs are not reset because initialized before this point in - board files.*/ - rccResetAHB1(~0); - rccResetAHB2(~STM32_GPIO_EN_MASK); - rccResetAHB3(~0); - rccResetAPB1R1(~0); - rccResetAPB1R2(~0); - rccResetAPB2(~0); - - /* Flash setup for selected MSI speed setting.*/ - flash_set_acr(FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN | - STM32_MSI_FLASHBITS); - - /* Static PWR configurations.*/ - hal_lld_set_static_pwr(); - - /* Core voltage setup, backup domain access enabled and left open.*/ - PWR->CR1 = STM32_VOS | PWR_CR1_DBP; - - /* Additional PWR configurations.*/ - PWR->CR2 = STM32_PWR_CR2; - - /* Wait until regulator is stable. */ - while ((PWR->SR2 & PWR_SR2_VOSF) != 0) - ; - - /* MSI clock reset.*/ - msi_reset(); - - /* Backup domain reset.*/ - bd_reset(); - - /* Clocks setup.*/ - lse_init(); - lsi_init(); - msi_init(); - hsi16_init(); - hsi48_init(); - hse32_init(); - - /* Backup domain initializations.*/ - bd_init(); - - /* Static clocks setup.*/ - hal_lld_set_static_clocks(); - - /* PLLs activation, if required.*/ - pll_init(); - pllsai1_init(); - - /* Extended clock recovery register (HCLK2, HCLK4, HCLK5). */ - RCC->EXTCFGR = STM32_RFCSSSEL | STM32_C2HPRE | STM32_SHDHPRE; - - /* Waiting for C2HPRE and SHDHPRE. */ - while ((RCC->EXTCFGR & (RCC_EXTCFGR_C2HPREF_Msk | - RCC_EXTCFGR_SHDHPREF_Msk)) != - (RCC_EXTCFGR_C2HPREF | RCC_EXTCFGR_SHDHPREF)) - ; - - /* Set flash WS's for SYSCLK source */ - if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) { - flash_set_acr((FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS); - } - - /* Switching to the configured SYSCLK source if it is different from MSI.*/ -#if (STM32_SW != STM32_SW_MSI) - RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ - /* Wait until SYSCLK is stable.*/ - while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) - ; -#endif - - /* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */ - if (STM32_FLASHBITS < STM32_MSI_FLASHBITS) { - flash_set_acr((FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS); - } - -#endif /* STM32_NO_INIT */ -} - -/** @} */ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Ilya Kharin. +*/ + +/** + * @file STM32WBxx/hal_lld.c + * @brief STM32WBxx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief CMSIS system core clock variable. + */ +uint32_t SystemCoreClock = STM32_HCLK; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Safe setting of flash ACR register. + * + * @param[in] acr value for the ACR register + */ +__STATIC_INLINE void flash_set_acr(uint32_t acr) { + + FLASH->ACR = acr; + while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (acr & FLASH_ACR_LATENCY_Msk)) { + /* Waiting for flash wait states setup.*/ + } +} + +/** + * @brief Configures the PWR unit. + * @note CR1, CR2 and CR5 are not initialized inside this function. + */ +__STATIC_INLINE void hal_lld_set_static_pwr(void) { + /* Static PWR configurations.*/ + PWR->CR3 = STM32_PWR_CR3; + PWR->CR4 = STM32_PWR_CR4; + PWR->PUCRA = STM32_PWR_PUCRA; + PWR->PDCRA = STM32_PWR_PDCRA; + PWR->PUCRB = STM32_PWR_PUCRB; + PWR->PDCRB = STM32_PWR_PDCRB; + PWR->PUCRC = STM32_PWR_PUCRC; + PWR->PDCRC = STM32_PWR_PDCRC; + PWR->PUCRD = STM32_PWR_PUCRD; + PWR->PDCRD = STM32_PWR_PDCRD; + PWR->PUCRE = STM32_PWR_PUCRE; + PWR->PDCRE = STM32_PWR_PDCRE; + PWR->PUCRH = STM32_PWR_PUCRH; + PWR->PDCRH = STM32_PWR_PDCRH; +} + +/** + * @brief Initializes static muxes and dividers. + */ +__STATIC_INLINE void hal_lld_set_static_clocks(void) { + uint32_t ccipr; + + /* Clock-related settings (dividers, MCO etc).*/ + RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK | + STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; + + /* Waiting for PPRE2, PPRE1 and HPRE applied. */ + while ((RCC->CFGR & (RCC_CFGR_PPRE2F_Msk | RCC_CFGR_PPRE1F_Msk | + RCC_CFGR_HPREF_Msk)) != + (RCC_CFGR_PPRE2F | RCC_CFGR_PPRE1F | RCC_CFGR_HPREF)) + ; + + /* CCIPR2 register initialization, note, must take care of the _OFF + pseudo settings.*/ + ccipr = STM32_RNGSEL | STM32_ADCSEL | STM32_CLK48SEL | + STM32_LPTIM2SEL | STM32_LPTIM1SEL | STM32_I2C1SEL | + STM32_USART1SEL | STM32_LPUART1SEL; +#if STM32_SAI1SEL != STM32_SAI1SEL_OFF + ccipr |= STM32_SAI1SEL; +#endif + RCC->CCIPR = ccipr; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* DMA subsystems initialization.*/ +#if defined(STM32_DMA_REQUIRED) + dmaInit(); +#endif + + /* NVIC initialization.*/ + nvicInit(); + + /* IRQ subsystem initialization.*/ + irqInit(); + + /* Programmable voltage detector enable.*/ +#if STM32_PVD_ENABLE + PWR->CR2 = PWR_CR2_PVDE | (STM32_PLS & STM32_PLS_MASK); +#else + PWR->CR2 = 0; +#endif /* STM32_PVD_ENABLE */ + + /* Enabling independent VDDUSB.*/ +#if HAL_USE_USB + PWR->CR2 |= PWR_CR2_USV; +#endif /* HAL_USE_USB */ +} + +/** + * @brief STM32WBxx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* Reset of all peripherals. + Note, GPIOs are not reset because initialized before this point in + board files.*/ + rccResetAHB1(~0); + rccResetAHB2(~STM32_GPIO_EN_MASK); + rccResetAHB3(~0); + rccResetAPB1R1(~0); + rccResetAPB1R2(~0); + rccResetAPB2(~0); + + /* Flash setup for selected MSI speed setting.*/ + flash_set_acr(FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN | + STM32_MSI_FLASHBITS); + + /* Static PWR configurations.*/ + hal_lld_set_static_pwr(); + + /* Core voltage setup, backup domain access enabled and left open.*/ + PWR->CR1 = STM32_VOS | PWR_CR1_DBP; + + /* Additional PWR configurations.*/ + PWR->CR2 = STM32_PWR_CR2; + + /* Wait until regulator is stable. */ + while ((PWR->SR2 & PWR_SR2_VOSF) != 0) + ; + + /* MSI clock reset.*/ + msi_reset(); + + /* Backup domain reset.*/ + bd_reset(); + + /* Clocks setup.*/ + lse_init(); + lsi_init(); + msi_init(); + hsi16_init(); + hsi48_init(); + hse32_init(); + + /* Backup domain initializations.*/ + bd_init(); + + /* Static clocks setup.*/ + hal_lld_set_static_clocks(); + + /* PLLs activation, if required.*/ + pll_init(); + pllsai1_init(); + + /* Extended clock recovery register (HCLK2, HCLK4, HCLK5). */ + RCC->EXTCFGR = STM32_RFCSSSEL | STM32_C2HPRE | STM32_SHDHPRE; + + /* Waiting for C2HPRE and SHDHPRE. */ + while ((RCC->EXTCFGR & (RCC_EXTCFGR_C2HPREF_Msk | + RCC_EXTCFGR_SHDHPREF_Msk)) != + (RCC_EXTCFGR_C2HPREF | RCC_EXTCFGR_SHDHPREF)) + ; + + /* Set flash WS's for SYSCLK source */ + if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) { + flash_set_acr((FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS); + } + + /* Switching to the configured SYSCLK source if it is different from MSI.*/ +#if (STM32_SW != STM32_SW_MSI) + RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ + /* Wait until SYSCLK is stable.*/ + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; +#endif + + /* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */ + if (STM32_FLASHBITS < STM32_MSI_FLASHBITS) { + flash_set_acr((FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS); + } + +#endif /* STM32_NO_INIT */ +} + +/** @} */ diff --git a/os/hal/ports/STM32/STM32WBxx/hal_lld.h b/os/hal/ports/STM32/STM32WBxx/hal_lld.h index 9839d4ad6..72323a14a 100644 --- a/os/hal/ports/STM32/STM32WBxx/hal_lld.h +++ b/os/hal/ports/STM32/STM32WBxx/hal_lld.h @@ -1,1766 +1,1765 @@ -/* - ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Ilya Kharin. -*/ - -/** - * @file STM32WBxx/hal_lld.h - * @brief STM32WBxx HAL subsystem low level driver header. - * @pre This module requires the following macros to be defined in the - * @p board.h file: - * - STM32_LSECLK. - * - STM32_LSEDRV. - * - STM32_LSE_BYPASS (optionally). - * - STM32_HSE32CLK. - * . - * One of the following macros must also be defined: - * - STM32WB55xx. - * - STM32WB50xx. - * . - * - * @addtogroup HAL - * @{ - */ - -#ifndef HAL_LLD_H -#define HAL_LLD_H - -#include "stm32_registry.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Platform identification - * @{ - */ -#if defined(STM32WB55xx) || defined(__DOXYGEN__) -#define PLATFORM_NAME "STM32WBxx Ultra Low Power" - -#elif defined(STM32WB50xx) -#define PLATFORM_NAME "STM32WBxx Ultra Low Power Value Line" - -#else -#error "STM32WBxx device not specified" -#endif - -/** - * @brief Sub-family identifier. - */ -#if !defined(STM32WBXX) || defined(__DOXYGEN__) -#define STM32WBXX -#endif -/** @} */ - -/** - * @name PWR_CR1 register bits definitions - * @{ - */ -#define STM32_VOS_MASK (3 << 9) /**< Core voltage mask. */ -#define STM32_VOS_RANGE1 (1 << 9) /**< Core voltage 1.2 Volts. */ -#define STM32_VOS_RANGE2 (2 << 9) /**< Core voltage 1.0 Volts. */ -/** @} */ - -/** - * @name PWR_CR2 register bits definitions - * @{ - */ -#define STM32_PLS_MASK (7 << 1) /**< PLS bits mask. */ -#define STM32_PLS_LEV0 (0 << 1) /**< PVD level 0. */ -#define STM32_PLS_LEV1 (1 << 1) /**< PVD level 1. */ -#define STM32_PLS_LEV2 (2 << 1) /**< PVD level 2. */ -#define STM32_PLS_LEV3 (3 << 1) /**< PVD level 3. */ -#define STM32_PLS_LEV4 (4 << 1) /**< PVD level 4. */ -#define STM32_PLS_LEV5 (5 << 1) /**< PVD level 5. */ -#define STM32_PLS_LEV6 (6 << 1) /**< PVD level 6. */ -#define STM32_PLS_EXT (7 << 1) /**< PVD level 7. */ -/** @} */ - -/** - * @brief HSE SYSCLK and PLL M divider prescaler. - */ -#define STM32_HSE32PRE_MASK (1 << 20) /**< HSEPRE mask. */ -#define STM32_HSE32PRE_DIV1 (0 << 20) /**< HSE divided by 1. */ -#define STM32_HSE32PRE_DIV2 (1 << 20) /**< HSE divided by 2. */ -/** @} */ - -/** - * @name RCC_CFGR register bits definitions - * @{ - */ -#define STM32_SW_MASK (3 << 0) /**< SW field mask. */ -#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */ -#define STM32_SW_HSI16 (1 << 0) /**< SYSCLK source is HSI. */ -#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */ -#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */ - -/* STM32WB CMSIS headers don't have these macros */ -#if !defined(RCC_CFGR_SW_MSI) -#define RCC_CFGR_SW_MSI (0x0U << RCC_CFGR_SW_Pos) -#endif -#if !defined(RCC_CFGR_SW_HSI) -#define RCC_CFGR_SW_HSI (0x1U << RCC_CFGR_SW_Pos) -#endif -#if !defined(RCC_CFGR_SW_HSE) -#define RCC_CFGR_SW_HSE (0x2U << RCC_CFGR_SW_Pos) -#endif -#if !defined(RCC_CFGR_SW_PLL) -#define RCC_CFGR_SW_PLL (0x3U << RCC_CFGR_SW_Pos) -#endif - -#if !defined(RCC_CFGR_SWS_MSI) -#define RCC_CFGR_SWS_MSI (0x0U << RCC_CFGR_SWS_Pos) -#endif -#if !defined(RCC_CFGR_SWS_HSI) -#define RCC_CFGR_SWS_HSI (0x1U << RCC_CFGR_SWS_Pos) -#endif -#if !defined(RCC_CFGR_SWS_HSE) -#define RCC_CFGR_SWS_HSE (0x2U << RCC_CFGR_SWS_Pos) -#endif -#if !defined(RCC_CFGR_SWS_PLL) -#define RCC_CFGR_SWS_PLL (0x3U << RCC_CFGR_SWS_Pos) -#endif - -#define STM32_STOPWUCK_MASK (1 << 15) /**< STOPWUCK field mask. */ -#define STM32_STOPWUCK_MSI (0 << 15) /**< Wakeup clock is MSI. */ -#define STM32_STOPWUCK_HSI16 (1 << 15) /**< Wakeup clock is HSI16. */ - -#define STM32_MCOSEL_MASK (15 << 24) /**< MCOSEL field mask. */ -#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ -#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */ -#define STM32_MCOSEL_MSI (2 << 24) /**< MSI clock on MCO pin. */ -#define STM32_MCOSEL_HSI16 (3 << 24) /**< HSI16 clock on MCO pin. */ -#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. - (after stabilization) */ -#define STM32_MCOSEL_PLLRCLK (5 << 24) /**< PLLR clock on MCO pin. */ -#define STM32_MCOSEL_LSI1 (6 << 24) /**< LSI clock on MCO pin. */ -#define STM32_MCOSEL_LSI2 (7 << 24) /**< LSI clock on MCO pin. */ -#define STM32_MCOSEL_LSE (8 << 24) /**< LSE clock on MCO pin. */ -#define STM32_MCOSEL_HSI48 (9 << 24) /**< HSI48 clock on MCO pin. */ -#define STM32_MCOSEL_HSE2 (4 << 24) /**< HSE clock on MCO pin. - (before stabilization) */ - -#define STM32_MCOPRE_MASK (7 << 28) /**< MCOPRE field mask. */ -#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */ -#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 2. */ -#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 4. */ -#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 8. */ -#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 16. */ -/** @} */ - -/** - * @name RCC_EXTCFGR register bits definitions - * @{ - */ -/** - * @brief HCLK5 clock source (RFC and APB3). - */ -#define STM32_RFCSSSEL_MASK (1 << 20) /**< RFCSS field mask. */ -#define STM32_RFCSSSEL_HSI16 (0 << 20) /**< RFCSS source is HSI16. */ -#define STM32_RFCSSSEL_HSE (1 << 20) /**< RFCSS source is HSE/2. */ - -/** - * @brief HCLK4 shared prescaler (AHB3, Flash memory and SRAM2). - */ -#define STM32_SHDHPRE_MASK (15 << 0) /**< SHDHPRE field mask. */ -#define STM32_SHDHPRE_DIV1 (0 << 0) /**< SYSCLK divided by 1. */ -#define STM32_SHDHPRE_DIV2 (8 << 0) /**< SYSCLK divided by 2. */ -#define STM32_SHDHPRE_DIV3 (1 << 0) /**< SYSCLK divided by 3. */ -#define STM32_SHDHPRE_DIV4 (9 << 0) /**< SYSCLK divided by 4. */ -#define STM32_SHDHPRE_DIV5 (2 << 0) /**< SYSCLK divided by 5. */ -#define STM32_SHDHPRE_DIV6 (5 << 0) /**< SYSCLK divided by 6. */ -#define STM32_SHDHPRE_DIV8 (10 << 0) /**< SYSCLK divided by 8. */ -#define STM32_SHDHPRE_DIV10 (6 << 0) /**< SYSCLK divided by 10. */ -#define STM32_SHDHPRE_DIV16 (11 << 0) /**< SYSCLK divided by 16. */ -#define STM32_SHDHPRE_DIV32 (7 << 0) /**< SYSCLK divided by 32. */ -#define STM32_SHDHPRE_DIV64 (12 << 0) /**< SYSCLK divided by 64. */ -#define STM32_SHDHPRE_DIV128 (13 << 0) /**< SYSCLK divided by 128. */ -#define STM32_SHDHPRE_DIV256 (14 << 0) /**< SYSCLK divided by 256. */ -#define STM32_SHDHPRE_DIV512 (15 << 0) /**< SYSCLK divided by 512. */ - -/** - * @brief HCLK2 prescaler (CPU2). - */ -#define STM32_C2HPRE_MASK (15 << 4) /**< C2HPRE field mask. */ -#define STM32_C2HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ -#define STM32_C2HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ -#define STM32_C2HPRE_DIV3 (1 << 4) /**< SYSCLK divided by 3. */ -#define STM32_C2HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ -#define STM32_C2HPRE_DIV5 (2 << 4) /**< SYSCLK divided by 5. */ -#define STM32_C2HPRE_DIV6 (5 << 4) /**< SYSCLK divided by 6. */ -#define STM32_C2HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ -#define STM32_C2HPRE_DIV10 (6 << 4) /**< SYSCLK divided by 10. */ -#define STM32_C2HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ -#define STM32_C2HPRE_DIV32 (7 << 4) /**< SYSCLK divided by 32. */ -#define STM32_C2HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ -#define STM32_C2HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ -#define STM32_C2HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ -#define STM32_C2HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ - -/** - * @brief HCLK5 and APB3 clock source. - */ -#define STM32_RFCSS_MASK (1 << 20) /**< RFCSS field mask. */ -#define STM32_RFCSS_HSI16 (0 << 20) /**< HSI16 on HCLK5 and APB3. */ -#define STM32_RFCSS_HSEDIV2 (1 << 20) /**< HSE/2 on HCLK5 and APB3. */ -/** @} */ - -/** - * @name RCC_PLLCFGR register bits definitions - * @{ - */ -#define STM32_PLLSRC_MASK (3 << 0) /**< PLL clock source mask. */ -#define STM32_PLLSRC_NOCLOCK (0 << 0) /**< PLL clock source disabled. */ -#define STM32_PLLSRC_MSI (1 << 0) /**< PLL clock source is MSI. */ -#define STM32_PLLSRC_HSI16 (2 << 0) /**< PLL clock source is HSI16. */ -#define STM32_PLLSRC_HSE (3 << 0) /**< PLL clock source is HSE. */ -/** @} */ - -/** - * @name RCC_CCIPR register bits definitions - * @{ - */ -#define STM32_USART1SEL_MASK (3 << 0) /**< USART1SEL mask. */ -#define STM32_USART1SEL_PCLK2 (0 << 0) /**< USART1 source is PCLK2. */ -#define STM32_USART1SEL_SYSCLK (1 << 0) /**< USART1 source is SYSCLK. */ -#define STM32_USART1SEL_HSI16 (2 << 0) /**< USART1 source is HSI16. */ -#define STM32_USART1SEL_LSE (3 << 0) /**< USART1 source is LSE. */ - -#define STM32_LPUART1SEL_MASK (3 << 10) /**< LPUART1 mask. */ -#define STM32_LPUART1SEL_PCLK1 (0 << 10) /**< LPUART1 source is PCLK1. */ -#define STM32_LPUART1SEL_SYSCLK (1 << 10) /**< LPUART1 source is SYSCLK. */ -#define STM32_LPUART1SEL_HSI16 (2 << 10) /**< LPUART1 source is HSI16. */ -#define STM32_LPUART1SEL_LSE (3 << 10) /**< LPUART1 source is LSE. */ - -#define STM32_I2C1SEL_MASK (3 << 12) /**< I2C1SEL mask. */ -#define STM32_I2C1SEL_PCLK1 (0 << 12) /**< I2C1 source is PCLK1. */ -#define STM32_I2C1SEL_SYSCLK (1 << 12) /**< I2C1 source is SYSCLK. */ -#define STM32_I2C1SEL_HSI16 (2 << 12) /**< I2C1 source is HSI16. */ - -#define STM32_I2C3SEL_MASK (3 << 16) /**< I2C3SEL mask. */ -#define STM32_I2C3SEL_PCLK1 (0 << 16) /**< I2C3 source is PCLK1. */ -#define STM32_I2C3SEL_SYSCLK (1 << 16) /**< I2C3 source is SYSCLK. */ -#define STM32_I2C3SEL_HSI16 (2 << 16) /**< I2C3 source is HSI16. */ - -#define STM32_LPTIM1SEL_MASK (3 << 18) /**< LPTIM1SEL mask. */ -#define STM32_LPTIM1SEL_PCLK1 (0 << 18) /**< LPTIM1 source is PCLK1. */ -#define STM32_LPTIM1SEL_LSI (1 << 18) /**< LPTIM1 source is LSI. */ -#define STM32_LPTIM1SEL_HSI16 (2 << 18) /**< LPTIM1 source is HSI16. */ -#define STM32_LPTIM1SEL_LSE (3 << 18) /**< LPTIM1 source is LSE. */ - -#define STM32_LPTIM2SEL_MASK (3 << 20) /**< LPTIM2SEL mask. */ -#define STM32_LPTIM2SEL_PCLK1 (0 << 20) /**< LPTIM2 source is PCLK1. */ -#define STM32_LPTIM2SEL_LSI (1 << 20) /**< LPTIM2 source is LSI. */ -#define STM32_LPTIM2SEL_HSI16 (2 << 20) /**< LPTIM2 source is HSI16. */ -#define STM32_LPTIM2SEL_LSE (3 << 20) /**< LPTIM2 source is LSE. */ - -#define STM32_SAI1SEL_MASK (3 << 22) /**< SAI1SEL mask. */ -#define STM32_SAI1SEL_PLLSAI1PCLK (0 << 22) /**< SAI1 source is PLLSAI1PCLK.*/ -#define STM32_SAI1SEL_PLLPCLK (2 << 22) /**< SAI1 source is PLLPCLK. */ -#define STM32_SAI1SEL_EXTCLK (3 << 22) /**< SAI1 source is external. */ -#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/ - -#define STM32_CLK48SEL_MASK (3 << 26) /**< CLK48SEL mask. */ -#define STM32_CLK48SEL_HSI48 (0 << 26) /**< CLK48 source is HSI48. */ -#define STM32_CLK48SEL_PLLSAI1QCLK (1 << 26) /**< CLK48 source is SAI1-Q. */ -#define STM32_CLK48SEL_PLLQCLK (2 << 26) /**< CLK48 source is PLLQCLK. */ -#define STM32_CLK48SEL_MSI (3 << 26) /**< CLK48 source is MSI. */ - -#define STM32_ADCSEL_MASK (3 << 28) /**< ADCSEL mask. */ -#define STM32_ADCSEL_NOCLK (0 << 28) /**< ADC clock disabled. */ -#define STM32_ADCSEL_PLLSAI1RCLK (1 << 28) /**< ADC source is PLLSAI1RCLK. */ -#define STM32_ADCSEL_PLLPCLK (2 << 28) /**< ADC source is PLLPCLK. */ -#define STM32_ADCSEL_SYSCLK (3 << 28) /**< ADC source is SYSCLK. */ - -#define STM32_RNGSEL_MASK (3 << 30) /**< RNGSEL mask. */ -#define STM32_RNGSEL_48CLK (0 << 30) /**< RNG source is CLK48SEL. */ -#define STM32_RNGSEL_LSI (1 << 30) /**< RNG source is LSI. */ -#define STM32_RNGSEL_LSE (3 << 30) /**< RNG source is LSE. */ -/** @} */ - -/** - * @name RCC_BDCR register bits definitions - * @{ - */ -#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */ -#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */ -#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */ -#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */ -#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */ - -#define STM32_LSCOSEL_MASK (3 << 24) /**< LSCO pin clock source. */ -#define STM32_LSCOSEL_NOCLOCK (0 << 24) /**< No clock on LSCO pin. */ -#define STM32_LSCOSEL_LSI (1 << 24) /**< LSI on LSCO pin. */ -#define STM32_LSCOSEL_LSE (3 << 24) /**< LSE on LSCO pin. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief Disables the PWR/RCC initialization in the HAL. - */ -#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) -#define STM32_NO_INIT FALSE -#endif - -/** - * @brief Core voltage selection. - * @note This setting affects all the performance and clock related - * settings, the maximum performance is only obtainable selecting - * the maximum voltage. - */ -#if !defined(STM32_VOS) || defined(__DOXYGEN__) -#define STM32_VOS STM32_VOS_RANGE1 -#endif - -/** - * @brief PWR CR2 register initialization value. - */ -#if !defined(STM32_PWR_CR2) || defined(__DOXYGEN__) -#define STM32_PWR_CR2 (PWR_CR2_PLS_0) -#endif - -/** - * @brief PWR CR3 register initialization value. - */ -#if !defined(STM32_PWR_CR3) || defined(__DOXYGEN__) -#define STM32_PWR_CR3 (PWR_CR3_EIWUL) -#endif - -/** - * @brief PWR CR4 register initialization value. - */ -#if !defined(STM32_PWR_CR4) || defined(__DOXYGEN__) -#define STM32_PWR_CR4 (0U) -#endif - -/** - * @brief PWR PUCRA register initialization value. - */ -#if !defined(STM32_PWR_PUCRA) || defined(__DOXYGEN__) -#define STM32_PWR_PUCRA (0U) -#endif - -/** - * @brief PWR PDCRA register initialization value. - */ -#if !defined(STM32_PWR_PDCRA) || defined(__DOXYGEN__) -#define STM32_PWR_PDCRA (0U) -#endif - -/** - * @brief PWR PUCRB register initialization value. - */ -#if !defined(STM32_PWR_PUCRB) || defined(__DOXYGEN__) -#define STM32_PWR_PUCRB (0U) -#endif - -/** - * @brief PWR PDCRB register initialization value. - */ -#if !defined(STM32_PWR_PDCRB) || defined(__DOXYGEN__) -#define STM32_PWR_PDCRB (0U) -#endif - -/** - * @brief PWR PUCRC register initialization value. - */ -#if !defined(STM32_PWR_PUCRC) || defined(__DOXYGEN__) -#define STM32_PWR_PUCRC (0U) -#endif - -/** - * @brief PWR PDCRC register initialization value. - */ -#if !defined(STM32_PWR_PDCRC) || defined(__DOXYGEN__) -#define STM32_PWR_PDCRC (0U) -#endif - -/** - * @brief PWR PUCRD register initialization value. - */ -#if !defined(STM32_PWR_PUCRD) || defined(__DOXYGEN__) -#define STM32_PWR_PUCRD (0U) -#endif - -/** - * @brief PWR PDCRD register initialization value. - */ -#if !defined(STM32_PWR_PDCRD) || defined(__DOXYGEN__) -#define STM32_PWR_PDCRD (0U) -#endif - -/** - * @brief PWR PUCRE register initialization value. - */ -#if !defined(STM32_PWR_PUCRE) || defined(__DOXYGEN__) -#define STM32_PWR_PUCRE (0U) -#endif - -/** - * @brief PWR PDCRE register initialization value. - */ -#if !defined(STM32_PWR_PDCRE) || defined(__DOXYGEN__) -#define STM32_PWR_PDCRE (0U) -#endif - -/** - * @brief PWR PUCRF register initialization value. - */ -#if !defined(STM32_PWR_PUCRF) || defined(__DOXYGEN__) -#define STM32_PWR_PUCRF (0U) -#endif - -/** - * @brief PWR PDCRF register initialization value. - */ -#if !defined(STM32_PWR_PDCRF) || defined(__DOXYGEN__) -#define STM32_PWR_PDCRF (0U) -#endif - -/** - * @brief PWR PUCRG register initialization value. - */ -#if !defined(STM32_PWR_PUCRG) || defined(__DOXYGEN__) -#define STM32_PWR_PUCRG (0U) -#endif - -/** - * @brief PWR PDCRG register initialization value. - */ -#if !defined(STM32_PWR_PDCRG) || defined(__DOXYGEN__) -#define STM32_PWR_PDCRG (0U) -#endif - -/** - * @brief PWR PUCRH register initialization value. - */ -#if !defined(STM32_PWR_PUCRH) || defined(__DOXYGEN__) -#define STM32_PWR_PUCRH (0U) -#endif - -/** - * @brief PWR PDCRH register initialization value. - */ -#if !defined(STM32_PWR_PDCRH) || defined(__DOXYGEN__) -#define STM32_PWR_PDCRH (0U) -#endif - -/** - * @brief Enables or disables the programmable voltage detector. - */ -#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) -#define STM32_PVD_ENABLE FALSE -#endif - -/** - * @brief Sets voltage level for programmable voltage detector. - */ -#if !defined(STM32_PLS) || defined(__DOXYGEN__) -#define STM32_PLS STM32_PLS_LEV0 -#endif - -/** - * @brief Enables or disables the HSI16 clock source. - */ -#if !defined(STM32_HSI16_ENABLED) || defined(__DOXYGEN__) -#define STM32_HSI16_ENABLED TRUE -#endif - -/** - * @brief Enables or disables the HSI48 clock source. - */ -#if !defined(STM32_HSI48_ENABLED) || defined(__DOXYGEN__) -#define STM32_HSI48_ENABLED FALSE -#endif - -/** - * @brief Enables or disables the LSI clock source. - */ -#if !defined(STM32_LSI1_ENABLED) || defined(__DOXYGEN__) -#define STM32_LSI1_ENABLED TRUE -#endif - -/** - * @brief Enables or disables the HSE clock source. - */ -#if !defined(STM32_HSE32_ENABLED) || defined(__DOXYGEN__) -#define STM32_HSE32_ENABLED FALSE -#endif - -/** - * @brief Enables or disables the LSE clock source. - */ -#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) -#define STM32_LSE_ENABLED FALSE -#endif - -/** - * @brief Enables or disables the MSI PLL on LSE clock source. - */ -#if !defined(STM32_MSIPLL_ENABLED) || defined(__DOXYGEN__) -#define STM32_MSIPLL_ENABLED FALSE -#endif - -/** - * @brief MSI frequency setting. - */ -#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__) -#define STM32_MSIRANGE STM32_MSIRANGE_4M -#endif - -/** - * @brief HSE32 prescaler value. - */ -#if !defined(STM32_HSE32PRE) || defined(__DOXYGEN__) -#define STM32_HSE32PRE STM32_HSE32PRE_DIV1 -#endif - -/** - * @brief Main clock source selection. - * @note If the selected clock source is not the PLL then the PLL is not - * initialized and started. - * @note The default value is calculated for a 32MHz system clock from - * the internal 4MHz MSI clock. - */ -#if !defined(STM32_SW) || defined(__DOXYGEN__) -#define STM32_SW STM32_SW_PLL -#endif - -/** - * @brief Clock source for the PLL. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 32MHz system clock from - * the internal 4MHz MSI clock. - */ -#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) -#define STM32_PLLSRC STM32_PLLSRC_MSI -#endif - -/** - * @brief PLLM divider value. - * @note The allowed values are 1..8. - * @note The default value is calculated for a 32MHz system clock from - * the internal 4MHz MSI clock. - */ -#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLM_VALUE 1 -#endif - -/** - * @brief PLLN multiplier value. - * @note The allowed values are 8..86. - * @note The default value is calculated for a 32MHz system clock from - * the internal 4MHz MSI clock. - */ -#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLN_VALUE 32 -#endif - -/** - * @brief PLLP divider value. - * @note The allowed values are 2..31. - */ -#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLP_VALUE 2 -#endif - -/** - * @brief PLLQ divider value. - * @note The allowed values are 2, 4, 6, 8. - */ -#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLQ_VALUE 2 -#endif - -/** - * @brief PLLR divider value. - * @note The allowed values are 2, 4, 6, 8. - * @note The default value is calculated for a 32MHz system clock from - * the internal 4MHz MSI clock. - */ -#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLR_VALUE 2 -#endif - -/** - * @brief HCLK1 (CPU1, AHB1, AHB2, AHB3 and SRAM1) prescaler value. - * @note The default value is calculated for a 32MHz system clock from - * the internal 4MHz MSI clock. - */ -#if !defined(STM32_HPRE) || defined(__DOXYGEN__) -#define STM32_HPRE STM32_HPRE_DIV1 -#endif - -/** - * @brief APB1 prescaler value. - */ -#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) -#define STM32_PPRE1 STM32_PPRE1_DIV1 -#endif - -/** - * @brief APB2 prescaler value. - */ -#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) -#define STM32_PPRE2 STM32_PPRE2_DIV1 -#endif - -/** - * @brief HCLK2 (CPU2) prescaler value. - * @note The default value is calculated for a 32MHz system clock from - * the internal 4MHz MSI clock. - */ -#if !defined(STM32_C2HPRE) || defined(__DOXYGEN__) -#define STM32_C2HPRE STM32_C2HPRE_DIV2 -#endif - -/** - * @brief HCLK4 (AHB4, Flash memory and SRAM2) prescaler value. - */ -#if !defined(STM32_SHDHPRE) || defined(__DOXYGEN__) -#define STM32_SHDHPRE STM32_SHDHPRE_DIV1 -#endif - -/** - * @brief HCLK5 (APB3, AHB5 and Radio system) clock source. - */ -#if !defined(STM32_RFCSSSEL) || defined(__DOXYGEN__) -#define STM32_RFCSSSEL STM32_RFCSSSEL_HSI16 -#endif - -/** - * @brief STOPWUCK clock setting. - */ -#if !defined(STM32_STOPWUCK) || defined(__DOXYGEN__) -#define STM32_STOPWUCK STM32_STOPWUCK_MSI -#endif - -/** - * @brief MCO clock source. - */ -#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) -#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#endif - -/** - * @brief MCO divider setting. - */ -#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__) -#define STM32_MCOPRE STM32_MCOPRE_DIV1 -#endif - -/** - * @brief LSCO clock source. - */ -#if !defined(STM32_LSCOSEL) || defined(__DOXYGEN__) -#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK -#endif - -/** - * @brief PLLSAI1N multiplier value. - * @note The allowed values are 4..86. - */ -#if !defined(STM32_PLLSAI1N_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLSAI1N_VALUE 24 -#endif - -/** - * @brief PLLSAI1P divider value. - * @note The allowed values are 2..32. - */ -#if !defined(STM32_PLLSAI1P_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLSAI1P_VALUE 2 -#endif - -/** - * @brief PLLSAI1Q divider value. - * @note The allowed values are 2..8. - */ -#if !defined(STM32_PLLSAI1Q_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLSAI1Q_VALUE 2 -#endif - -/** - * @brief PLLSAI1R divider value. - * @note The allowed values are 2..8. - */ -#if !defined(STM32_PLLSAI1R_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLSAI1R_VALUE 2 -#endif - -/** - * @brief USART1 clock source. - */ -#if !defined(STM32_USART1SEL) || defined(__DOXYGEN__) -#define STM32_USART1SEL STM32_USART1SEL_PCLK2 -#endif - -/** - * @brief LPUART1 clock source. - */ -#if !defined(STM32_LPUART1SEL) || defined(__DOXYGEN__) -#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK1 -#endif - -/** - * @brief I2C1 clock source. - */ -#if !defined(STM32_I2C1SEL) || defined(__DOXYGEN__) -#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 -#endif - -/** - * @brief I2C3 clock source. - */ -#if !defined(STM32_I2C3SEL) || defined(__DOXYGEN__) -#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 -#endif - -/** - * @brief LPTIM1 clock source. - */ -#if !defined(STM32_LPTIM1SEL) || defined(__DOXYGEN__) -#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 -#endif - -/** - * @brief LPTIM2 clock source. - */ -#if !defined(STM32_LPTIM2SEL) || defined(__DOXYGEN__) -#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 -#endif - -/** - * @brief SAI1SEL value (SAI1 clock source). - */ -#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__) -#define STM32_SAI1SEL STM32_SAI1SEL_OFF -#endif - -/** - * @brief CLK48SEL value (48MHz clock source). - */ -#if !defined(STM32_CLK48SEL) || defined(__DOXYGEN__) -#define STM32_CLK48SEL STM32_CLK48SEL_PLLQCLK -// #define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1QCLK -#endif - -/** - * @brief ADCSEL value (ADCs clock source). - */ -#if !defined(STM32_ADCSEL) || defined(__DOXYGEN__) -#define STM32_ADCSEL STM32_ADCSEL_SYSCLK -#endif - -/** - * @brief RNGSEL value (RNGs clock source). - */ -#if !defined(STM32_RNGSEL) || defined(__DOXYGEN__) -#define STM32_RNGSEL STM32_RNGSEL_48CLK -#endif - -/** - * @brief RTC/LCD clock source. - */ -#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) -#define STM32_RTCSEL STM32_RTCSEL_LSI -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* - * Configuration-related checks. - */ -#if !defined(STM32WBxx_MCUCONF) -#error "Using a wrong mcuconf.h file, STM32WBxx_MCUCONF not defined" -#endif - -/* - * Board files sanity checks. - */ -#if !defined(STM32_LSECLK) -#error "STM32_LSECLK not defined in board.h" -#endif - -#if !defined(STM32_LSEDRV) -#error "STM32_LSEDRV not defined in board.h" -#endif - -/* Voltage related limits.*/ -#if (STM32_VOS == STM32_VOS_RANGE1) || defined(__DOXYGEN__) -/** - * @name System Limits - * @{ - */ -/** - * @brief Maximum SYSCLK clock frequency at current voltage setting. - */ -#define STM32_SYSCLK_MAX 64000000 - -/** - * @brief Maximum C2HPRE clock frequency at current voltage setting. - */ -#define STM32_C2HPRE_MAX 32000000 - -/** - * @brief Maximum LSE clock frequency. - */ -#define STM32_LSECLK_MAX 32768 - -/** - * @brief Maximum LSE clock frequency using an external source. - */ -#define STM32_LSECLK_BYP_MAX 1000000 - -/** - * @brief Minimum LSE clock frequency. - */ -#define STM32_LSECLK_MIN 32768 - -/** - * @brief Minimum LSE clock frequency using an external source. - */ -#define STM32_LSECLK_BYP_MIN 32768 - -/** - * @brief Maximum PLLs input clock frequency. - */ -#define STM32_PLLIN_MAX 16000000 - -/** - * @brief Minimum PLLs input clock frequency. - */ -#define STM32_PLLIN_MIN 2660000 - -/** - * @brief Maximum VCO clock frequency at current voltage setting. - */ -#define STM32_PLLVCO_MAX 344000000 - -/** - * @brief Minimum VCO clock frequency at current voltage setting. - */ -#define STM32_PLLVCO_MIN 96000000 - -/** - * @brief Maximum PLL-P output clock frequency. - */ -#define STM32_PLLP_MAX 64000000 - -/** - * @brief Minimum PLL-P output clock frequency. - */ -#define STM32_PLLP_MIN 2000000 - -/** - * @brief Maximum PLL-Q output clock frequency. - */ -#define STM32_PLLQ_MAX 64000000 - -/** - * @brief Minimum PLL-Q output clock frequency. - */ -#define STM32_PLLQ_MIN 8000000 - -/** - * @brief Maximum PLL-R output clock frequency. - */ -#define STM32_PLLR_MAX 64000000 - -/** - * @brief Minimum PLL-R output clock frequency. - */ -#define STM32_PLLR_MIN 8000000 - -/** - * @brief Maximum VCO clock frequency at current voltage setting. - */ -#define STM32_PLLSAI1VCO_MAX 344000000 - -/** - * @brief Minimum VCO clock frequency at current voltage setting. - */ -#define STM32_PLLSAI1VCO_MIN 64000000 - -/** - * @brief Maximum APB1 clock frequency. - */ -#define STM32_PCLK1_MAX 64000000 - -/** - * @brief Maximum APB2 clock frequency. - */ -#define STM32_PCLK2_MAX 64000000 - -/** - * @brief Maximum ADC clock frequency. - */ -#define STM32_ADCCLK_MAX 64000000 -/** @} */ - -/** - * @name Flash Wait states - * @{ - */ -#define STM32_0WS_THRESHOLD 18000000 -#define STM32_1WS_THRESHOLD 36000000 -#define STM32_2WS_THRESHOLD 54000000 -/** @} */ - -#elif STM32_VOS == STM32_VOS_RANGE2 -#define STM32_SYSCLK_MAX 16000000 -#define STM32_C2HPRE_MAX 16000000 -#define STM32_LSECLK_MAX 32768 -#define STM32_LSECLK_BYP_MAX 1000000 -#define STM32_LSECLK_MIN 32768 -#define STM32_LSECLK_BYP_MIN 32768 -#define STM32_PLLIN_MAX 16000000 -#define STM32_PLLIN_MIN 2660000 -#define STM32_PLLVCO_MAX 128000000 -#define STM32_PLLVCO_MIN 64000000 -#define STM32_PLLSAI1VCO_MAX 128000000 -#define STM32_PLLSAI1VCO_MIN 64000000 -#define STM32_PLLP_MAX 16000000 -#define STM32_PLLP_MIN 2000000 -#define STM32_PLLQ_MAX 16000000 -#define STM32_PLLQ_MIN 8000000 -#define STM32_PLLR_MAX 16000000 -#define STM32_PLLR_MIN 8000000 -#define STM32_PCLK1_MAX 26000000 -#define STM32_PCLK2_MAX 26000000 -#define STM32_ADCCLK_MAX 26000000 - -#define STM32_0WS_THRESHOLD 6000000 -#define STM32_1WS_THRESHOLD 12000000 -#define STM32_2WS_THRESHOLD 16000000 - -#else -#error "invalid STM32_VOS value specified" -#endif - -/** - * @name PLL dividers limits - * @{ - */ -#define STM32_PLLM_VALUE_MAX 8 -#define STM32_PLLM_VALUE_MIN 1 -#define STM32_PLLN_VALUE_MAX 127 -#define STM32_PLLN_VALUE_MIN 6 -#define STM32_PLLR_VALUE_MAX 8 -#define STM32_PLLR_VALUE_MIN 2 -#define STM32_PLLQ_VALUE_MAX 8 -#define STM32_PLLQ_VALUE_MIN 2 -#define STM32_PLLP_VALUE_MAX 32 -#define STM32_PLLP_VALUE_MIN 2 -/** @} */ - -/** - * @name PLLSAI1 dividers limits - * @{ - */ -#define STM32_PLLSAI1N_VALUE_MAX 86 -#define STM32_PLLSAI1N_VALUE_MIN 4 -#define STM32_PLLSAI1R_VALUE_MAX 8 -#define STM32_PLLSAI1R_VALUE_MIN 2 -#define STM32_PLLSAI1Q_VALUE_MAX 8 -#define STM32_PLLSAI1Q_VALUE_MIN 2 -#define STM32_PLLSAI1P_VALUE_MAX 32 -#define STM32_PLLSAI1P_VALUE_MIN 2 -/** @} */ - -/* Clock handlers.*/ -#include "stm32_bd.inc" -#include "stm32_lse.inc" -#include "stm32_lsi_v2.inc" -#include "stm32_msi_v2.inc" -#include "stm32_hsi16.inc" -#include "stm32_hsi48.inc" -#include "stm32_hse32.inc" - -/* - * HSI16 related checks. - */ -#if STM32_HSI16_ENABLED -#else /* !STM32_HSI16_ENABLED */ - -#if STM32_SW == STM32_SW_HSI16 -#error "HSI16 not enabled, required by STM32_SW" -#endif - -#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI16) -#error "HSI16 not enabled, required by STM32_SW and STM32_PLLSRC" -#endif - -#if (STM32_MCOSEL == STM32_MCOSEL_HSI16) || \ - ((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSI16)) -#error "HSI16 not enabled, required by STM32_MCOSEL" -#endif - -#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1PCLK) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSI16) -#error "HSI16 not enabled, required by STM32_SAI1SEL" -#endif - -#if (STM32_USART1SEL == STM32_USART1SEL_HSI16) -#error "HSI16 not enabled, required by STM32_USART1SEL" -#endif -#if (STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16) -#error "HSI16 not enabled, required by STM32_LPUART1SEL" -#endif - -#if (STM32_I2C1SEL == STM32_I2C1SEL_HSI16) -#error "HSI16 not enabled, required by I2C1SEL" -#endif -#if (STM32_I2C3SEL == STM32_I2C3SEL_HSI16) -#error "HSI16 not enabled, required by I2C3SEL" -#endif - -#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16) -#error "HSI16 not enabled, required by LPTIM1SEL" -#endif -#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16) -#error "HSI16 not enabled, required by LPTIM2SEL" -#endif - -#if (STM32_RFCSSSEL == STM32_RFCSSSEL_HSI16) -#error "HSI16 not enabled, required by RFCSS" -#endif - -#endif /* !STM32_HSI16_ENABLED */ - -#if STM32_HSI48_ENABLED -#else /* !STM32_HSI48_ENABLED */ - -#if STM32_MCOSEL == STM32_MCOSEL_HSI48 -#error "HSI48 not enabled, required by STM32_MCOSEL" -#endif - -#if STM32_CLK48SEL == STM32_CLK48SEL_HSI48 -#error "HSI48 not enabled, required by STM32_CLK48SEL" -#endif -#endif /* !STM32_HSI48_ENABLED */ - -/* - * HSE related checks. - */ -#if STM32_HSE32_ENABLED - - #if STM32_HSE32CLK == 0 - #error "HSE frequency not defined" - #else /* STM32_HSE32CLK != 0 */ - #if STM32_HSE32CLK != 32000000 - #error "STM32_HSE32CLK is not 32 Mhz" - #endif - #endif /* STM32_HSE32CLK != 0 */ - - #else /* !STM32_HSE32_ENABLED */ - - #if STM32_SW == STM32_SW_HSE - #error "HSE not enabled, required by STM32_SW" - #endif - - #if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) - #error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" - #endif - - #if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ - ((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSE)) - #error "HSE not enabled, required by STM32_MCOSEL" - #endif - - #if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1PCLK) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSE) - #error "HSE not enabled, required by STM32_SAI1SEL" - #endif - - #if STM32_RTCSEL == STM32_RTCSEL_HSEDIV - #error "HSE not enabled, required by STM32_RTCSEL" - #endif - - #if (STM32_RFCSSSEL == STM32_RFCSSSEL_HSE) - #error "HSE not enabled, required by RFCSS" - #endif - -#endif /* !STM32_HSE32_ENABLED */ - -/* - * LSI related checks. - */ -#if !(STM32_LSI1_ENABLED || STM32_LSI2_ENABLED) - - #if STM32_RTCSEL == STM32_RTCSEL_LSI - #error "LSI1 or LSI2 not enabled, required by STM32_RTCSEL" - #endif - - #if STM32_LSCOSEL == STM32_LSCOSEL_LSI - #error "LSI1 or LSI2 not enabled, required by STM32_LSCOSEL" - #endif - - #if STM32_RNGSEL == STM32_RNGSEL_LSI - #error "LSI1 or LSI2 not enabled, required by STM32_RNGSEL" - #endif - -#endif /* !(STM32_LSI1_ENABLED || STM32_LSI2_ENABLED) */ - -#if !STM32_LSI1_ENABLED - #if STM32_MCOSEL == STM32_MCOSEL_LSI1 - #error "LSI1 not enabled, required by STM32_MCOSEL" - #endif -#endif - -#if !STM32_LSI2_ENABLED - #if STM32_MCOSEL == STM32_MCOSEL_LSI2 - #error "LSI2 not enabled, required by STM32_MCOSEL" - #endif -#endif - -/* - * LSE related checks. - */ -#if STM32_LSE_ENABLED - - #if (STM32_LSECLK == 0) - #error "LSE frequency not defined" - #endif - - #if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) - #error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" - #endif - -#else /* !STM32_LSE_ENABLED */ - - #if STM32_RTCSEL == STM32_RTCSEL_LSE - #error "LSE not enabled, required by STM32_RTCSEL" - #endif - - #if STM32_MCOSEL == STM32_MCOSEL_LSE - #error "LSE not enabled, required by STM32_MCOSEL" - #endif - - #if STM32_LSCOSEL == STM32_LSCOSEL_LSE - #error "LSE not enabled, required by STM32_LSCOSEL" - #endif - - #if STM32_RNGSEL == STM32_RNGSEL_LSE - #error "LSE not enabled, required by STM32_RNGSEL" - #endif - - #if STM32_MSIPLL_ENABLED == TRUE - #error "LSE not enabled, required by STM32_MSIPLL_ENABLED" - #endif - -#endif /* !STM32_LSE_ENABLED */ - -/* - * MSI related checks. - */ -#if (STM32_MSIRANGE == STM32_MSIRANGE_48M) && !STM32_MSIPLL_ENABLED -#warning "STM32_MSIRANGE_48M should be used with STM32_MSIPLL_ENABLED" -#endif - -/** - * @brief PLLs input clock frequency. - */ -#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) -#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE) - -#elif STM32_PLLSRC == STM32_PLLSRC_MSI -#define STM32_PLLCLKIN (STM32_MSICLK / STM32_PLLM_VALUE) - -#elif STM32_PLLSRC == STM32_PLLSRC_HSI16 -#define STM32_PLLCLKIN (STM32_HSI16CLK / STM32_PLLM_VALUE) - -#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK -#define STM32_PLLCLKIN 0 - -#else -#error "invalid STM32_PLLSRC value specified" -#endif - -/* - * PLLs input frequency range check. - */ -#if (STM32_PLLCLKIN != 0) && \ - ((STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)) -#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" -#endif - -/* - * PLLSAI1 enable check. - */ -#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1PCLK) || \ - (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1QCLK) || \ - (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1RCLK) || \ - defined(__DOXYGEN__) -/** - * @brief PLLSAI1 activation flag. - */ -#define STM32_ACTIVATE_PLLSAI1 TRUE -#else -#define STM32_ACTIVATE_PLLSAI1 FALSE -#endif - -/* - * PLL enable check. - */ -#if (STM32_HSI48_ENABLED && (STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK)) || \ - (STM32_SW == STM32_SW_PLL) || \ - (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \ - (STM32_SAI1SEL == STM32_SAI1SEL_PLLPCLK) || \ - (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \ - (STM32_ACTIVATE_PLLSAI1) || \ - defined(__DOXYGEN__) - -#if STM32_PLLCLKIN == 0 -#error "PLL activation required but no PLL clock selected" -#endif - -/** - * @brief PLL activation flag. - */ -#define STM32_ACTIVATE_PLL TRUE -#else -#define STM32_ACTIVATE_PLL FALSE -#endif - - -/** - * @brief STM32_PLLPEN field. - */ -#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLPCLK) || \ - (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \ - defined(__DOXYGEN__) -#define STM32_PLLPEN (1 << 16) -#else -#define STM32_PLLPEN (0 << 16) -#endif - -/** - * @brief STM32_PLLQEN field. - */ -#if (STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK) || defined(__DOXYGEN__) -#define STM32_PLLQEN (1 << 24) -#else -#define STM32_PLLQEN (0 << 24) -#endif - -/** - * @brief STM32_PLLREN field. - */ -#if (STM32_SW == STM32_SW_PLL) || \ - (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \ - defined(__DOXYGEN__) -#define STM32_PLLREN (1 << 28) -#else -#define STM32_PLLREN (0 << 28) -#endif - -/* Inclusion of PLL-related checks and calculations.*/ -#include "stm32_pll_v2.inc" - -/** - * @brief System clock source. - */ -#if STM32_NO_INIT || defined(__DOXYGEN__) -#define STM32_SYSCLK STM32_MSICLK - -#elif (STM32_SW == STM32_SW_MSI) -#define STM32_SYSCLK STM32_MSICLK - -#elif (STM32_SW == STM32_SW_HSI16) -#define STM32_SYSCLK STM32_HSI16CLK - -#elif (STM32_SW == STM32_SW_HSE) -#define STM32_SYSCLK STM32_HSECLK - -#elif (STM32_SW == STM32_SW_PLL) -#define STM32_SYSCLK STM32_PLL_R_CLKOUT - -#else -#error "invalid STM32_SW value specified" -#endif - -/* Bus handlers.*/ -#include "stm32_ahb.inc" -#include "stm32_apb1.inc" -#include "stm32_apb2.inc" - -/** - * @brief HCLK2 (CPU2) frequency. - */ -#if (STM32_C2HPRE == STM32_C2HPRE_DIV1) || defined(__DOXYGEN__) -#define STM32_HCLK2 (STM32_SYSCLK / 1) - -#elif STM32_C2HPRE == STM32_C2HPRE_DIV2 -#define STM32_HCLK2 (STM32_SYSCLK / 2) - -#elif STM32_C2HPRE == STM32_C2HPRE_DIV3 -#define STM32_HCLK2 (STM32_SYSCLK / 3) - -#elif STM32_C2HPRE == STM32_C2HPRE_DIV4 -#define STM32_HCLK2 (STM32_SYSCLK / 4) - -#elif STM32_C2HPRE == STM32_C2HPRE_DIV5 -#define STM32_HCLK2 (STM32_SYSCLK / 5) - -#elif STM32_C2HPRE == STM32_C2HPRE_DIV6 -#define STM32_HCLK2 (STM32_SYSCLK / 6) - -#elif STM32_C2HPRE == STM32_C2HPRE_DIV8 -#define STM32_HCLK2 (STM32_SYSCLK / 8) - -#elif STM32_C2HPRE == STM32_C2HPRE_DIV10 -#define STM32_HCLK2 (STM32_SYSCLK / 10) - -#elif STM32_C2HPRE == STM32_C2HPRE_DIV16 -#define STM32_HCLK2 (STM32_SYSCLK / 16) - -#elif STM32_C2HPRE == STM32_C2HPRE_DIV32 -#define STM32_HCLK2 (STM32_SYSCLK / 32) - -#elif STM32_C2HPRE == STM32_C2HPRE_DIV64 -#define STM32_HCLK2 (STM32_SYSCLK / 64) - -#elif STM32_C2HPRE == STM32_C2HPRE_DIV128 -#define STM32_HCLK2 (STM32_SYSCLK / 128) - -#elif STM32_C2HPRE == STM32_C2HPRE_DIV256 -#define STM32_HCLK2 (STM32_SYSCLK / 256) - -#elif STM32_C2HPRE == STM32_C2HPRE_DIV512 -#define STM32_HCLK2 (STM32_SYSCLK / 512) - -#else -#error "invalid STM32_C2HPRE value specified" -#endif - -/* - * HCLK2 (CPU2) frequency check. - */ -#if STM32_HCLK2 > STM32_C2HPRE_MAX -#error "STM32_HCLK2 exceeding maximum frequency (STM32_C2HPRE_MAX)" -#endif - -/** - * @brief AHB4 frequency. - */ -#if (STM32_SHDHPRE == STM32_SHDHPRE_DIV1) || defined(__DOXYGEN__) -#define STM32_HCLK4 (STM32_SYSCLK / 1) - -#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV2 -#define STM32_HCLK4 (STM32_SYSCLK / 2) - -#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV3 -#define STM32_HCLK4 (STM32_SYSCLK / 3) - -#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV4 -#define STM32_HCLK4 (STM32_SYSCLK / 4) - -#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV5 -#define STM32_HCLK4 (STM32_SYSCLK / 5) - -#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV6 -#define STM32_HCLK4 (STM32_SYSCLK / 6) - -#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV8 -#define STM32_HCLK4 (STM32_SYSCLK / 8) - -#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV10 -#define STM32_HCLK4 (STM32_SYSCLK / 10) - -#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV16 -#define STM32_HCLK4 (STM32_SYSCLK / 16) - -#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV32 -#define STM32_HCLK4 (STM32_SYSCLK / 32) - -#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV64 -#define STM32_HCLK4 (STM32_SYSCLK / 64) - -#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV128 -#define STM32_HCLK4 (STM32_SYSCLK / 128) - -#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV256 -#define STM32_HCLK4 (STM32_SYSCLK / 256) - -#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV512 -#define STM32_HCLK4 (STM32_SYSCLK / 512) - -#else -#error "invalid STM32_SHDHPRE value specified" -#endif - -/** - * @brief STM32_PLLSAI1PEN field. - */ -#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1PCLK) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAI1PEN (1 << 16) -#else -#define STM32_PLLSAI1PEN (0 << 16) -#endif - -/** - * @brief STM32_PLLSAI1QEN field. - */ -#if (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1QCLK) || defined(__DOXYGEN__) -#define STM32_PLLSAI1QEN (1 << 24) -#else -#define STM32_PLLSAI1QEN (0 << 24) -#endif - -/** - * @brief STM32_PLLSAI1REN field. - */ -#if (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1RCLK) || defined(__DOXYGEN__) -#define STM32_PLLSAI1REN (1 << 28) -#else -#define STM32_PLLSAI1REN (0 << 28) -#endif - -/* Inclusion of PLLSAI-related checks and calculations, all PLLs share the - same clock source so enforcing this condition.*/ -#define STM32_PLLSAI1CLKIN STM32_PLLCLKIN -#include "stm32_pllsai1_v2.inc" - -/** - * @brief MCO divider clock frequency. - */ -#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__) -#define STM32_MCODIVCLK 0 - -#elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK -#define STM32_MCODIVCLK STM32_SYSCLK - -#elif STM32_MCOSEL == STM32_MCOSEL_MSI -#define STM32_MCODIVCLK STM32_MSICLK - -#elif STM32_MCOSEL == STM32_MCOSEL_HSI16 -#define STM32_MCODIVCLK STM32_HSI16CLK - -#elif STM32_MCOSEL == STM32_MCOSEL_HSE -#define STM32_MCODIVCLK STM32_HSE32CLK - -#elif STM32_MCOSEL == STM32_MCOSEL_PLLRCLK -#define STM32_MCODIVCLK STM32_PLL_P_CLKOUT - -#elif (STM32_MCOSEL == STM32_MCOSEL_LSI1 || STM32_MCOSEL == STM32_MCOSEL_LSI2) -#define STM32_MCODIVCLK STM32_LSICLK - -#elif STM32_MCOSEL == STM32_MCOSEL_LSE -#define STM32_MCODIVCLK STM32_LSECLK - -#elif STM32_MCOSEL == STM32_MCOSEL_HSI48 -#define STM32_MCODIVCLK STM32_HSI48CLK - -#else -#error "invalid STM32_MCOSEL value specified" -#endif - -/** - * @brief MCO output pin clock frequency. - */ -#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__) -#define STM32_MCOCLK STM32_MCODIVCLK - -#elif STM32_MCOPRE == STM32_MCOPRE_DIV2 -#define STM32_MCOCLK (STM32_MCODIVCLK / 2) - -#elif STM32_MCOPRE == STM32_MCOPRE_DIV4 -#define STM32_MCOCLK (STM32_MCODIVCLK / 4) - -#elif STM32_MCOPRE == STM32_MCOPRE_DIV8 -#define STM32_MCOCLK (STM32_MCODIVCLK / 8) - -#elif STM32_MCOPRE == STM32_MCOPRE_DIV16 -#define STM32_MCOCLK (STM32_MCODIVCLK / 16) - -#else -#error "invalid STM32_MCOPRE value specified" -#endif - -/** - * @brief RTC clock frequency. - */ -#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__) -#define STM32_RTCCLK 0 - -#elif STM32_RTCSEL == STM32_RTCSEL_LSE -#define STM32_RTCCLK STM32_LSECLK - -#elif STM32_RTCSEL == STM32_RTCSEL_LSI -#define STM32_RTCCLK STM32_LSICLK - -#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV -#define STM32_RTCCLK (STM32_HSE32CLK / 32) - -#else -#error "invalid STM32_RTCSEL value specified" -#endif - -/** - * @brief USART1 clock frequency. - */ -#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__) -#define STM32_USART1CLK STM32_PCLK2 -#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK -#define STM32_USART1CLK STM32_SYSCLK -#elif STM32_USART1SEL == STM32_USART1SEL_HSI16 -#define STM32_USART1CLK STM32_HSI16CLK -#elif STM32_USART1SEL == STM32_USART1SEL_LSE -#define STM32_USART1CLK STM32_LSECLK -#else -#error "invalid source selected for USART1 clock" -#endif - -/** - * @brief LPUART1 clock frequency. - */ -#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_LPUART1CLK STM32_PCLK1 -#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK -#define STM32_LPUART1CLK STM32_SYSCLK -#elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16 -#define STM32_LPUART1CLK STM32_HSI16CLK -#elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE -#define STM32_LPUART1CLK STM32_LSECLK -#else -#error "invalid source selected for LPUART1 clock" -#endif - -/** - * @brief I2C1 clock frequency. - */ -#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_I2C1CLK STM32_PCLK1 -#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK -#define STM32_I2C1CLK STM32_SYSCLK -#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI16 -#define STM32_I2C1CLK STM32_HSI16CLK -#else -#error "invalid source selected for I2C1 clock" -#endif - -/** - * @brief I2C3 clock frequency. - */ -#if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_I2C3CLK STM32_PCLK1 -#elif STM32_I2C3SEL == STM32_I2C3SEL_SYSCLK -#define STM32_I2C3CLK STM32_SYSCLK -#elif STM32_I2C3SEL == STM32_I2C3SEL_HSI16 -#define STM32_I2C3CLK STM32_HSI16CLK -#else -#error "invalid source selected for I2C3 clock" -#endif - -/** - * @brief LPTIM1 clock frequency. - */ -#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_LPTIM1CLK STM32_PCLK1 -#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI -#define STM32_LPTIM1CLK STM32_LSICLK -#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16 -#define STM32_LPTIM1CLK STM32_HSI16CLK -#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE -#define STM32_LPTIM1CLK STM32_LSECLK -#else -#error "invalid source selected for LPTIM1 clock" -#endif - -/** - * @brief LPTIM2 clock frequency. - */ -#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_LPTIM2CLK STM32_PCLK1 -#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSI -#define STM32_LPTIM2CLK STM32_LSICLK -#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16 -#define STM32_LPTIM2CLK STM32_HSI16CLK -#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSE -#define STM32_LPTIM2CLK STM32_LSECLK -#else -#error "invalid source selected for LPTIM2 clock" -#endif - -/** - * @brief 48MHz clock frequency. - */ -#if (STM32_CLK48SEL == STM32_CLK48SEL_HSI48) || defined(__DOXYGEN__) -#define STM32_48CLK STM32_HSI48CLK -#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1QCLK -#define STM32_48CLK (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE) -#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK -#define STM32_48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE) -#elif STM32_CLK48SEL == STM32_CLK48SEL_MSI -#define STM32_48CLK STM32_MSICLK -#else -#error "invalid source selected for 48CLK clock" -#endif - -/** - * @brief SAI1 clock frequency. - */ -#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1PCLK) || defined(__DOXYGEN__) -#define STM32_SAI1CLK STM32_PLLSAI1_P_CLKOUT -#elif STM32_SAI1SEL == STM32_SAI1SEL_PLLPCLK -#define STM32_SAI1CLK STM32_PLL_P_CLKOUT -#elif STM32_SAI1SEL == STM32_SAI1SEL_EXTCLK -#define STM32_SAI1CLK 0 /* Unknown, would require a board value */ -#elif STM32_SAI1SEL == STM32_SAI1SEL_OFF -#define STM32_SAI1CLK 0 -#else -#error "invalid source selected for SAI1 clock" -#endif - -/** - * @brief USB clock point. - */ -#define STM32_USBCLK STM32_48CLK - -/** - * @brief RNG clock frequency. - */ -#if (STM32_RNGSEL == STM32_RNGSEL_48CLK) || defined(__DOXYGEN__) -#define STM32_RNGCLK STM32_48CLK -#elif STM32_RNGSEL == STM32_RNGSEL_LSI -#define STM32_RNGCLK STM32_LSICLK -#elif STM32_RNGSEL == STM32_RNGSEL_LSE -#define STM32_RNGCLK STM32_LSECLK -#else -#error "invalid source selected for RNG clock" -#endif - -/** - * @brief ADC clock frequency. - */ -#if (STM32_ADCSEL == STM32_ADCSEL_NOCLK) || defined(__DOXYGEN__) -#define STM32_ADCCLK 0 -#elif STM32_ADCSEL == STM32_ADCSEL_PLLSAI1RCLK -#define STM32_ADCCLK STM32_PLLSAI1_R_CLKOUT -#elif STM32_ADCSEL == STM32_ADCSEL_PLLPCLK -#define STM32_ADCCLK STM32_PLL_P_CLKOUT -#elif STM32_ADCSEL == STM32_ADCSEL_SYSCLK -#define STM32_ADCCLK STM32_SYSCLK -#else -#error "invalid source selected for ADC clock" -#endif - -/** - * @brief SDMMC frequency. - */ -#define STM32_SDMMC1CLK STM32_48CLK - -/** - * @brief Clock of timers connected to APB1 - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK1 (STM32_PCLK1 * 1) -#else -#define STM32_TIMCLK1 (STM32_PCLK1 * 2) -#endif - -/** - * @brief Clock of timers connected to APB2. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK2 (STM32_PCLK2 * 1) -#else -#define STM32_TIMCLK2 (STM32_PCLK2 * 2) -#endif - -/** - * @brief Flash settings. - */ -#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__) -#define STM32_FLASHBITS FLASH_ACR_LATENCY_0WS - -#elif STM32_HCLK <= STM32_1WS_THRESHOLD -#define STM32_FLASHBITS FLASH_ACR_LATENCY_1WS - -#elif STM32_HCLK <= STM32_2WS_THRESHOLD -#define STM32_FLASHBITS FLASH_ACR_LATENCY_2WS - -#else -#define STM32_FLASHBITS FLASH_ACR_LATENCY_3WS -#endif - -/** - * @brief Flash settings for MSI. - */ -#if (STM32_MSICLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__) -#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_0WS - -#elif STM32_MSICLK <= STM32_1WS_THRESHOLD -#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_1WS - -#elif STM32_MSICLK <= STM32_2WS_THRESHOLD -#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_2WS - -#else -#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_3WS -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* Various helpers.*/ -#include "nvic.h" -#include "cache.h" -#include "mpu_v7m.h" -#include "stm32_isr.h" -#include "stm32_dma.h" -#include "stm32_exti.h" -#include "stm32_rcc.h" -#include "stm32_tim.h" - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void stm32_clock_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_LLD_H */ - -/** @} */ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Ilya Kharin. +*/ + +/** + * @file STM32WBxx/hal_lld.h + * @brief STM32WBxx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - STM32_LSECLK. + * - STM32_LSEDRV. + * - STM32_LSE_BYPASS (optionally). + * - STM32_HSE32CLK. + * . + * One of the following macros must also be defined: + * - STM32WB55xx. + * - STM32WB50xx. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef HAL_LLD_H +#define HAL_LLD_H + +#include "stm32_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Platform identification + * @{ + */ +#if defined(STM32WB55xx) || defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32WBxx Ultra Low Power" + +#elif defined(STM32WB50xx) +#define PLATFORM_NAME "STM32WBxx Ultra Low Power Value Line" + +#else +#error "STM32WBxx device not specified" +#endif + +/** + * @brief Sub-family identifier. + */ +#if !defined(STM32WBXX) || defined(__DOXYGEN__) +#define STM32WBXX +#endif +/** @} */ + +/** + * @name PWR_CR1 register bits definitions + * @{ + */ +#define STM32_VOS_MASK (3 << 9) /**< Core voltage mask. */ +#define STM32_VOS_RANGE1 (1 << 9) /**< Core voltage 1.2 Volts. */ +#define STM32_VOS_RANGE2 (2 << 9) /**< Core voltage 1.0 Volts. */ +/** @} */ + +/** + * @name PWR_CR2 register bits definitions + * @{ + */ +#define STM32_PLS_MASK (7 << 1) /**< PLS bits mask. */ +#define STM32_PLS_LEV0 (0 << 1) /**< PVD level 0. */ +#define STM32_PLS_LEV1 (1 << 1) /**< PVD level 1. */ +#define STM32_PLS_LEV2 (2 << 1) /**< PVD level 2. */ +#define STM32_PLS_LEV3 (3 << 1) /**< PVD level 3. */ +#define STM32_PLS_LEV4 (4 << 1) /**< PVD level 4. */ +#define STM32_PLS_LEV5 (5 << 1) /**< PVD level 5. */ +#define STM32_PLS_LEV6 (6 << 1) /**< PVD level 6. */ +#define STM32_PLS_EXT (7 << 1) /**< PVD level 7. */ +/** @} */ + +/** + * @brief HSE SYSCLK and PLL M divider prescaler. + */ +#define STM32_HSE32PRE_MASK (1 << 20) /**< HSEPRE mask. */ +#define STM32_HSE32PRE_DIV1 (0 << 20) /**< HSE divided by 1. */ +#define STM32_HSE32PRE_DIV2 (1 << 20) /**< HSE divided by 2. */ +/** @} */ + +/** + * @name RCC_CFGR register bits definitions + * @{ + */ +#define STM32_SW_MASK (3 << 0) /**< SW field mask. */ +#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */ +#define STM32_SW_HSI16 (1 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */ + +/* STM32WB CMSIS headers don't have these macros */ +#if !defined(RCC_CFGR_SW_MSI) +#define RCC_CFGR_SW_MSI (0x0U << RCC_CFGR_SW_Pos) +#endif +#if !defined(RCC_CFGR_SW_HSI) +#define RCC_CFGR_SW_HSI (0x1U << RCC_CFGR_SW_Pos) +#endif +#if !defined(RCC_CFGR_SW_HSE) +#define RCC_CFGR_SW_HSE (0x2U << RCC_CFGR_SW_Pos) +#endif +#if !defined(RCC_CFGR_SW_PLL) +#define RCC_CFGR_SW_PLL (0x3U << RCC_CFGR_SW_Pos) +#endif + +#if !defined(RCC_CFGR_SWS_MSI) +#define RCC_CFGR_SWS_MSI (0x0U << RCC_CFGR_SWS_Pos) +#endif +#if !defined(RCC_CFGR_SWS_HSI) +#define RCC_CFGR_SWS_HSI (0x1U << RCC_CFGR_SWS_Pos) +#endif +#if !defined(RCC_CFGR_SWS_HSE) +#define RCC_CFGR_SWS_HSE (0x2U << RCC_CFGR_SWS_Pos) +#endif +#if !defined(RCC_CFGR_SWS_PLL) +#define RCC_CFGR_SWS_PLL (0x3U << RCC_CFGR_SWS_Pos) +#endif + +#define STM32_STOPWUCK_MASK (1 << 15) /**< STOPWUCK field mask. */ +#define STM32_STOPWUCK_MSI (0 << 15) /**< Wakeup clock is MSI. */ +#define STM32_STOPWUCK_HSI16 (1 << 15) /**< Wakeup clock is HSI16. */ + +#define STM32_MCOSEL_MASK (15 << 24) /**< MCOSEL field mask. */ +#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ +#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */ +#define STM32_MCOSEL_MSI (2 << 24) /**< MSI clock on MCO pin. */ +#define STM32_MCOSEL_HSI16 (3 << 24) /**< HSI16 clock on MCO pin. */ +#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. + (after stabilization) */ +#define STM32_MCOSEL_PLLRCLK (5 << 24) /**< PLLR clock on MCO pin. */ +#define STM32_MCOSEL_LSI1 (6 << 24) /**< LSI clock on MCO pin. */ +#define STM32_MCOSEL_LSI2 (7 << 24) /**< LSI clock on MCO pin. */ +#define STM32_MCOSEL_LSE (8 << 24) /**< LSE clock on MCO pin. */ +#define STM32_MCOSEL_HSI48 (9 << 24) /**< HSI48 clock on MCO pin. */ +#define STM32_MCOSEL_HSE2 (4 << 24) /**< HSE clock on MCO pin. + (before stabilization) */ + +#define STM32_MCOPRE_MASK (7 << 28) /**< MCOPRE field mask. */ +#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */ +#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 2. */ +#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 4. */ +#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 8. */ +#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 16. */ +/** @} */ + +/** + * @name RCC_EXTCFGR register bits definitions + * @{ + */ +/** + * @brief HCLK5 clock source (RFC and APB3). + */ +#define STM32_RFCSSSEL_MASK (1 << 20) /**< RFCSS field mask. */ +#define STM32_RFCSSSEL_HSI16 (0 << 20) /**< RFCSS source is HSI16. */ +#define STM32_RFCSSSEL_HSE (1 << 20) /**< RFCSS source is HSE/2. */ + +/** + * @brief HCLK4 shared prescaler (AHB3, Flash memory and SRAM2). + */ +#define STM32_SHDHPRE_MASK (15 << 0) /**< SHDHPRE field mask. */ +#define STM32_SHDHPRE_DIV1 (0 << 0) /**< SYSCLK divided by 1. */ +#define STM32_SHDHPRE_DIV2 (8 << 0) /**< SYSCLK divided by 2. */ +#define STM32_SHDHPRE_DIV3 (1 << 0) /**< SYSCLK divided by 3. */ +#define STM32_SHDHPRE_DIV4 (9 << 0) /**< SYSCLK divided by 4. */ +#define STM32_SHDHPRE_DIV5 (2 << 0) /**< SYSCLK divided by 5. */ +#define STM32_SHDHPRE_DIV6 (5 << 0) /**< SYSCLK divided by 6. */ +#define STM32_SHDHPRE_DIV8 (10 << 0) /**< SYSCLK divided by 8. */ +#define STM32_SHDHPRE_DIV10 (6 << 0) /**< SYSCLK divided by 10. */ +#define STM32_SHDHPRE_DIV16 (11 << 0) /**< SYSCLK divided by 16. */ +#define STM32_SHDHPRE_DIV32 (7 << 0) /**< SYSCLK divided by 32. */ +#define STM32_SHDHPRE_DIV64 (12 << 0) /**< SYSCLK divided by 64. */ +#define STM32_SHDHPRE_DIV128 (13 << 0) /**< SYSCLK divided by 128. */ +#define STM32_SHDHPRE_DIV256 (14 << 0) /**< SYSCLK divided by 256. */ +#define STM32_SHDHPRE_DIV512 (15 << 0) /**< SYSCLK divided by 512. */ + +/** + * @brief HCLK2 prescaler (CPU2). + */ +#define STM32_C2HPRE_MASK (15 << 4) /**< C2HPRE field mask. */ +#define STM32_C2HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_C2HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_C2HPRE_DIV3 (1 << 4) /**< SYSCLK divided by 3. */ +#define STM32_C2HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_C2HPRE_DIV5 (2 << 4) /**< SYSCLK divided by 5. */ +#define STM32_C2HPRE_DIV6 (5 << 4) /**< SYSCLK divided by 6. */ +#define STM32_C2HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_C2HPRE_DIV10 (6 << 4) /**< SYSCLK divided by 10. */ +#define STM32_C2HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_C2HPRE_DIV32 (7 << 4) /**< SYSCLK divided by 32. */ +#define STM32_C2HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_C2HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_C2HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_C2HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +/** + * @brief HCLK5 and APB3 clock source. + */ +#define STM32_RFCSS_MASK (1 << 20) /**< RFCSS field mask. */ +#define STM32_RFCSS_HSI16 (0 << 20) /**< HSI16 on HCLK5 and APB3. */ +#define STM32_RFCSS_HSEDIV2 (1 << 20) /**< HSE/2 on HCLK5 and APB3. */ +/** @} */ + +/** + * @name RCC_PLLCFGR register bits definitions + * @{ + */ +#define STM32_PLLSRC_MASK (3 << 0) /**< PLL clock source mask. */ +#define STM32_PLLSRC_NOCLOCK (0 << 0) /**< PLL clock source disabled. */ +#define STM32_PLLSRC_MSI (1 << 0) /**< PLL clock source is MSI. */ +#define STM32_PLLSRC_HSI16 (2 << 0) /**< PLL clock source is HSI16. */ +#define STM32_PLLSRC_HSE (3 << 0) /**< PLL clock source is HSE. */ +/** @} */ + +/** + * @name RCC_CCIPR register bits definitions + * @{ + */ +#define STM32_USART1SEL_MASK (3 << 0) /**< USART1SEL mask. */ +#define STM32_USART1SEL_PCLK2 (0 << 0) /**< USART1 source is PCLK2. */ +#define STM32_USART1SEL_SYSCLK (1 << 0) /**< USART1 source is SYSCLK. */ +#define STM32_USART1SEL_HSI16 (2 << 0) /**< USART1 source is HSI16. */ +#define STM32_USART1SEL_LSE (3 << 0) /**< USART1 source is LSE. */ + +#define STM32_LPUART1SEL_MASK (3 << 10) /**< LPUART1 mask. */ +#define STM32_LPUART1SEL_PCLK1 (0 << 10) /**< LPUART1 source is PCLK1. */ +#define STM32_LPUART1SEL_SYSCLK (1 << 10) /**< LPUART1 source is SYSCLK. */ +#define STM32_LPUART1SEL_HSI16 (2 << 10) /**< LPUART1 source is HSI16. */ +#define STM32_LPUART1SEL_LSE (3 << 10) /**< LPUART1 source is LSE. */ + +#define STM32_I2C1SEL_MASK (3 << 12) /**< I2C1SEL mask. */ +#define STM32_I2C1SEL_PCLK1 (0 << 12) /**< I2C1 source is PCLK1. */ +#define STM32_I2C1SEL_SYSCLK (1 << 12) /**< I2C1 source is SYSCLK. */ +#define STM32_I2C1SEL_HSI16 (2 << 12) /**< I2C1 source is HSI16. */ + +#define STM32_I2C3SEL_MASK (3 << 16) /**< I2C3SEL mask. */ +#define STM32_I2C3SEL_PCLK1 (0 << 16) /**< I2C3 source is PCLK1. */ +#define STM32_I2C3SEL_SYSCLK (1 << 16) /**< I2C3 source is SYSCLK. */ +#define STM32_I2C3SEL_HSI16 (2 << 16) /**< I2C3 source is HSI16. */ + +#define STM32_LPTIM1SEL_MASK (3 << 18) /**< LPTIM1SEL mask. */ +#define STM32_LPTIM1SEL_PCLK1 (0 << 18) /**< LPTIM1 source is PCLK1. */ +#define STM32_LPTIM1SEL_LSI (1 << 18) /**< LPTIM1 source is LSI. */ +#define STM32_LPTIM1SEL_HSI16 (2 << 18) /**< LPTIM1 source is HSI16. */ +#define STM32_LPTIM1SEL_LSE (3 << 18) /**< LPTIM1 source is LSE. */ + +#define STM32_LPTIM2SEL_MASK (3 << 20) /**< LPTIM2SEL mask. */ +#define STM32_LPTIM2SEL_PCLK1 (0 << 20) /**< LPTIM2 source is PCLK1. */ +#define STM32_LPTIM2SEL_LSI (1 << 20) /**< LPTIM2 source is LSI. */ +#define STM32_LPTIM2SEL_HSI16 (2 << 20) /**< LPTIM2 source is HSI16. */ +#define STM32_LPTIM2SEL_LSE (3 << 20) /**< LPTIM2 source is LSE. */ + +#define STM32_SAI1SEL_MASK (3 << 22) /**< SAI1SEL mask. */ +#define STM32_SAI1SEL_PLLSAI1PCLK (0 << 22) /**< SAI1 source is PLLSAI1PCLK.*/ +#define STM32_SAI1SEL_PLLPCLK (2 << 22) /**< SAI1 source is PLLPCLK. */ +#define STM32_SAI1SEL_EXTCLK (3 << 22) /**< SAI1 source is external. */ +#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/ + +#define STM32_CLK48SEL_MASK (3 << 26) /**< CLK48SEL mask. */ +#define STM32_CLK48SEL_HSI48 (0 << 26) /**< CLK48 source is HSI48. */ +#define STM32_CLK48SEL_PLLSAI1QCLK (1 << 26) /**< CLK48 source is SAI1-Q. */ +#define STM32_CLK48SEL_PLLQCLK (2 << 26) /**< CLK48 source is PLLQCLK. */ +#define STM32_CLK48SEL_MSI (3 << 26) /**< CLK48 source is MSI. */ + +#define STM32_ADCSEL_MASK (3 << 28) /**< ADCSEL mask. */ +#define STM32_ADCSEL_NOCLK (0 << 28) /**< ADC clock disabled. */ +#define STM32_ADCSEL_PLLSAI1RCLK (1 << 28) /**< ADC source is PLLSAI1RCLK. */ +#define STM32_ADCSEL_PLLPCLK (2 << 28) /**< ADC source is PLLPCLK. */ +#define STM32_ADCSEL_SYSCLK (3 << 28) /**< ADC source is SYSCLK. */ + +#define STM32_RNGSEL_MASK (3 << 30) /**< RNGSEL mask. */ +#define STM32_RNGSEL_48CLK (0 << 30) /**< RNG source is CLK48SEL. */ +#define STM32_RNGSEL_LSI (1 << 30) /**< RNG source is LSI. */ +#define STM32_RNGSEL_LSE (3 << 30) /**< RNG source is LSE. */ +/** @} */ + +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */ +#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */ +#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */ +#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */ + +#define STM32_LSCOSEL_MASK (3 << 24) /**< LSCO pin clock source. */ +#define STM32_LSCOSEL_NOCLOCK (0 << 24) /**< No clock on LSCO pin. */ +#define STM32_LSCOSEL_LSI (1 << 24) /**< LSI on LSCO pin. */ +#define STM32_LSCOSEL_LSE (3 << 24) /**< LSE on LSCO pin. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Disables the PWR/RCC initialization in the HAL. + */ +#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) +#define STM32_NO_INIT FALSE +#endif + +/** + * @brief Core voltage selection. + * @note This setting affects all the performance and clock related + * settings, the maximum performance is only obtainable selecting + * the maximum voltage. + */ +#if !defined(STM32_VOS) || defined(__DOXYGEN__) +#define STM32_VOS STM32_VOS_RANGE1 +#endif + +/** + * @brief PWR CR2 register initialization value. + */ +#if !defined(STM32_PWR_CR2) || defined(__DOXYGEN__) +#define STM32_PWR_CR2 (PWR_CR2_PLS_0) +#endif + +/** + * @brief PWR CR3 register initialization value. + */ +#if !defined(STM32_PWR_CR3) || defined(__DOXYGEN__) +#define STM32_PWR_CR3 (PWR_CR3_EIWUL) +#endif + +/** + * @brief PWR CR4 register initialization value. + */ +#if !defined(STM32_PWR_CR4) || defined(__DOXYGEN__) +#define STM32_PWR_CR4 (0U) +#endif + +/** + * @brief PWR PUCRA register initialization value. + */ +#if !defined(STM32_PWR_PUCRA) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRA (0U) +#endif + +/** + * @brief PWR PDCRA register initialization value. + */ +#if !defined(STM32_PWR_PDCRA) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRA (0U) +#endif + +/** + * @brief PWR PUCRB register initialization value. + */ +#if !defined(STM32_PWR_PUCRB) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRB (0U) +#endif + +/** + * @brief PWR PDCRB register initialization value. + */ +#if !defined(STM32_PWR_PDCRB) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRB (0U) +#endif + +/** + * @brief PWR PUCRC register initialization value. + */ +#if !defined(STM32_PWR_PUCRC) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRC (0U) +#endif + +/** + * @brief PWR PDCRC register initialization value. + */ +#if !defined(STM32_PWR_PDCRC) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRC (0U) +#endif + +/** + * @brief PWR PUCRD register initialization value. + */ +#if !defined(STM32_PWR_PUCRD) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRD (0U) +#endif + +/** + * @brief PWR PDCRD register initialization value. + */ +#if !defined(STM32_PWR_PDCRD) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRD (0U) +#endif + +/** + * @brief PWR PUCRE register initialization value. + */ +#if !defined(STM32_PWR_PUCRE) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRE (0U) +#endif + +/** + * @brief PWR PDCRE register initialization value. + */ +#if !defined(STM32_PWR_PDCRE) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRE (0U) +#endif + +/** + * @brief PWR PUCRF register initialization value. + */ +#if !defined(STM32_PWR_PUCRF) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRF (0U) +#endif + +/** + * @brief PWR PDCRF register initialization value. + */ +#if !defined(STM32_PWR_PDCRF) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRF (0U) +#endif + +/** + * @brief PWR PUCRG register initialization value. + */ +#if !defined(STM32_PWR_PUCRG) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRG (0U) +#endif + +/** + * @brief PWR PDCRG register initialization value. + */ +#if !defined(STM32_PWR_PDCRG) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRG (0U) +#endif + +/** + * @brief PWR PUCRH register initialization value. + */ +#if !defined(STM32_PWR_PUCRH) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRH (0U) +#endif + +/** + * @brief PWR PDCRH register initialization value. + */ +#if !defined(STM32_PWR_PDCRH) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRH (0U) +#endif + +/** + * @brief Enables or disables the programmable voltage detector. + */ +#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) +#define STM32_PVD_ENABLE FALSE +#endif + +/** + * @brief Sets voltage level for programmable voltage detector. + */ +#if !defined(STM32_PLS) || defined(__DOXYGEN__) +#define STM32_PLS STM32_PLS_LEV0 +#endif + +/** + * @brief Enables or disables the HSI16 clock source. + */ +#if !defined(STM32_HSI16_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI16_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the HSI48 clock source. + */ +#if !defined(STM32_HSI48_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI48_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM32_LSI1_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSI1_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM32_HSE32_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSE32_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the LSE clock source. + */ +#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSE_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the MSI PLL on LSE clock source. + */ +#if !defined(STM32_MSIPLL_ENABLED) || defined(__DOXYGEN__) +#define STM32_MSIPLL_ENABLED FALSE +#endif + +/** + * @brief MSI frequency setting. + */ +#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__) +#define STM32_MSIRANGE STM32_MSIRANGE_4M +#endif + +/** + * @brief HSE32 prescaler value. + */ +#if !defined(STM32_HSE32PRE) || defined(__DOXYGEN__) +#define STM32_HSE32PRE STM32_HSE32PRE_DIV1 +#endif + +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 32MHz system clock from + * the internal 4MHz MSI clock. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLL. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 32MHz system clock from + * the internal 4MHz MSI clock. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_MSI +#endif + +/** + * @brief PLLM divider value. + * @note The allowed values are 1..8. + * @note The default value is calculated for a 32MHz system clock from + * the internal 4MHz MSI clock. + */ +#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLM_VALUE 1 +#endif + +/** + * @brief PLLN multiplier value. + * @note The allowed values are 8..86. + * @note The default value is calculated for a 32MHz system clock from + * the internal 4MHz MSI clock. + */ +#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLN_VALUE 32 +#endif + +/** + * @brief PLLP divider value. + * @note The allowed values are 2..31. + */ +#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLP_VALUE 2 +#endif + +/** + * @brief PLLQ divider value. + * @note The allowed values are 2, 4, 6, 8. + */ +#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLQ_VALUE 2 +#endif + +/** + * @brief PLLR divider value. + * @note The allowed values are 2, 4, 6, 8. + * @note The default value is calculated for a 32MHz system clock from + * the internal 4MHz MSI clock. + */ +#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLR_VALUE 2 +#endif + +/** + * @brief HCLK1 (CPU1, AHB1, AHB2, AHB3 and SRAM1) prescaler value. + * @note The default value is calculated for a 32MHz system clock from + * the internal 4MHz MSI clock. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#endif + +/** + * @brief HCLK2 (CPU2) prescaler value. + * @note The default value is calculated for a 32MHz system clock from + * the internal 4MHz MSI clock. + */ +#if !defined(STM32_C2HPRE) || defined(__DOXYGEN__) +#define STM32_C2HPRE STM32_C2HPRE_DIV2 +#endif + +/** + * @brief HCLK4 (AHB4, Flash memory and SRAM2) prescaler value. + */ +#if !defined(STM32_SHDHPRE) || defined(__DOXYGEN__) +#define STM32_SHDHPRE STM32_SHDHPRE_DIV1 +#endif + +/** + * @brief HCLK5 (APB3, AHB5 and Radio system) clock source. + */ +#if !defined(STM32_RFCSSSEL) || defined(__DOXYGEN__) +#define STM32_RFCSSSEL STM32_RFCSSSEL_HSI16 +#endif + +/** + * @brief STOPWUCK clock setting. + */ +#if !defined(STM32_STOPWUCK) || defined(__DOXYGEN__) +#define STM32_STOPWUCK STM32_STOPWUCK_MSI +#endif + +/** + * @brief MCO clock source. + */ +#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#endif + +/** + * @brief MCO divider setting. + */ +#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__) +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#endif + +/** + * @brief LSCO clock source. + */ +#if !defined(STM32_LSCOSEL) || defined(__DOXYGEN__) +#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK +#endif + +/** + * @brief PLLSAI1N multiplier value. + * @note The allowed values are 4..86. + */ +#if !defined(STM32_PLLSAI1N_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLSAI1N_VALUE 24 +#endif + +/** + * @brief PLLSAI1P divider value. + * @note The allowed values are 2..32. + */ +#if !defined(STM32_PLLSAI1P_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLSAI1P_VALUE 2 +#endif + +/** + * @brief PLLSAI1Q divider value. + * @note The allowed values are 2..8. + */ +#if !defined(STM32_PLLSAI1Q_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLSAI1Q_VALUE 2 +#endif + +/** + * @brief PLLSAI1R divider value. + * @note The allowed values are 2..8. + */ +#if !defined(STM32_PLLSAI1R_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLSAI1R_VALUE 2 +#endif + +/** + * @brief USART1 clock source. + */ +#if !defined(STM32_USART1SEL) || defined(__DOXYGEN__) +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#endif + +/** + * @brief LPUART1 clock source. + */ +#if !defined(STM32_LPUART1SEL) || defined(__DOXYGEN__) +#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK1 +#endif + +/** + * @brief I2C1 clock source. + */ +#if !defined(STM32_I2C1SEL) || defined(__DOXYGEN__) +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#endif + +/** + * @brief I2C3 clock source. + */ +#if !defined(STM32_I2C3SEL) || defined(__DOXYGEN__) +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#endif + +/** + * @brief LPTIM1 clock source. + */ +#if !defined(STM32_LPTIM1SEL) || defined(__DOXYGEN__) +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#endif + +/** + * @brief LPTIM2 clock source. + */ +#if !defined(STM32_LPTIM2SEL) || defined(__DOXYGEN__) +#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 +#endif + +/** + * @brief SAI1SEL value (SAI1 clock source). + */ +#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__) +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#endif + +/** + * @brief CLK48SEL value (48MHz clock source). + */ +#if !defined(STM32_CLK48SEL) || defined(__DOXYGEN__) +#define STM32_CLK48SEL STM32_CLK48SEL_PLLQCLK +// #define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1QCLK +#endif + +/** + * @brief ADCSEL value (ADCs clock source). + */ +#if !defined(STM32_ADCSEL) || defined(__DOXYGEN__) +#define STM32_ADCSEL STM32_ADCSEL_SYSCLK +#endif + +/** + * @brief RNGSEL value (RNGs clock source). + */ +#if !defined(STM32_RNGSEL) || defined(__DOXYGEN__) +#define STM32_RNGSEL STM32_RNGSEL_48CLK +#endif + +/** + * @brief RTC/LCD clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_LSI +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(STM32WBxx_MCUCONF) +#error "Using a wrong mcuconf.h file, STM32WBxx_MCUCONF not defined" +#endif + +/* + * Board files sanity checks. + */ +#if !defined(STM32_LSECLK) +#error "STM32_LSECLK not defined in board.h" +#endif + +#if !defined(STM32_LSEDRV) +#error "STM32_LSEDRV not defined in board.h" +#endif + +/* Voltage related limits.*/ +#if (STM32_VOS == STM32_VOS_RANGE1) || defined(__DOXYGEN__) +/** + * @name System Limits + * @{ + */ +/** + * @brief Maximum SYSCLK clock frequency at current voltage setting. + */ +#define STM32_SYSCLK_MAX 64000000 + +/** + * @brief Maximum C2HPRE clock frequency at current voltage setting. + */ +#define STM32_C2HPRE_MAX 32000000 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_MAX 32768 + +/** + * @brief Maximum LSE clock frequency using an external source. + */ +#define STM32_LSECLK_BYP_MAX 1000000 + +/** + * @brief Minimum LSE clock frequency. + */ +#define STM32_LSECLK_MIN 32768 + +/** + * @brief Minimum LSE clock frequency using an external source. + */ +#define STM32_LSECLK_BYP_MIN 32768 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLLIN_MAX 16000000 + +/** + * @brief Minimum PLLs input clock frequency. + */ +#define STM32_PLLIN_MIN 2660000 + +/** + * @brief Maximum VCO clock frequency at current voltage setting. + */ +#define STM32_PLLVCO_MAX 344000000 + +/** + * @brief Minimum VCO clock frequency at current voltage setting. + */ +#define STM32_PLLVCO_MIN 96000000 + +/** + * @brief Maximum PLL-P output clock frequency. + */ +#define STM32_PLLP_MAX 64000000 + +/** + * @brief Minimum PLL-P output clock frequency. + */ +#define STM32_PLLP_MIN 2000000 + +/** + * @brief Maximum PLL-Q output clock frequency. + */ +#define STM32_PLLQ_MAX 64000000 + +/** + * @brief Minimum PLL-Q output clock frequency. + */ +#define STM32_PLLQ_MIN 8000000 + +/** + * @brief Maximum PLL-R output clock frequency. + */ +#define STM32_PLLR_MAX 64000000 + +/** + * @brief Minimum PLL-R output clock frequency. + */ +#define STM32_PLLR_MIN 8000000 + +/** + * @brief Maximum VCO clock frequency at current voltage setting. + */ +#define STM32_PLLSAI1VCO_MAX 344000000 + +/** + * @brief Minimum VCO clock frequency at current voltage setting. + */ +#define STM32_PLLSAI1VCO_MIN 64000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX 64000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX 64000000 + +/** + * @brief Maximum ADC clock frequency. + */ +#define STM32_ADCCLK_MAX 64000000 +/** @} */ + +/** + * @name Flash Wait states + * @{ + */ +#define STM32_0WS_THRESHOLD 18000000 +#define STM32_1WS_THRESHOLD 36000000 +#define STM32_2WS_THRESHOLD 54000000 +/** @} */ + +#elif STM32_VOS == STM32_VOS_RANGE2 +#define STM32_SYSCLK_MAX 16000000 +#define STM32_C2HPRE_MAX 16000000 +#define STM32_LSECLK_MAX 32768 +#define STM32_LSECLK_BYP_MAX 1000000 +#define STM32_LSECLK_MIN 32768 +#define STM32_LSECLK_BYP_MIN 32768 +#define STM32_PLLIN_MAX 16000000 +#define STM32_PLLIN_MIN 2660000 +#define STM32_PLLVCO_MAX 128000000 +#define STM32_PLLVCO_MIN 64000000 +#define STM32_PLLSAI1VCO_MAX 128000000 +#define STM32_PLLSAI1VCO_MIN 64000000 +#define STM32_PLLP_MAX 16000000 +#define STM32_PLLP_MIN 2000000 +#define STM32_PLLQ_MAX 16000000 +#define STM32_PLLQ_MIN 8000000 +#define STM32_PLLR_MAX 16000000 +#define STM32_PLLR_MIN 8000000 +#define STM32_PCLK1_MAX 26000000 +#define STM32_PCLK2_MAX 26000000 +#define STM32_ADCCLK_MAX 26000000 + +#define STM32_0WS_THRESHOLD 6000000 +#define STM32_1WS_THRESHOLD 12000000 +#define STM32_2WS_THRESHOLD 16000000 + +#else +#error "invalid STM32_VOS value specified" +#endif + +/** + * @name PLL dividers limits + * @{ + */ +#define STM32_PLLM_VALUE_MAX 8 +#define STM32_PLLM_VALUE_MIN 1 +#define STM32_PLLN_VALUE_MAX 127 +#define STM32_PLLN_VALUE_MIN 6 +#define STM32_PLLR_VALUE_MAX 8 +#define STM32_PLLR_VALUE_MIN 2 +#define STM32_PLLQ_VALUE_MAX 8 +#define STM32_PLLQ_VALUE_MIN 2 +#define STM32_PLLP_VALUE_MAX 32 +#define STM32_PLLP_VALUE_MIN 2 +/** @} */ + +/** + * @name PLLSAI1 dividers limits + * @{ + */ +#define STM32_PLLSAI1N_VALUE_MAX 86 +#define STM32_PLLSAI1N_VALUE_MIN 4 +#define STM32_PLLSAI1R_VALUE_MAX 8 +#define STM32_PLLSAI1R_VALUE_MIN 2 +#define STM32_PLLSAI1Q_VALUE_MAX 8 +#define STM32_PLLSAI1Q_VALUE_MIN 2 +#define STM32_PLLSAI1P_VALUE_MAX 32 +#define STM32_PLLSAI1P_VALUE_MIN 2 +/** @} */ + +/* Clock handlers.*/ +#include "stm32_bd.inc" +#include "stm32_lse.inc" +#include "stm32_lsi_v2.inc" +#include "stm32_msi_v2.inc" +#include "stm32_hsi16.inc" +#include "stm32_hsi48.inc" +#include "stm32_hse32.inc" + +/* + * HSI16 related checks. + */ +#if STM32_HSI16_ENABLED +#else /* !STM32_HSI16_ENABLED */ + +#if STM32_SW == STM32_SW_HSI16 +#error "HSI16 not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI16) +#error "HSI16 not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSI16) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI16)) +#error "HSI16 not enabled, required by STM32_MCOSEL" +#endif + +#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1PCLK) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI16) +#error "HSI16 not enabled, required by STM32_SAI1SEL" +#endif + +#if (STM32_USART1SEL == STM32_USART1SEL_HSI16) +#error "HSI16 not enabled, required by STM32_USART1SEL" +#endif +#if (STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16) +#error "HSI16 not enabled, required by STM32_LPUART1SEL" +#endif + +#if (STM32_I2C1SEL == STM32_I2C1SEL_HSI16) +#error "HSI16 not enabled, required by I2C1SEL" +#endif +#if (STM32_I2C3SEL == STM32_I2C3SEL_HSI16) +#error "HSI16 not enabled, required by I2C3SEL" +#endif + +#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16) +#error "HSI16 not enabled, required by LPTIM1SEL" +#endif +#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16) +#error "HSI16 not enabled, required by LPTIM2SEL" +#endif + +#if (STM32_RFCSSSEL == STM32_RFCSSSEL_HSI16) +#error "HSI16 not enabled, required by RFCSS" +#endif + +#endif /* !STM32_HSI16_ENABLED */ + +#if STM32_HSI48_ENABLED +#else /* !STM32_HSI48_ENABLED */ + +#if STM32_MCOSEL == STM32_MCOSEL_HSI48 +#error "HSI48 not enabled, required by STM32_MCOSEL" +#endif + +#if STM32_CLK48SEL == STM32_CLK48SEL_HSI48 +#error "HSI48 not enabled, required by STM32_CLK48SEL" +#endif +#endif /* !STM32_HSI48_ENABLED */ + +/* + * HSE related checks. + */ +#if STM32_HSE32_ENABLED + + #if STM32_HSE32CLK == 0 + #error "HSE frequency not defined" + #else /* STM32_HSE32CLK != 0 */ + #if STM32_HSE32CLK != 32000000 + #error "STM32_HSE32CLK is not 32 Mhz" + #endif + #endif /* STM32_HSE32CLK != 0 */ + + #else /* !STM32_HSE32_ENABLED */ + + #if STM32_SW == STM32_SW_HSE + #error "HSE not enabled, required by STM32_SW" + #endif + + #if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) + #error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" + #endif + + #if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) + #error "HSE not enabled, required by STM32_MCOSEL" + #endif + + #if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1PCLK) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE) + #error "HSE not enabled, required by STM32_SAI1SEL" + #endif + + #if STM32_RTCSEL == STM32_RTCSEL_HSEDIV + #error "HSE not enabled, required by STM32_RTCSEL" + #endif + + #if (STM32_RFCSSSEL == STM32_RFCSSSEL_HSE) + #error "HSE not enabled, required by RFCSS" + #endif + +#endif /* !STM32_HSE32_ENABLED */ + +/* + * LSI related checks. + */ +#if !(STM32_LSI1_ENABLED || STM32_LSI2_ENABLED) + + #if STM32_RTCSEL == STM32_RTCSEL_LSI + #error "LSI1 or LSI2 not enabled, required by STM32_RTCSEL" + #endif + + #if STM32_LSCOSEL == STM32_LSCOSEL_LSI + #error "LSI1 or LSI2 not enabled, required by STM32_LSCOSEL" + #endif + + #if STM32_RNGSEL == STM32_RNGSEL_LSI + #error "LSI1 or LSI2 not enabled, required by STM32_RNGSEL" + #endif + +#endif /* !(STM32_LSI1_ENABLED || STM32_LSI2_ENABLED) */ + +#if !STM32_LSI1_ENABLED + #if STM32_MCOSEL == STM32_MCOSEL_LSI1 + #error "LSI1 not enabled, required by STM32_MCOSEL" + #endif +#endif + +#if !STM32_LSI2_ENABLED + #if STM32_MCOSEL == STM32_MCOSEL_LSI2 + #error "LSI2 not enabled, required by STM32_MCOSEL" + #endif +#endif + +/* + * LSE related checks. + */ +#if STM32_LSE_ENABLED + + #if (STM32_LSECLK == 0) + #error "LSE frequency not defined" + #endif + + #if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) + #error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" + #endif + +#else /* !STM32_LSE_ENABLED */ + + #if STM32_RTCSEL == STM32_RTCSEL_LSE + #error "LSE not enabled, required by STM32_RTCSEL" + #endif + + #if STM32_MCOSEL == STM32_MCOSEL_LSE + #error "LSE not enabled, required by STM32_MCOSEL" + #endif + + #if STM32_LSCOSEL == STM32_LSCOSEL_LSE + #error "LSE not enabled, required by STM32_LSCOSEL" + #endif + + #if STM32_RNGSEL == STM32_RNGSEL_LSE + #error "LSE not enabled, required by STM32_RNGSEL" + #endif + + #if STM32_MSIPLL_ENABLED == TRUE + #error "LSE not enabled, required by STM32_MSIPLL_ENABLED" + #endif + +#endif /* !STM32_LSE_ENABLED */ + +/* + * MSI related checks. + */ +#if (STM32_MSIRANGE == STM32_MSIRANGE_48M) && !STM32_MSIPLL_ENABLED +#warning "STM32_MSIRANGE_48M should be used with STM32_MSIPLL_ENABLED" +#endif + +/** + * @brief PLLs input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE) + +#elif STM32_PLLSRC == STM32_PLLSRC_MSI +#define STM32_PLLCLKIN (STM32_MSICLK / STM32_PLLM_VALUE) + +#elif STM32_PLLSRC == STM32_PLLSRC_HSI16 +#define STM32_PLLCLKIN (STM32_HSI16CLK / STM32_PLLM_VALUE) + +#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK +#define STM32_PLLCLKIN 0 + +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* + * PLLs input frequency range check. + */ +#if (STM32_PLLCLKIN != 0) && \ + ((STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" +#endif + +/* + * PLLSAI1 enable check. + */ +#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1PCLK) || \ + (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1QCLK) || \ + (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1RCLK) || \ + defined(__DOXYGEN__) +/** + * @brief PLLSAI1 activation flag. + */ +#define STM32_ACTIVATE_PLLSAI1 TRUE +#else +#define STM32_ACTIVATE_PLLSAI1 FALSE +#endif + +/* + * PLL enable check. + */ +#if (STM32_HSI48_ENABLED && (STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK)) || \ + (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \ + (STM32_SAI1SEL == STM32_SAI1SEL_PLLPCLK) || \ + (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \ + (STM32_ACTIVATE_PLLSAI1) || \ + defined(__DOXYGEN__) + +#if STM32_PLLCLKIN == 0 +#error "PLL activation required but no PLL clock selected" +#endif + +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLL TRUE +#else +#define STM32_ACTIVATE_PLL FALSE +#endif + +/** + * @brief STM32_PLLPEN field. + */ +#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLPCLK) || \ + (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \ + defined(__DOXYGEN__) +#define STM32_PLLPEN (1 << 16) +#else +#define STM32_PLLPEN (0 << 16) +#endif + +/** + * @brief STM32_PLLQEN field. + */ +#if (STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK) || defined(__DOXYGEN__) +#define STM32_PLLQEN (1 << 24) +#else +#define STM32_PLLQEN (0 << 24) +#endif + +/** + * @brief STM32_PLLREN field. + */ +#if (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \ + defined(__DOXYGEN__) +#define STM32_PLLREN (1 << 28) +#else +#define STM32_PLLREN (0 << 28) +#endif + +/* Inclusion of PLL-related checks and calculations.*/ +#include "stm32_pll_v2.inc" + +/** + * @brief System clock source. + */ +#if STM32_NO_INIT || defined(__DOXYGEN__) +#define STM32_SYSCLK STM32_MSICLK + +#elif (STM32_SW == STM32_SW_MSI) +#define STM32_SYSCLK STM32_MSICLK + +#elif (STM32_SW == STM32_SW_HSI16) +#define STM32_SYSCLK STM32_HSI16CLK + +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK + +#elif (STM32_SW == STM32_SW_PLL) +#define STM32_SYSCLK STM32_PLL_R_CLKOUT + +#else +#error "invalid STM32_SW value specified" +#endif + +/* Bus handlers.*/ +#include "stm32_ahb.inc" +#include "stm32_apb1.inc" +#include "stm32_apb2.inc" + +/** + * @brief HCLK2 (CPU2) frequency. + */ +#if (STM32_C2HPRE == STM32_C2HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK2 (STM32_SYSCLK / 1) + +#elif STM32_C2HPRE == STM32_C2HPRE_DIV2 +#define STM32_HCLK2 (STM32_SYSCLK / 2) + +#elif STM32_C2HPRE == STM32_C2HPRE_DIV3 +#define STM32_HCLK2 (STM32_SYSCLK / 3) + +#elif STM32_C2HPRE == STM32_C2HPRE_DIV4 +#define STM32_HCLK2 (STM32_SYSCLK / 4) + +#elif STM32_C2HPRE == STM32_C2HPRE_DIV5 +#define STM32_HCLK2 (STM32_SYSCLK / 5) + +#elif STM32_C2HPRE == STM32_C2HPRE_DIV6 +#define STM32_HCLK2 (STM32_SYSCLK / 6) + +#elif STM32_C2HPRE == STM32_C2HPRE_DIV8 +#define STM32_HCLK2 (STM32_SYSCLK / 8) + +#elif STM32_C2HPRE == STM32_C2HPRE_DIV10 +#define STM32_HCLK2 (STM32_SYSCLK / 10) + +#elif STM32_C2HPRE == STM32_C2HPRE_DIV16 +#define STM32_HCLK2 (STM32_SYSCLK / 16) + +#elif STM32_C2HPRE == STM32_C2HPRE_DIV32 +#define STM32_HCLK2 (STM32_SYSCLK / 32) + +#elif STM32_C2HPRE == STM32_C2HPRE_DIV64 +#define STM32_HCLK2 (STM32_SYSCLK / 64) + +#elif STM32_C2HPRE == STM32_C2HPRE_DIV128 +#define STM32_HCLK2 (STM32_SYSCLK / 128) + +#elif STM32_C2HPRE == STM32_C2HPRE_DIV256 +#define STM32_HCLK2 (STM32_SYSCLK / 256) + +#elif STM32_C2HPRE == STM32_C2HPRE_DIV512 +#define STM32_HCLK2 (STM32_SYSCLK / 512) + +#else +#error "invalid STM32_C2HPRE value specified" +#endif + +/* + * HCLK2 (CPU2) frequency check. + */ +#if STM32_HCLK2 > STM32_C2HPRE_MAX +#error "STM32_HCLK2 exceeding maximum frequency (STM32_C2HPRE_MAX)" +#endif + +/** + * @brief AHB4 frequency. + */ +#if (STM32_SHDHPRE == STM32_SHDHPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK4 (STM32_SYSCLK / 1) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV2 +#define STM32_HCLK4 (STM32_SYSCLK / 2) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV3 +#define STM32_HCLK4 (STM32_SYSCLK / 3) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV4 +#define STM32_HCLK4 (STM32_SYSCLK / 4) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV5 +#define STM32_HCLK4 (STM32_SYSCLK / 5) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV6 +#define STM32_HCLK4 (STM32_SYSCLK / 6) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV8 +#define STM32_HCLK4 (STM32_SYSCLK / 8) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV10 +#define STM32_HCLK4 (STM32_SYSCLK / 10) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV16 +#define STM32_HCLK4 (STM32_SYSCLK / 16) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV32 +#define STM32_HCLK4 (STM32_SYSCLK / 32) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV64 +#define STM32_HCLK4 (STM32_SYSCLK / 64) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV128 +#define STM32_HCLK4 (STM32_SYSCLK / 128) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV256 +#define STM32_HCLK4 (STM32_SYSCLK / 256) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV512 +#define STM32_HCLK4 (STM32_SYSCLK / 512) + +#else +#error "invalid STM32_SHDHPRE value specified" +#endif + +/** + * @brief STM32_PLLSAI1PEN field. + */ +#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1PCLK) || \ + defined(__DOXYGEN__) +#define STM32_PLLSAI1PEN (1 << 16) +#else +#define STM32_PLLSAI1PEN (0 << 16) +#endif + +/** + * @brief STM32_PLLSAI1QEN field. + */ +#if (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1QCLK) || defined(__DOXYGEN__) +#define STM32_PLLSAI1QEN (1 << 24) +#else +#define STM32_PLLSAI1QEN (0 << 24) +#endif + +/** + * @brief STM32_PLLSAI1REN field. + */ +#if (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1RCLK) || defined(__DOXYGEN__) +#define STM32_PLLSAI1REN (1 << 28) +#else +#define STM32_PLLSAI1REN (0 << 28) +#endif + +/* Inclusion of PLLSAI-related checks and calculations, all PLLs share the + same clock source so enforcing this condition.*/ +#define STM32_PLLSAI1CLKIN STM32_PLLCLKIN +#include "stm32_pllsai1_v2.inc" + +/** + * @brief MCO divider clock frequency. + */ +#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__) +#define STM32_MCODIVCLK 0 + +#elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK +#define STM32_MCODIVCLK STM32_SYSCLK + +#elif STM32_MCOSEL == STM32_MCOSEL_MSI +#define STM32_MCODIVCLK STM32_MSICLK + +#elif STM32_MCOSEL == STM32_MCOSEL_HSI16 +#define STM32_MCODIVCLK STM32_HSI16CLK + +#elif STM32_MCOSEL == STM32_MCOSEL_HSE +#define STM32_MCODIVCLK STM32_HSE32CLK + +#elif STM32_MCOSEL == STM32_MCOSEL_PLLRCLK +#define STM32_MCODIVCLK STM32_PLL_P_CLKOUT + +#elif (STM32_MCOSEL == STM32_MCOSEL_LSI1 || STM32_MCOSEL == STM32_MCOSEL_LSI2) +#define STM32_MCODIVCLK STM32_LSICLK + +#elif STM32_MCOSEL == STM32_MCOSEL_LSE +#define STM32_MCODIVCLK STM32_LSECLK + +#elif STM32_MCOSEL == STM32_MCOSEL_HSI48 +#define STM32_MCODIVCLK STM32_HSI48CLK + +#else +#error "invalid STM32_MCOSEL value specified" +#endif + +/** + * @brief MCO output pin clock frequency. + */ +#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_MCOCLK STM32_MCODIVCLK + +#elif STM32_MCOPRE == STM32_MCOPRE_DIV2 +#define STM32_MCOCLK (STM32_MCODIVCLK / 2) + +#elif STM32_MCOPRE == STM32_MCOPRE_DIV4 +#define STM32_MCOCLK (STM32_MCODIVCLK / 4) + +#elif STM32_MCOPRE == STM32_MCOPRE_DIV8 +#define STM32_MCOCLK (STM32_MCODIVCLK / 8) + +#elif STM32_MCOPRE == STM32_MCOPRE_DIV16 +#define STM32_MCOCLK (STM32_MCODIVCLK / 16) + +#else +#error "invalid STM32_MCOPRE value specified" +#endif + +/** + * @brief RTC clock frequency. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__) +#define STM32_RTCCLK 0 + +#elif STM32_RTCSEL == STM32_RTCSEL_LSE +#define STM32_RTCCLK STM32_LSECLK + +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK + +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK (STM32_HSE32CLK / 32) + +#else +#error "invalid STM32_RTCSEL value specified" +#endif + +/** + * @brief USART1 clock frequency. + */ +#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__) +#define STM32_USART1CLK STM32_PCLK2 +#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK +#define STM32_USART1CLK STM32_SYSCLK +#elif STM32_USART1SEL == STM32_USART1SEL_HSI16 +#define STM32_USART1CLK STM32_HSI16CLK +#elif STM32_USART1SEL == STM32_USART1SEL_LSE +#define STM32_USART1CLK STM32_LSECLK +#else +#error "invalid source selected for USART1 clock" +#endif + +/** + * @brief LPUART1 clock frequency. + */ +#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK1) || defined(__DOXYGEN__) +#define STM32_LPUART1CLK STM32_PCLK1 +#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK +#define STM32_LPUART1CLK STM32_SYSCLK +#elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16 +#define STM32_LPUART1CLK STM32_HSI16CLK +#elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE +#define STM32_LPUART1CLK STM32_LSECLK +#else +#error "invalid source selected for LPUART1 clock" +#endif + +/** + * @brief I2C1 clock frequency. + */ +#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__) +#define STM32_I2C1CLK STM32_PCLK1 +#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK +#define STM32_I2C1CLK STM32_SYSCLK +#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI16 +#define STM32_I2C1CLK STM32_HSI16CLK +#else +#error "invalid source selected for I2C1 clock" +#endif + +/** + * @brief I2C3 clock frequency. + */ +#if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK1) || defined(__DOXYGEN__) +#define STM32_I2C3CLK STM32_PCLK1 +#elif STM32_I2C3SEL == STM32_I2C3SEL_SYSCLK +#define STM32_I2C3CLK STM32_SYSCLK +#elif STM32_I2C3SEL == STM32_I2C3SEL_HSI16 +#define STM32_I2C3CLK STM32_HSI16CLK +#else +#error "invalid source selected for I2C3 clock" +#endif + +/** + * @brief LPTIM1 clock frequency. + */ +#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__) +#define STM32_LPTIM1CLK STM32_PCLK1 +#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI +#define STM32_LPTIM1CLK STM32_LSICLK +#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16 +#define STM32_LPTIM1CLK STM32_HSI16CLK +#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE +#define STM32_LPTIM1CLK STM32_LSECLK +#else +#error "invalid source selected for LPTIM1 clock" +#endif + +/** + * @brief LPTIM2 clock frequency. + */ +#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK1) || defined(__DOXYGEN__) +#define STM32_LPTIM2CLK STM32_PCLK1 +#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSI +#define STM32_LPTIM2CLK STM32_LSICLK +#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16 +#define STM32_LPTIM2CLK STM32_HSI16CLK +#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSE +#define STM32_LPTIM2CLK STM32_LSECLK +#else +#error "invalid source selected for LPTIM2 clock" +#endif + +/** + * @brief 48MHz clock frequency. + */ +#if (STM32_CLK48SEL == STM32_CLK48SEL_HSI48) || defined(__DOXYGEN__) +#define STM32_48CLK STM32_HSI48CLK +#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1QCLK +#define STM32_48CLK (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE) +#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK +#define STM32_48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE) +#elif STM32_CLK48SEL == STM32_CLK48SEL_MSI +#define STM32_48CLK STM32_MSICLK +#else +#error "invalid source selected for 48CLK clock" +#endif + +/** + * @brief SAI1 clock frequency. + */ +#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1PCLK) || defined(__DOXYGEN__) +#define STM32_SAI1CLK STM32_PLLSAI1_P_CLKOUT +#elif STM32_SAI1SEL == STM32_SAI1SEL_PLLPCLK +#define STM32_SAI1CLK STM32_PLL_P_CLKOUT +#elif STM32_SAI1SEL == STM32_SAI1SEL_EXTCLK +#define STM32_SAI1CLK 0 /* Unknown, would require a board value */ +#elif STM32_SAI1SEL == STM32_SAI1SEL_OFF +#define STM32_SAI1CLK 0 +#else +#error "invalid source selected for SAI1 clock" +#endif + +/** + * @brief USB clock point. + */ +#define STM32_USBCLK STM32_48CLK + +/** + * @brief RNG clock frequency. + */ +#if (STM32_RNGSEL == STM32_RNGSEL_48CLK) || defined(__DOXYGEN__) +#define STM32_RNGCLK STM32_48CLK +#elif STM32_RNGSEL == STM32_RNGSEL_LSI +#define STM32_RNGCLK STM32_LSICLK +#elif STM32_RNGSEL == STM32_RNGSEL_LSE +#define STM32_RNGCLK STM32_LSECLK +#else +#error "invalid source selected for RNG clock" +#endif + +/** + * @brief ADC clock frequency. + */ +#if (STM32_ADCSEL == STM32_ADCSEL_NOCLK) || defined(__DOXYGEN__) +#define STM32_ADCCLK 0 +#elif STM32_ADCSEL == STM32_ADCSEL_PLLSAI1RCLK +#define STM32_ADCCLK STM32_PLLSAI1_R_CLKOUT +#elif STM32_ADCSEL == STM32_ADCSEL_PLLPCLK +#define STM32_ADCCLK STM32_PLL_P_CLKOUT +#elif STM32_ADCSEL == STM32_ADCSEL_SYSCLK +#define STM32_ADCCLK STM32_SYSCLK +#else +#error "invalid source selected for ADC clock" +#endif + +/** + * @brief SDMMC frequency. + */ +#define STM32_SDMMC1CLK STM32_48CLK + +/** + * @brief Clock of timers connected to APB1 + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Clock of timers connected to APB2. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__) +#define STM32_FLASHBITS FLASH_ACR_LATENCY_0WS + +#elif STM32_HCLK <= STM32_1WS_THRESHOLD +#define STM32_FLASHBITS FLASH_ACR_LATENCY_1WS + +#elif STM32_HCLK <= STM32_2WS_THRESHOLD +#define STM32_FLASHBITS FLASH_ACR_LATENCY_2WS + +#else +#define STM32_FLASHBITS FLASH_ACR_LATENCY_3WS +#endif + +/** + * @brief Flash settings for MSI. + */ +#if (STM32_MSICLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__) +#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_0WS + +#elif STM32_MSICLK <= STM32_1WS_THRESHOLD +#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_1WS + +#elif STM32_MSICLK <= STM32_2WS_THRESHOLD +#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_2WS + +#else +#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_3WS +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* Various helpers.*/ +#include "nvic.h" +#include "cache.h" +#include "mpu_v7m.h" +#include "stm32_isr.h" +#include "stm32_dma.h" +#include "stm32_exti.h" +#include "stm32_rcc.h" +#include "stm32_tim.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void stm32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32WBxx/stm32_dmamux.h b/os/hal/ports/STM32/STM32WBxx/stm32_dmamux.h index bec662816..6ceb99227 100644 --- a/os/hal/ports/STM32/STM32WBxx/stm32_dmamux.h +++ b/os/hal/ports/STM32/STM32WBxx/stm32_dmamux.h @@ -1,109 +1,109 @@ -/* - ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Ilya Kharin. -*/ - -/** - * @file STM32WBxx/stm32_dmamux.h - * @brief STM32WBxx DMAMUX handler header. - * - * @addtogroup STM32WBxxp_DMAMUX - * @{ - */ - -#ifndef STM32_DMAMUX_H -#define STM32_DMAMUX_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name DMAMUX1 request sources - * @{ - */ -#define STM32_DMAMUX1_REQ_GEN0 1 -#define STM32_DMAMUX1_REQ_GEN1 2 -#define STM32_DMAMUX1_REQ_GEN2 3 -#define STM32_DMAMUX1_REQ_GEN3 4 -#define STM32_DMAMUX1_ADC1 5 -#define STM32_DMAMUX1_SPI1_RX 6 -#define STM32_DMAMUX1_SPI1_TX 7 -#define STM32_DMAMUX1_SPI2_RX 8 -#define STM32_DMAMUX1_SPI2_TX 9 -#define STM32_DMAMUX1_I2C1_RX 10 -#define STM32_DMAMUX1_I2C1_TX 11 -#define STM32_DMAMUX1_I2C3_RX 12 -#define STM32_DMAMUX1_I2C3_TX 13 -#define STM32_DMAMUX1_USART1_RX 14 -#define STM32_DMAMUX1_USART1_TX 15 -#define STM32_DMAMUX1_LPUART1_RX 16 -#define STM32_DMAMUX1_LPUART1_TX 17 -#define STM32_DMAMUX1_SAI1_A 18 -#define STM32_DMAMUX1_SAI1_B 19 -#define STM32_DMAMUX1_QUADSPI 20 -#define STM32_DMAMUX1_TIM1_CH1 21 -#define STM32_DMAMUX1_TIM1_CH2 22 -#define STM32_DMAMUX1_TIM1_CH3 23 -#define STM32_DMAMUX1_TIM1_CH4 24 -#define STM32_DMAMUX1_TIM1_UP 25 -#define STM32_DMAMUX1_TIM1_TRIG 26 -#define STM32_DMAMUX1_TIM1_COM 27 -#define STM32_DMAMUX1_TIM2_CH1 28 -#define STM32_DMAMUX1_TIM2_CH2 29 -#define STM32_DMAMUX1_TIM2_CH3 30 -#define STM32_DMAMUX1_TIM2_CH4 31 -#define STM32_DMAMUX1_TIM2_UP 32 -#define STM32_DMAMUX1_TIM16_CH1 33 -#define STM32_DMAMUX1_TIM16_UP 34 -#define STM32_DMAMUX1_TIM17_CH1 35 -#define STM32_DMAMUX1_TIM17_UP 36 -#define STM32_DMAMUX1_CRYP_IN 37 -#define STM32_DMAMUX1_CRYP_OUT 38 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* STM32_DMAMUX_H */ - -/** @} */ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Ilya Kharin. +*/ + +/** + * @file STM32WBxx/stm32_dmamux.h + * @brief STM32WBxx DMAMUX handler header. + * + * @addtogroup STM32WBxxp_DMAMUX + * @{ + */ + +#ifndef STM32_DMAMUX_H +#define STM32_DMAMUX_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name DMAMUX1 request sources + * @{ + */ +#define STM32_DMAMUX1_REQ_GEN0 1 +#define STM32_DMAMUX1_REQ_GEN1 2 +#define STM32_DMAMUX1_REQ_GEN2 3 +#define STM32_DMAMUX1_REQ_GEN3 4 +#define STM32_DMAMUX1_ADC1 5 +#define STM32_DMAMUX1_SPI1_RX 6 +#define STM32_DMAMUX1_SPI1_TX 7 +#define STM32_DMAMUX1_SPI2_RX 8 +#define STM32_DMAMUX1_SPI2_TX 9 +#define STM32_DMAMUX1_I2C1_RX 10 +#define STM32_DMAMUX1_I2C1_TX 11 +#define STM32_DMAMUX1_I2C3_RX 12 +#define STM32_DMAMUX1_I2C3_TX 13 +#define STM32_DMAMUX1_USART1_RX 14 +#define STM32_DMAMUX1_USART1_TX 15 +#define STM32_DMAMUX1_LPUART1_RX 16 +#define STM32_DMAMUX1_LPUART1_TX 17 +#define STM32_DMAMUX1_SAI1_A 18 +#define STM32_DMAMUX1_SAI1_B 19 +#define STM32_DMAMUX1_QUADSPI 20 +#define STM32_DMAMUX1_TIM1_CH1 21 +#define STM32_DMAMUX1_TIM1_CH2 22 +#define STM32_DMAMUX1_TIM1_CH3 23 +#define STM32_DMAMUX1_TIM1_CH4 24 +#define STM32_DMAMUX1_TIM1_UP 25 +#define STM32_DMAMUX1_TIM1_TRIG 26 +#define STM32_DMAMUX1_TIM1_COM 27 +#define STM32_DMAMUX1_TIM2_CH1 28 +#define STM32_DMAMUX1_TIM2_CH2 29 +#define STM32_DMAMUX1_TIM2_CH3 30 +#define STM32_DMAMUX1_TIM2_CH4 31 +#define STM32_DMAMUX1_TIM2_UP 32 +#define STM32_DMAMUX1_TIM16_CH1 33 +#define STM32_DMAMUX1_TIM16_UP 34 +#define STM32_DMAMUX1_TIM17_CH1 35 +#define STM32_DMAMUX1_TIM17_UP 36 +#define STM32_DMAMUX1_CRYP_IN 37 +#define STM32_DMAMUX1_CRYP_OUT 38 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_DMAMUX_H */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32WBxx/stm32_isr.c b/os/hal/ports/STM32/STM32WBxx/stm32_isr.c index d442a61de..46fd0a575 100644 --- a/os/hal/ports/STM32/STM32WBxx/stm32_isr.c +++ b/os/hal/ports/STM32/STM32WBxx/stm32_isr.c @@ -1,134 +1,134 @@ -/* - ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Ilya Kharin. -*/ - -/** - * @file STM32WBxx/stm32_isr.h - * @brief STM32WBxx ISR handler code. - * - * @addtogroup STM32WBxx_ISR - * @{ - */ - -#include "hal.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -#define exti_serve_irq(pr, channel) { \ - \ - if ((pr) & (1U << (channel))) { \ - _pal_isr_code(channel); \ - } \ -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#include "stm32_exti0.inc" -#include "stm32_exti1.inc" -#include "stm32_exti2.inc" -#include "stm32_exti3.inc" -#include "stm32_exti4.inc" -#include "stm32_exti5_9.inc" -#include "stm32_exti10_15.inc" -#include "stm32_exti16-31-33.inc" -#include "stm32_exti17.inc" -#include "stm32_exti18.inc" -#include "stm32_exti19.inc" -#include "stm32_exti20_21.inc" - -#include "stm32_usart1.inc" -#include "stm32_lpuart1.inc" - -#include "stm32_tim1_16_17.inc" -#include "stm32_tim2.inc" - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enables IRQ sources. - * - * @notapi - */ -void irqInit(void) { - - exti0_irq_init(); - exti1_irq_init(); - exti2_irq_init(); - exti3_irq_init(); - exti4_irq_init(); - exti5_9_irq_init(); - exti10_15_irq_init(); - exti16_exti31_exti33_irq_init(); - exti17_irq_init(); - exti18_irq_init(); - exti19_irq_init(); - exti20_exti21_irq_init(); - - tim1_tim16_tim17_irq_init(); - tim2_irq_init(); - - usart1_irq_init(); - lpuart1_irq_init(); -} - -/** - * @brief Disables IRQ sources. - * - * @notapi - */ -void irqDeinit(void) { - - exti0_irq_deinit(); - exti1_irq_deinit(); - exti2_irq_deinit(); - exti3_irq_deinit(); - exti4_irq_deinit(); - exti5_9_irq_deinit(); - exti10_15_irq_deinit(); - exti16_exti31_exti33_irq_deinit(); - exti17_irq_deinit(); - exti18_irq_deinit(); - exti19_irq_deinit(); - exti20_exti21_irq_deinit(); - - tim1_tim16_tim17_irq_deinit(); - tim2_irq_deinit(); - - usart1_irq_deinit(); - lpuart1_irq_deinit(); -} - -/** @} */ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Ilya Kharin. +*/ + +/** + * @file STM32WBxx/stm32_isr.h + * @brief STM32WBxx ISR handler code. + * + * @addtogroup STM32WBxx_ISR + * @{ + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#define exti_serve_irq(pr, channel) { \ + \ + if ((pr) & (1U << (channel))) { \ + _pal_isr_code(channel); \ + } \ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#include "stm32_exti0.inc" +#include "stm32_exti1.inc" +#include "stm32_exti2.inc" +#include "stm32_exti3.inc" +#include "stm32_exti4.inc" +#include "stm32_exti5_9.inc" +#include "stm32_exti10_15.inc" +#include "stm32_exti16-31-33.inc" +#include "stm32_exti17.inc" +#include "stm32_exti18.inc" +#include "stm32_exti19.inc" +#include "stm32_exti20_21.inc" + +#include "stm32_usart1.inc" +#include "stm32_lpuart1.inc" + +#include "stm32_tim1_16_17.inc" +#include "stm32_tim2.inc" + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables IRQ sources. + * + * @notapi + */ +void irqInit(void) { + + exti0_irq_init(); + exti1_irq_init(); + exti2_irq_init(); + exti3_irq_init(); + exti4_irq_init(); + exti5_9_irq_init(); + exti10_15_irq_init(); + exti16_exti31_exti33_irq_init(); + exti17_irq_init(); + exti18_irq_init(); + exti19_irq_init(); + exti20_exti21_irq_init(); + + tim1_tim16_tim17_irq_init(); + tim2_irq_init(); + + usart1_irq_init(); + lpuart1_irq_init(); +} + +/** + * @brief Disables IRQ sources. + * + * @notapi + */ +void irqDeinit(void) { + + exti0_irq_deinit(); + exti1_irq_deinit(); + exti2_irq_deinit(); + exti3_irq_deinit(); + exti4_irq_deinit(); + exti5_9_irq_deinit(); + exti10_15_irq_deinit(); + exti16_exti31_exti33_irq_deinit(); + exti17_irq_deinit(); + exti18_irq_deinit(); + exti19_irq_deinit(); + exti20_exti21_irq_deinit(); + + tim1_tim16_tim17_irq_deinit(); + tim2_irq_deinit(); + + usart1_irq_deinit(); + lpuart1_irq_deinit(); +} + +/** @} */ diff --git a/os/hal/ports/STM32/STM32WBxx/stm32_isr.h b/os/hal/ports/STM32/STM32WBxx/stm32_isr.h index c9873a16e..3d0973495 100644 --- a/os/hal/ports/STM32/STM32WBxx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32WBxx/stm32_isr.h @@ -1,206 +1,206 @@ -/* - ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Ilya Kharin. -*/ - -/** - * @file STM32WBxx/stm32_isr.h - * @brief STM32WBxx ISR handler header. - * - * @addtogroup SRM32WBxx_ISR - * @{ - */ - -#ifndef STM32_ISR_H -#define STM32_ISR_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name ISRs suppressed in standard drivers - * @{ - */ -#define STM32_TIM1_SUPPRESS_ISR -#define STM32_TIM2_SUPPRESS_ISR -#define STM32_TIM16_SUPPRESS_ISR -#define STM32_TIM17_SUPPRESS_ISR - -#define STM32_USART1_SUPPRESS_ISR -#define STM32_LPUART1_SUPPRESS_ISR -/** @} */ - -/** - * @name ISR names and numbers - * @{ - */ -/* - * ADC unit. - */ -#define STM32_ADC1_HANDLER Vector88 - -#define STM32_ADC1_NUMBER 18 - -/* - * DMA unit. - */ -#define STM32_DMA1_CH1_HANDLER Vector6C -#define STM32_DMA1_CH2_HANDLER Vector70 -#define STM32_DMA1_CH3_HANDLER Vector74 -#define STM32_DMA1_CH4_HANDLER Vector78 -#define STM32_DMA1_CH5_HANDLER Vector7C -#define STM32_DMA1_CH6_HANDLER Vector80 -#define STM32_DMA1_CH7_HANDLER Vector84 -#define STM32_DMA2_CH1_HANDLER Vector11C -#define STM32_DMA2_CH2_HANDLER Vector120 -#define STM32_DMA2_CH3_HANDLER Vector124 -#define STM32_DMA2_CH4_HANDLER Vector128 -#define STM32_DMA2_CH5_HANDLER Vector12C -#define STM32_DMA2_CH6_HANDLER Vector130 -#define STM32_DMA2_CH7_HANDLER Vector134 - -#define STM32_DMA1_CH1_NUMBER 11 -#define STM32_DMA1_CH2_NUMBER 12 -#define STM32_DMA1_CH3_NUMBER 13 -#define STM32_DMA1_CH4_NUMBER 14 -#define STM32_DMA1_CH5_NUMBER 15 -#define STM32_DMA1_CH6_NUMBER 16 -#define STM32_DMA1_CH7_NUMBER 17 -#define STM32_DMA2_CH1_NUMBER 55 -#define STM32_DMA2_CH2_NUMBER 56 -#define STM32_DMA2_CH3_NUMBER 57 -#define STM32_DMA2_CH4_NUMBER 58 -#define STM32_DMA2_CH5_NUMBER 59 -#define STM32_DMA2_CH6_NUMBER 60 -#define STM32_DMA2_CH7_NUMBER 61 - -/* - * EXTI unit. - */ -#define STM32_EXTI0_HANDLER Vector58 -#define STM32_EXTI1_HANDLER Vector5C -#define STM32_EXTI2_HANDLER Vector60 -#define STM32_EXTI3_HANDLER Vector64 -#define STM32_EXTI4_HANDLER Vector68 -#define STM32_EXTI5_9_HANDLER Vector9C -#define STM32_EXTI10_15_HANDLER VectorE0 -#define STM32_EXTI16_31_33_HANDLER Vector44 /* PVD PVM0 PVM2 */ -#define STM32_EXTI17_HANDLER VectorE4 /* RTC ALARM */ -#define STM32_EXTI18_HANDLER Vector48 /* RTC TAMP CSS */ -#define STM32_EXTI19_HANDLER Vector4C /* RTC WAKEUP */ -#define STM32_EXTI20_21_HANDLER Vector98 /* COMP2 COMP1 */ - -#define STM32_EXTI0_NUMBER 6 -#define STM32_EXTI1_NUMBER 7 -#define STM32_EXTI2_NUMBER 8 -#define STM32_EXTI3_NUMBER 9 -#define STM32_EXTI4_NUMBER 10 -#define STM32_EXTI5_9_NUMBER 23 -#define STM32_EXTI10_15_NUMBER 40 -#define STM32_EXTI16_31_33_NUMBER 1 -#define STM32_EXTI17_NUMBER 41 -#define STM32_EXTI18_NUMBER 2 -#define STM32_EXTI19_NUMBER 3 -#define STM32_EXTI20_21_NUMBER 22 - -/* - * I2C units. - */ -#define STM32_I2C1_EVENT_HANDLER VectorB8 -#define STM32_I2C1_ERROR_HANDLER VectorBC -#define STM32_I2C3_EVENT_HANDLER VectorC0 -#define STM32_I2C3_ERROR_HANDLER VectorC4 - -#define STM32_I2C1_EVENT_NUMBER 30 -#define STM32_I2C1_ERROR_NUMBER 31 -#define STM32_I2C3_EVENT_NUMBER 32 -#define STM32_I2C3_ERROR_NUMBER 33 - -/* - * QUADSPI unit. - */ -#define STM32_QUADSPI1_HANDLER Vector108 - -#define STM32_QUADSPI1_NUMBER 50 - -/* - * TIM units. - */ -#define STM32_TIM1_BRK_HANDLER VectorA0 -#define STM32_TIM1_UP_TIM16_HANDLER VectorA4 -#define STM32_TIM1_TRGCO_TIM17_HANDLER VectorA8 -#define STM32_TIM1_CC_HANDLER VectorAC -#define STM32_TIM2_HANDLER VectorB0 - -#define STM32_TIM1_BRK_NUMBER 24 -#define STM32_TIM1_UP_TIM16_NUMBER 25 -#define STM32_TIM1_TRGCO_TIM17_NUMBER 26 -#define STM32_TIM1_CC_NUMBER 27 -#define STM32_TIM2_NUMBER 28 - -/* - * USART/UART units. - */ -#define STM32_USART1_HANDLER VectorD0 -#define STM32_LPUART1_HANDLER VectorD4 - -#define STM32_USART1_NUMBER 36 -#define STM32_LPUART1_NUMBER 37 - -/* - * USB unit. - */ -#define STM32_USB1_HP_HANDLER Vector8C -#define STM32_USB1_LP_HANDLER Vector90 - -#define STM32_USB1_HP_NUMBER 19 -#define STM32_USB1_LP_NUMBER 20 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void irqInit(void); - void irqDeinit(void); -#ifdef __cplusplus -} -#endif - -#endif /* STM32_ISR_H */ - -/** @} */ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Ilya Kharin. +*/ + +/** + * @file STM32WBxx/stm32_isr.h + * @brief STM32WBxx ISR handler header. + * + * @addtogroup SRM32WBxx_ISR + * @{ + */ + +#ifndef STM32_ISR_H +#define STM32_ISR_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name ISRs suppressed in standard drivers + * @{ + */ +#define STM32_TIM1_SUPPRESS_ISR +#define STM32_TIM2_SUPPRESS_ISR +#define STM32_TIM16_SUPPRESS_ISR +#define STM32_TIM17_SUPPRESS_ISR + +#define STM32_USART1_SUPPRESS_ISR +#define STM32_LPUART1_SUPPRESS_ISR +/** @} */ + +/** + * @name ISR names and numbers + * @{ + */ +/* + * ADC unit. + */ +#define STM32_ADC1_HANDLER Vector88 + +#define STM32_ADC1_NUMBER 18 + +/* + * DMA unit. + */ +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA2_CH1_HANDLER Vector11C +#define STM32_DMA2_CH2_HANDLER Vector120 +#define STM32_DMA2_CH3_HANDLER Vector124 +#define STM32_DMA2_CH4_HANDLER Vector128 +#define STM32_DMA2_CH5_HANDLER Vector12C +#define STM32_DMA2_CH6_HANDLER Vector130 +#define STM32_DMA2_CH7_HANDLER Vector134 + +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 +#define STM32_DMA2_CH1_NUMBER 55 +#define STM32_DMA2_CH2_NUMBER 56 +#define STM32_DMA2_CH3_NUMBER 57 +#define STM32_DMA2_CH4_NUMBER 58 +#define STM32_DMA2_CH5_NUMBER 59 +#define STM32_DMA2_CH6_NUMBER 60 +#define STM32_DMA2_CH7_NUMBER 61 + +/* + * EXTI unit. + */ +#define STM32_EXTI0_HANDLER Vector58 +#define STM32_EXTI1_HANDLER Vector5C +#define STM32_EXTI2_HANDLER Vector60 +#define STM32_EXTI3_HANDLER Vector64 +#define STM32_EXTI4_HANDLER Vector68 +#define STM32_EXTI5_9_HANDLER Vector9C +#define STM32_EXTI10_15_HANDLER VectorE0 +#define STM32_EXTI16_31_33_HANDLER Vector44 /* PVD PVM0 PVM2 */ +#define STM32_EXTI17_HANDLER VectorE4 /* RTC ALARM */ +#define STM32_EXTI18_HANDLER Vector48 /* RTC TAMP CSS */ +#define STM32_EXTI19_HANDLER Vector4C /* RTC WAKEUP */ +#define STM32_EXTI20_21_HANDLER Vector98 /* COMP2 COMP1 */ + +#define STM32_EXTI0_NUMBER 6 +#define STM32_EXTI1_NUMBER 7 +#define STM32_EXTI2_NUMBER 8 +#define STM32_EXTI3_NUMBER 9 +#define STM32_EXTI4_NUMBER 10 +#define STM32_EXTI5_9_NUMBER 23 +#define STM32_EXTI10_15_NUMBER 40 +#define STM32_EXTI16_31_33_NUMBER 1 +#define STM32_EXTI17_NUMBER 41 +#define STM32_EXTI18_NUMBER 2 +#define STM32_EXTI19_NUMBER 3 +#define STM32_EXTI20_21_NUMBER 22 + +/* + * I2C units. + */ +#define STM32_I2C1_EVENT_HANDLER VectorB8 +#define STM32_I2C1_ERROR_HANDLER VectorBC +#define STM32_I2C3_EVENT_HANDLER VectorC0 +#define STM32_I2C3_ERROR_HANDLER VectorC4 + +#define STM32_I2C1_EVENT_NUMBER 30 +#define STM32_I2C1_ERROR_NUMBER 31 +#define STM32_I2C3_EVENT_NUMBER 32 +#define STM32_I2C3_ERROR_NUMBER 33 + +/* + * QUADSPI unit. + */ +#define STM32_QUADSPI1_HANDLER Vector108 + +#define STM32_QUADSPI1_NUMBER 50 + +/* + * TIM units. + */ +#define STM32_TIM1_BRK_HANDLER VectorA0 +#define STM32_TIM1_UP_TIM16_HANDLER VectorA4 +#define STM32_TIM1_TRGCO_TIM17_HANDLER VectorA8 +#define STM32_TIM1_CC_HANDLER VectorAC +#define STM32_TIM2_HANDLER VectorB0 + +#define STM32_TIM1_BRK_NUMBER 24 +#define STM32_TIM1_UP_TIM16_NUMBER 25 +#define STM32_TIM1_TRGCO_TIM17_NUMBER 26 +#define STM32_TIM1_CC_NUMBER 27 +#define STM32_TIM2_NUMBER 28 + +/* + * USART/UART units. + */ +#define STM32_USART1_HANDLER VectorD0 +#define STM32_LPUART1_HANDLER VectorD4 + +#define STM32_USART1_NUMBER 36 +#define STM32_LPUART1_NUMBER 37 + +/* + * USB unit. + */ +#define STM32_USB1_HP_HANDLER Vector8C +#define STM32_USB1_LP_HANDLER Vector90 + +#define STM32_USB1_HP_NUMBER 19 +#define STM32_USB1_LP_NUMBER 20 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void irqInit(void); + void irqDeinit(void); +#ifdef __cplusplus +} +#endif + +#endif /* STM32_ISR_H */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32WBxx/stm32_rcc.h b/os/hal/ports/STM32/STM32WBxx/stm32_rcc.h index 80193391d..08f960b21 100644 --- a/os/hal/ports/STM32/STM32WBxx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32WBxx/stm32_rcc.h @@ -1,795 +1,795 @@ -/* - ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Ilya Kharin. -*/ - -/** - * @file STM32WBxx/stm32_rcc.h - * @brief RCC helper driver header. - * @note This file requires definitions from the ST header file - * @p stm32WBxx.h. - * - * @addtogroup STM32WDxx_RCC - * @{ - */ -#ifndef STM32_RCC_H -#define STM32_RCC_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Generic RCC operations - * @{ - */ -/** - * @brief Enables the clock of one or more peripheral on the APB1 bus (R1). - * - * @param[in] mask APB1 R1 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAPB1R1(mask, lp) { \ - RCC->APB1ENR1 |= (mask); \ - if (lp) \ - RCC->APB1SMENR1 |= (mask); \ - else \ - RCC->APB1SMENR1 &= ~(mask); \ - (void)RCC->APB1SMENR1; \ -} - -/** - * @brief Disables the clock of one or more peripheral on the APB1 bus (R1). - * - * @param[in] mask APB1 R1 peripherals mask - * - * @api - */ -#define rccDisableAPB1R1(mask) { \ - RCC->APB1ENR1 &= ~(mask); \ - RCC->APB1SMENR1 &= ~(mask); \ - (void)RCC->APB1SMENR1; \ -} - -/** - * @brief Resets one or more peripheral on the APB1 bus (R1). - * - * @param[in] mask APB1 R1 peripherals mask - * - * @api - */ -#define rccResetAPB1R1(mask) { \ - RCC->APB1RSTR1 |= (mask); \ - RCC->APB1RSTR1 &= ~(mask); \ - (void)RCC->APB1RSTR1; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the APB1 bus (R2). - * - * @param[in] mask APB1 R2 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAPB1R2(mask, lp) { \ - RCC->APB1ENR2 |= (mask); \ - if (lp) \ - RCC->APB1SMENR2 |= (mask); \ - else \ - RCC->APB1SMENR2 &= ~(mask); \ - (void)RCC->APB1SMENR2; \ -} - -/** - * @brief Disables the clock of one or more peripheral on the APB1 bus (R2). - * - * @param[in] mask APB1 R2 peripherals mask - * - * @api - */ -#define rccDisableAPB1R2(mask) { \ - RCC->APB1ENR2 &= ~(mask); \ - RCC->APB1SMENR2 &= ~(mask); \ - (void)RCC->APB1SMENR2; \ -} - -/** - * @brief Resets one or more peripheral on the APB1 bus (R2). - * - * @param[in] mask APB1 R2 peripherals mask - * - * @api - */ -#define rccResetAPB1R2(mask) { \ - RCC->APB1RSTR2 |= (mask); \ - RCC->APB1RSTR2 &= ~(mask); \ - (void)RCC->APB1RSTR2; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the APB2 bus. - * - * @param[in] mask APB2 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAPB2(mask, lp) { \ - RCC->APB2ENR |= (mask); \ - if (lp) \ - RCC->APB2SMENR |= (mask); \ - else \ - RCC->APB2SMENR &= ~(mask); \ - (void)RCC->APB2SMENR; \ -} - -/** - * @brief Disables the clock of one or more peripheral on the APB2 bus. - * - * @param[in] mask APB2 peripherals mask - * - * @api - */ -#define rccDisableAPB2(mask) { \ - RCC->APB2ENR &= ~(mask); \ - RCC->APB2SMENR &= ~(mask); \ - (void)RCC->APB2SMENR; \ -} - -/** - * @brief Resets one or more peripheral on the APB2 bus. - * - * @param[in] mask APB2 peripherals mask - * - * @api - */ -#define rccResetAPB2(mask) { \ - RCC->APB2RSTR |= (mask); \ - RCC->APB2RSTR &= ~(mask); \ - (void)RCC->APB2RSTR; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the AHB1 bus. - * - * @param[in] mask AHB1 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAHB1(mask, lp) { \ - RCC->AHB1ENR |= (mask); \ - if (lp) \ - RCC->AHB1SMENR |= (mask); \ - else \ - RCC->AHB1SMENR &= ~(mask); \ - (void)RCC->AHB1SMENR; \ -} - -/** - * @brief Disables the clock of one or more peripheral on the AHB1 bus. - * - * @param[in] mask AHB1 peripherals mask - * - * @api - */ -#define rccDisableAHB1(mask) { \ - RCC->AHB1ENR &= ~(mask); \ - RCC->AHB1SMENR &= ~(mask); \ - (void)RCC->AHB1SMENR; \ -} - -/** - * @brief Resets one or more peripheral on the AHB1 bus. - * - * @param[in] mask AHB1 peripherals mask - * - * @api - */ -#define rccResetAHB1(mask) { \ - RCC->AHB1RSTR |= (mask); \ - RCC->AHB1RSTR &= ~(mask); \ - (void)RCC->AHB1RSTR; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the AHB2 bus. - * - * @param[in] mask AHB2 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAHB2(mask, lp) { \ - RCC->AHB2ENR |= (mask); \ - if (lp) \ - RCC->AHB2SMENR |= (mask); \ - else \ - RCC->AHB2SMENR &= ~(mask); \ - (void)RCC->AHB2SMENR; \ -} - -/** - * @brief Disables the clock of one or more peripheral on the AHB2 bus. - * - * @param[in] mask AHB2 peripherals mask - * - * @api - */ -#define rccDisableAHB2(mask) { \ - RCC->AHB2ENR &= ~(mask); \ - RCC->AHB2SMENR &= ~(mask); \ - (void)RCC->AHB2SMENR; \ -} - -/** - * @brief Resets one or more peripheral on the AHB2 bus. - * - * @param[in] mask AHB2 peripherals mask - * - * @api - */ -#define rccResetAHB2(mask) { \ - RCC->AHB2RSTR |= (mask); \ - RCC->AHB2RSTR &= ~(mask); \ - (void)RCC->AHB2RSTR; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus. - * - * @param[in] mask AHB3 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAHB3(mask, lp) { \ - RCC->AHB3ENR |= (mask); \ - if (lp) \ - RCC->AHB3SMENR |= (mask); \ - else \ - RCC->AHB3SMENR &= ~(mask); \ - (void)RCC->AHB3SMENR; \ -} - -/** - * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus. - * - * @param[in] mask AHB3 peripherals mask - * - * @api - */ -#define rccDisableAHB3(mask) { \ - RCC->AHB3ENR &= ~(mask); \ - RCC->AHB3SMENR &= ~(mask); \ - (void)RCC->AHB3SMENR; \ -} - -/** - * @brief Resets one or more peripheral on the AHB3 (FSMC) bus. - * - * @param[in] mask AHB3 peripherals mask - * - * @api - */ -#define rccResetAHB3(mask) { \ - RCC->AHB3RSTR |= (mask); \ - RCC->AHB3RSTR &= ~(mask); \ - (void)RCC->AHB3RSTR; \ -} -/** @} */ - -/** - * @name ADC peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the ADC1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableADC1(lp) rccEnableAHB2(RCC_AHB2ENR_ADCEN, lp) - -/** - * @brief Disables the ADC1 peripheral clock. - * - * @api - */ -#define rccDisableADC1() rccDisableAHB2(RCC_AHB2ENR_ADCEN) - -/** - * @brief Resets the ADC1 peripheral. - * - * @api - */ -#define rccResetADC1() rccResetAHB2(RCC_AHB2RSTR_ADCRST) -/** @} */ - -/** - * @name DMA peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the DMA1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp) - -/** - * @brief Disables the DMA1 peripheral clock. - * - * @api - */ -#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN) - -/** - * @brief Resets the DMA1 peripheral. - * - * @api - */ -#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST) - -/** - * @brief Enables the DMA2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp) - -/** - * @brief Disables the DMA2 peripheral clock. - * - * @api - */ -#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN) - -/** - * @brief Resets the DMA2 peripheral. - * - * @api - */ -#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST) -/** @} */ - -/** - * @name DMAMUX peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the DMAMUX peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableDMAMUX(lp) rccEnableAHB1(RCC_AHB1ENR_DMAMUX1EN, lp) - -/** - * @brief Disables the DMAMUX peripheral clock. - * - * @api - */ -#define rccDisableDMAMUX() rccDisableAHB1(RCC_AHB1ENR_DMAMUX1EN) - -/** - * @brief Resets the DMAMUX peripheral. - * - * @api - */ -#define rccResetDMAMUX() rccResetAHB1(RCC_AHB1RSTR_DMAMUX1RST) -/** @} */ - -/** - * @name I2C peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the I2C1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableI2C1(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C1EN, lp) - -/** - * @brief Disables the I2C1 peripheral clock. - * - * @api - */ -#define rccDisableI2C1() rccDisableAPB1R1(RCC_APB1ENR1_I2C1EN) - -/** - * @brief Resets the I2C1 peripheral. - * - * @api - */ -#define rccResetI2C1() rccResetAPB1R1(RCC_APB1RSTR1_I2C1RST) - -/** - * @brief Enables the I2C3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableI2C3(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C3EN, lp) - -/** - * @brief Disables the I2C3 peripheral clock. - * - * @api - */ -#define rccDisableI2C3() rccDisableAPB1R1(RCC_APB1ENR1_I2C3EN) - -/** - * @brief Resets the I2C3 peripheral. - * - * @api - */ -#define rccResetI2C3() rccResetAPB1R1(RCC_APB1RSTR1_I2C3RST) - -/** - * @name QUADSPI peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the QUADSPI1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp) - -/** - * @brief Disables the QUADSPI1 peripheral clock. - * - * @api - */ -#define rccDisableQUADSPI1() rccDisableAHB3(RCC_AHB3ENR_QSPIEN) - -/** - * @brief Resets the QUADSPI1 peripheral. - * - * @api - */ -#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST) -/** @} */ - -/** - * @name RNG peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the RNG peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableRNG(lp) rccEnableAHB3(RCC_AHB3ENR_RNGEN, lp) - -/** - * @brief Disables the RNG peripheral clock. - * - * @api - */ -#define rccDisableRNG() rccDisableAHB3(RCC_AHB3ENR_RNGEN) - -/** - * @brief Resets the RNG peripheral. - * - * @api - */ -#define rccResetRNG() rccResetAHB3(RCC_AHB3RSTR_RNGRST) -/** @} */ - -/** - * @name SPI peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the SPI1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) - -/** - * @brief Disables the SPI1 peripheral clock. - * - * @api - */ -#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN) - -/** - * @brief Resets the SPI1 peripheral. - * - * @api - */ -#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) - -/** - * @brief Enables the SPI2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI2(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI2EN, lp) - -/** - * @brief Disables the SPI2 peripheral clock. - * - * @api - */ -#define rccDisableSPI2() rccDisableAPB1R1(RCC_APB1ENR1_SPI2EN) - -/** - * @brief Resets the SPI2 peripheral. - * - * @api - */ -#define rccResetSPI2() rccResetAPB1R1(RCC_APB1RSTR1_SPI2RST) - -/** - * @name TIM peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the TIM1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) - -/** - * @brief Disables the TIM1 peripheral clock. - * - * @api - */ -#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN) - -/** - * @brief Resets the TIM1 peripheral. - * - * @api - */ -#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) - -/** - * @brief Enables the TIM2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM2(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM2EN, lp) - -/** - * @brief Disables the TIM2 peripheral clock. - * - * @api - */ -#define rccDisableTIM2() rccDisableAPB1R1(RCC_APB1ENR1_TIM2EN) - -/** - * @brief Resets the TIM2 peripheral. - * - * @api - */ -#define rccResetTIM2() rccResetAPB1R1(RCC_APB1RSTR1_TIM2RST) - -/** - * @brief Enables the TIM16 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp) - -/** - * @brief Disables the TIM16 peripheral clock. - * - * @api - */ -#define rccDisableTIM16() rccDisableAPB2(RCC_APB2ENR_TIM16EN) - -/** - * @brief Resets the TIM16 peripheral. - * - * @api - */ -#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST) - -/** - * @brief Enables the TIM17 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp) - -/** - * @brief Disables the TIM17 peripheral clock. - * - * @api - */ -#define rccDisableTIM17() rccDisableAPB2(RCC_APB2ENR_TIM17EN) - -/** - * @brief Resets the TIM17 peripheral. - * - * @api - */ -#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST) -/** @} */ - -/** - * @name USART/UART peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the USART1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) - -/** - * @brief Disables the USART1 peripheral clock. - * - * @api - */ -#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN) - -/** - * @brief Resets the USART1 peripheral. - * - * @api - */ -#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) - -/** - * @brief Enables the LPUART1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableLPUART1(lp) rccEnableAPB1R2(RCC_APB1ENR2_LPUART1EN, lp) - -/** - * @brief Disables the LPUART1 peripheral clock. - * - * @api - */ -#define rccDisableLPUART1() rccDisableAPB1R2(RCC_APB1ENR2_LPUART1EN) - -/** - * @brief Resets the USART1 peripheral. - * - * @api - */ -#define rccResetLPUART1() rccResetAPB1R2(RCC_APB1RSTR2_LPUART1RST) -/** @} */ - -/** - * @name USB peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the USB peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUSB(lp) rccEnableAPB1R1(RCC_APB1ENR1_USBEN, lp) - -/** - * @brief Disables the USB peripheral clock. - * - * @api - */ -#define rccDisableUSB() rccDisableAPB1R1(RCC_APB1ENR1_USBEN) - -/** - * @brief Resets the USB peripheral. - * - * @api - */ -#define rccResetUSB() rccResetAPB1R1(RCC_APB1RSTR1_USBRST) -/** @} */ - -/** - * @name CRC peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the CRC peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableCRC(lp) rccEnableAHB1(RCC_AHB1ENR_CRCEN, lp) - -/** - * @brief Disables the CRC peripheral clock. - * - * @api - */ -#define rccDisableCRC() rccDisableAHB1(RCC_AHB1ENR_CRCEN) - -/** - * @brief Resets the CRC peripheral. - * - * @api - */ -#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -#ifdef __cplusplus -} -#endif - -#endif /* STM32_RCC_H */ - -/** @} */ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Ilya Kharin. +*/ + +/** + * @file STM32WBxx/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32WBxx.h. + * + * @addtogroup STM32WDxx_RCC + * @{ + */ +#ifndef STM32_RCC_H +#define STM32_RCC_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus (R1). + * + * @param[in] mask APB1 R1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1R1(mask, lp) { \ + RCC->APB1ENR1 |= (mask); \ + if (lp) \ + RCC->APB1SMENR1 |= (mask); \ + else \ + RCC->APB1SMENR1 &= ~(mask); \ + (void)RCC->APB1SMENR1; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus (R1). + * + * @param[in] mask APB1 R1 peripherals mask + * + * @api + */ +#define rccDisableAPB1R1(mask) { \ + RCC->APB1ENR1 &= ~(mask); \ + RCC->APB1SMENR1 &= ~(mask); \ + (void)RCC->APB1SMENR1; \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus (R1). + * + * @param[in] mask APB1 R1 peripherals mask + * + * @api + */ +#define rccResetAPB1R1(mask) { \ + RCC->APB1RSTR1 |= (mask); \ + RCC->APB1RSTR1 &= ~(mask); \ + (void)RCC->APB1RSTR1; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus (R2). + * + * @param[in] mask APB1 R2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1R2(mask, lp) { \ + RCC->APB1ENR2 |= (mask); \ + if (lp) \ + RCC->APB1SMENR2 |= (mask); \ + else \ + RCC->APB1SMENR2 &= ~(mask); \ + (void)RCC->APB1SMENR2; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus (R2). + * + * @param[in] mask APB1 R2 peripherals mask + * + * @api + */ +#define rccDisableAPB1R2(mask) { \ + RCC->APB1ENR2 &= ~(mask); \ + RCC->APB1SMENR2 &= ~(mask); \ + (void)RCC->APB1SMENR2; \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus (R2). + * + * @param[in] mask APB1 R2 peripherals mask + * + * @api + */ +#define rccResetAPB1R2(mask) { \ + RCC->APB1RSTR2 |= (mask); \ + RCC->APB1RSTR2 &= ~(mask); \ + (void)RCC->APB1RSTR2; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB2(mask, lp) { \ + RCC->APB2ENR |= (mask); \ + if (lp) \ + RCC->APB2SMENR |= (mask); \ + else \ + RCC->APB2SMENR &= ~(mask); \ + (void)RCC->APB2SMENR; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccDisableAPB2(mask) { \ + RCC->APB2ENR &= ~(mask); \ + RCC->APB2SMENR &= ~(mask); \ + (void)RCC->APB2SMENR; \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccResetAPB2(mask) { \ + RCC->APB2RSTR |= (mask); \ + RCC->APB2RSTR &= ~(mask); \ + (void)RCC->APB2RSTR; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB1(mask, lp) { \ + RCC->AHB1ENR |= (mask); \ + if (lp) \ + RCC->AHB1SMENR |= (mask); \ + else \ + RCC->AHB1SMENR &= ~(mask); \ + (void)RCC->AHB1SMENR; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * + * @api + */ +#define rccDisableAHB1(mask) { \ + RCC->AHB1ENR &= ~(mask); \ + RCC->AHB1SMENR &= ~(mask); \ + (void)RCC->AHB1SMENR; \ +} + +/** + * @brief Resets one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * + * @api + */ +#define rccResetAHB1(mask) { \ + RCC->AHB1RSTR |= (mask); \ + RCC->AHB1RSTR &= ~(mask); \ + (void)RCC->AHB1RSTR; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB2(mask, lp) { \ + RCC->AHB2ENR |= (mask); \ + if (lp) \ + RCC->AHB2SMENR |= (mask); \ + else \ + RCC->AHB2SMENR &= ~(mask); \ + (void)RCC->AHB2SMENR; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * + * @api + */ +#define rccDisableAHB2(mask) { \ + RCC->AHB2ENR &= ~(mask); \ + RCC->AHB2SMENR &= ~(mask); \ + (void)RCC->AHB2SMENR; \ +} + +/** + * @brief Resets one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * + * @api + */ +#define rccResetAHB2(mask) { \ + RCC->AHB2RSTR |= (mask); \ + RCC->AHB2RSTR &= ~(mask); \ + (void)RCC->AHB2RSTR; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB3(mask, lp) { \ + RCC->AHB3ENR |= (mask); \ + if (lp) \ + RCC->AHB3SMENR |= (mask); \ + else \ + RCC->AHB3SMENR &= ~(mask); \ + (void)RCC->AHB3SMENR; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * + * @api + */ +#define rccDisableAHB3(mask) { \ + RCC->AHB3ENR &= ~(mask); \ + RCC->AHB3SMENR &= ~(mask); \ + (void)RCC->AHB3SMENR; \ +} + +/** + * @brief Resets one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * + * @api + */ +#define rccResetAHB3(mask) { \ + RCC->AHB3RSTR |= (mask); \ + RCC->AHB3RSTR &= ~(mask); \ + (void)RCC->AHB3RSTR; \ +} +/** @} */ + +/** + * @name ADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC1(lp) rccEnableAHB2(RCC_AHB2ENR_ADCEN, lp) + +/** + * @brief Disables the ADC1 peripheral clock. + * + * @api + */ +#define rccDisableADC1() rccDisableAHB2(RCC_AHB2ENR_ADCEN) + +/** + * @brief Resets the ADC1 peripheral. + * + * @api + */ +#define rccResetADC1() rccResetAHB2(RCC_AHB2RSTR_ADCRST) +/** @} */ + +/** + * @name DMA peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * + * @api + */ +#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN) + +/** + * @brief Resets the DMA1 peripheral. + * + * @api + */ +#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST) + +/** + * @brief Enables the DMA2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp) + +/** + * @brief Disables the DMA2 peripheral clock. + * + * @api + */ +#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN) + +/** + * @brief Resets the DMA2 peripheral. + * + * @api + */ +#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST) +/** @} */ + +/** + * @name DMAMUX peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DMAMUX peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMAMUX(lp) rccEnableAHB1(RCC_AHB1ENR_DMAMUX1EN, lp) + +/** + * @brief Disables the DMAMUX peripheral clock. + * + * @api + */ +#define rccDisableDMAMUX() rccDisableAHB1(RCC_AHB1ENR_DMAMUX1EN) + +/** + * @brief Resets the DMAMUX peripheral. + * + * @api + */ +#define rccResetDMAMUX() rccResetAHB1(RCC_AHB1RSTR_DMAMUX1RST) +/** @} */ + +/** + * @name I2C peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * + * @api + */ +#define rccDisableI2C1() rccDisableAPB1R1(RCC_APB1ENR1_I2C1EN) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPB1R1(RCC_APB1RSTR1_I2C1RST) + +/** + * @brief Enables the I2C3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C3(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C3EN, lp) + +/** + * @brief Disables the I2C3 peripheral clock. + * + * @api + */ +#define rccDisableI2C3() rccDisableAPB1R1(RCC_APB1ENR1_I2C3EN) + +/** + * @brief Resets the I2C3 peripheral. + * + * @api + */ +#define rccResetI2C3() rccResetAPB1R1(RCC_APB1RSTR1_I2C3RST) + +/** + * @name QUADSPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the QUADSPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp) + +/** + * @brief Disables the QUADSPI1 peripheral clock. + * + * @api + */ +#define rccDisableQUADSPI1() rccDisableAHB3(RCC_AHB3ENR_QSPIEN) + +/** + * @brief Resets the QUADSPI1 peripheral. + * + * @api + */ +#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST) +/** @} */ + +/** + * @name RNG peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the RNG peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableRNG(lp) rccEnableAHB3(RCC_AHB3ENR_RNGEN, lp) + +/** + * @brief Disables the RNG peripheral clock. + * + * @api + */ +#define rccDisableRNG() rccDisableAHB3(RCC_AHB3ENR_RNGEN) + +/** + * @brief Resets the RNG peripheral. + * + * @api + */ +#define rccResetRNG() rccResetAHB3(RCC_AHB3RSTR_RNGRST) +/** @} */ + +/** + * @name SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * + * @api + */ +#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * + * @api + */ +#define rccDisableSPI2() rccDisableAPB1R1(RCC_APB1ENR1_SPI2EN) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPB1R1(RCC_APB1RSTR1_SPI2RST) + +/** + * @name TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Disables the TIM1 peripheral clock. + * + * @api + */ +#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN) + +/** + * @brief Resets the TIM1 peripheral. + * + * @api + */ +#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) + +/** + * @brief Enables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * + * @api + */ +#define rccDisableTIM2() rccDisableAPB1R1(RCC_APB1ENR1_TIM2EN) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPB1R1(RCC_APB1RSTR1_TIM2RST) + +/** + * @brief Enables the TIM16 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp) + +/** + * @brief Disables the TIM16 peripheral clock. + * + * @api + */ +#define rccDisableTIM16() rccDisableAPB2(RCC_APB2ENR_TIM16EN) + +/** + * @brief Resets the TIM16 peripheral. + * + * @api + */ +#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST) + +/** + * @brief Enables the TIM17 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp) + +/** + * @brief Disables the TIM17 peripheral clock. + * + * @api + */ +#define rccDisableTIM17() rccDisableAPB2(RCC_APB2ENR_TIM17EN) + +/** + * @brief Resets the TIM17 peripheral. + * + * @api + */ +#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST) +/** @} */ + +/** + * @name USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * + * @api + */ +#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) + +/** + * @brief Enables the LPUART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableLPUART1(lp) rccEnableAPB1R2(RCC_APB1ENR2_LPUART1EN, lp) + +/** + * @brief Disables the LPUART1 peripheral clock. + * + * @api + */ +#define rccDisableLPUART1() rccDisableAPB1R2(RCC_APB1ENR2_LPUART1EN) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetLPUART1() rccResetAPB1R2(RCC_APB1RSTR2_LPUART1RST) +/** @} */ + +/** + * @name USB peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the USB peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSB(lp) rccEnableAPB1R1(RCC_APB1ENR1_USBEN, lp) + +/** + * @brief Disables the USB peripheral clock. + * + * @api + */ +#define rccDisableUSB() rccDisableAPB1R1(RCC_APB1ENR1_USBEN) + +/** + * @brief Resets the USB peripheral. + * + * @api + */ +#define rccResetUSB() rccResetAPB1R1(RCC_APB1RSTR1_USBRST) +/** @} */ + +/** + * @name CRC peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the CRC peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCRC(lp) rccEnableAHB1(RCC_AHB1ENR_CRCEN, lp) + +/** + * @brief Disables the CRC peripheral clock. + * + * @api + */ +#define rccDisableCRC() rccDisableAHB1(RCC_AHB1ENR_CRCEN) + +/** + * @brief Resets the CRC peripheral. + * + * @api + */ +#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* STM32_RCC_H */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32WLxx/hal_lld.c b/os/hal/ports/STM32/STM32WLxx/hal_lld.c index e2bb9720b..99d57e701 100644 --- a/os/hal/ports/STM32/STM32WLxx/hal_lld.c +++ b/os/hal/ports/STM32/STM32WLxx/hal_lld.c @@ -279,7 +279,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp, /* PLL VCO frequency.*/ vcoclk = (selclk / (halfreq_t)mdiv) * (halfreq_t)ndiv; - if((vcoclk < slp->pllvco_min) || (vcoclk > slp->pllvco_max)) { + if ((vcoclk < slp->pllvco_min) || (vcoclk > slp->pllvco_max)) { return true; } @@ -291,9 +291,9 @@ static bool hal_lld_check_pll(const system_limits_t *slp, } if ((cfgr & RCC_PLLCFGR_PLLPEN) != 0U) { - pclk = vcoclk / pdiv ; + pclk = vcoclk / pdiv; - if((pclk < slp->pllp_min) || (pclk > slp->pllp_max)) { + if ((pclk < slp->pllp_min) || (pclk > slp->pllp_max)) { return true; } } @@ -308,7 +308,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp, if ((cfgr & RCC_PLLCFGR_PLLQEN) != 0U) { qclk = vcoclk / qdiv; - if((qclk < slp->pllq_min) || (qclk > slp->pllq_max)) { + if ((qclk < slp->pllq_min) || (qclk > slp->pllq_max)) { return true; } } @@ -323,7 +323,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp, if ((cfgr & RCC_PLLCFGR_PLLREN) != 0U) { rclk = vcoclk / rdiv; - if((rclk < slp->pllr_min) || (rclk > slp->pllr_max)) { + if ((rclk < slp->pllr_min) || (rclk > slp->pllr_max)) { return true; } } @@ -415,7 +415,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { } /* SYSCLK frequency.*/ - switch(ccp->rcc_cfgr & RCC_CFGR_SW_Msk) { + switch (ccp->rcc_cfgr & RCC_CFGR_SW_Msk) { case STM32_SW_HSI16: sysclk = hsi16clk; break; @@ -437,7 +437,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { } /* LPRUN sysclk check.*/ - if (((ccp->pwr_cr1 & PWR_CR1_LPR_Msk) != 0U) && (sysclk > STM32_LPRUN_SYSCLK_MAX) ) { + if (((ccp->pwr_cr1 & PWR_CR1_LPR_Msk) != 0U) && (sysclk > STM32_LPRUN_SYSCLK_MAX)) { return true; } @@ -469,7 +469,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { hclk3 = sysclk / hprediv[(ccp->rcc_extcfgr & RCC_EXTCFGR_SHDHPRE_Msk) >> RCC_EXTCFGR_SHDHPRE_Pos]; /* MCO clock.*/ - switch(ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) { + switch (ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) { case STM32_MCOSEL_NOCLOCK: mcoclk = 0U; break; @@ -662,7 +662,6 @@ void hal_lld_init(void) { irqInit(); } - /** * @brief STM32WLxx clocks and PLL initialization. * @note All the involved constants come from the file @p board.h. diff --git a/os/hal/ports/STM32/STM32WLxx/hal_lld.h b/os/hal/ports/STM32/STM32WLxx/hal_lld.h index 205d678aa..eba3933bf 100644 --- a/os/hal/ports/STM32/STM32WLxx/hal_lld.h +++ b/os/hal/ports/STM32/STM32WLxx/hal_lld.h @@ -473,7 +473,6 @@ #define STM32_LSI_ENABLED TRUE #endif - /** * @brief LSI prescaler value. */ diff --git a/os/nil/include/ch.h b/os/nil/include/ch.h index fd85f11f1..50704f541 100644 --- a/os/nil/include/ch.h +++ b/os/nil/include/ch.h @@ -418,7 +418,7 @@ typedef uint8_t ucnt_t; /**< Generic unsigned counter. */ #error "unsupported PORT_ARCH_REGISTERS_WIDTH value" #endif /** @} */ -#endif /* defined(PORT_DOES_NOT_PROVIDE_TYPES) */ +#endif #if (CH_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__) /** diff --git a/os/oslib/src/chobjcaches.c b/os/oslib/src/chobjcaches.c index 09b2ecbc5..f46c3be85 100644 --- a/os/oslib/src/chobjcaches.c +++ b/os/oslib/src/chobjcaches.c @@ -200,7 +200,6 @@ static oc_object_t *lru_get_last_s(objects_cache_t *ocp) { return objp; } - /* Out of critical section.*/ chSysUnlock(); diff --git a/os/rt/include/chearly.h b/os/rt/include/chearly.h index e970cdee9..c0d2ccd35 100644 --- a/os/rt/include/chearly.h +++ b/os/rt/include/chearly.h @@ -119,7 +119,7 @@ typedef uint8_t ucnt_t; /**< Generic unsigned counter. */ #error "unsupported PORT_ARCH_REGISTERS_WIDTH value" #endif /** @} */ -#endif /* defined(PORT_DOES_NOT_PROVIDE_TYPES) */ +#endif /** * @brief Type of a core identifier. @@ -195,16 +195,16 @@ typedef struct ch_os_instance os_instance_t; #endif /** - * @brief Safe cast of a queue pointer to a thread pointer. - * @note Casting to a thread pointer should always be performed using + * @brief Safe cast of a queue pointer to a thread pointer. + * @note Casting to a thread pointer should always be performed using * this macro. Casting to threads pointer is allowed by design * and this is the single check point for this operation. * - * @param[in] p pointer to a queue/list structure - * @return The pointer to the thread containing the queue/list + * @param[in] p pointer to a queue/list structure + * @return The pointer to the thread containing the queue/list * element. */ -#define threadref(p) ((thread_t *)(void *)(p)) +#define threadref(p) ((thread_t *)(void *)(p)) /*===========================================================================*/ /* External declarations. */ diff --git a/os/rt/include/chsys.h b/os/rt/include/chsys.h index 01742c946..04915eaec 100644 --- a/os/rt/include/chsys.h +++ b/os/rt/include/chsys.h @@ -91,7 +91,7 @@ #else #define currcore (&ch0) #endif -#endif /* defined(PORT_INSTANCE_ACCESS) */ +#endif /*===========================================================================*/ /* Module macros. */