diff --git a/demos/STM32/RT-STM32L053-DISCOVERY/cfg/mcuconf.h b/demos/STM32/RT-STM32L053-DISCOVERY/cfg/mcuconf.h index ee5a9b763..e0a250745 100644 --- a/demos/STM32/RT-STM32L053-DISCOVERY/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32L053-DISCOVERY/cfg/mcuconf.h @@ -83,10 +83,16 @@ #define STM32_IRQ_EXTI16_PRIORITY 3 #define STM32_IRQ_EXTI17_20_PRIORITY 3 #define STM32_IRQ_EXTI21_22_PRIORITY 3 + #define STM32_IRQ_USART1_PRIORITY 3 #define STM32_IRQ_USART2_PRIORITY 3 #define STM32_IRQ_LPUART1_PRIORITY 3 +#define STM32_IRQ_TIM2_PRIORITY 1 +#define STM32_IRQ_TIM6_PRIORITY 1 +#define STM32_IRQ_TIM21_PRIORITY 1 +#define STM32_IRQ_TIM22_PRIORITY 1 + /* * ADC driver system settings. * Note, IRQ is shared with EXT channels 21 and 22. @@ -113,10 +119,6 @@ #define STM32_GPT_USE_TIM6 FALSE #define STM32_GPT_USE_TIM21 FALSE #define STM32_GPT_USE_TIM22 FALSE -#define STM32_GPT_TIM2_IRQ_PRIORITY 2 -#define STM32_GPT_TIM6_IRQ_PRIORITY 2 -#define STM32_GPT_TIM21_IRQ_PRIORITY 2 -#define STM32_GPT_TIM22_IRQ_PRIORITY 2 /* * I2C driver system settings. @@ -141,9 +143,6 @@ #define STM32_ICU_USE_TIM2 FALSE #define STM32_ICU_USE_TIM21 FALSE #define STM32_ICU_USE_TIM22 FALSE -#define STM32_ICU_TIM2_IRQ_PRIORITY 3 -#define STM32_ICU_TIM21_IRQ_PRIORITY 3 -#define STM32_ICU_TIM22_IRQ_PRIORITY 3 /* * PWM driver system settings. @@ -151,9 +150,6 @@ #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM21 FALSE #define STM32_PWM_USE_TIM22 FALSE -#define STM32_PWM_TIM2_IRQ_PRIORITY 3 -#define STM32_PWM_TIM21_IRQ_PRIORITY 3 -#define STM32_PWM_TIM22_IRQ_PRIORITY 3 /* * SERIAL driver system settings. @@ -195,6 +191,8 @@ #define STM32_UART_USE_USART2 FALSE #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) diff --git a/demos/STM32/RT-STM32L053R8-NUCLEO64/cfg/mcuconf.h b/demos/STM32/RT-STM32L053R8-NUCLEO64/cfg/mcuconf.h index 6236d4f7f..397d72131 100644 --- a/demos/STM32/RT-STM32L053R8-NUCLEO64/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32L053R8-NUCLEO64/cfg/mcuconf.h @@ -83,10 +83,16 @@ #define STM32_IRQ_EXTI16_PRIORITY 3 #define STM32_IRQ_EXTI17_20_PRIORITY 3 #define STM32_IRQ_EXTI21_22_PRIORITY 3 + #define STM32_IRQ_USART1_PRIORITY 3 #define STM32_IRQ_USART2_PRIORITY 3 #define STM32_IRQ_LPUART1_PRIORITY 3 +#define STM32_IRQ_TIM2_PRIORITY 1 +#define STM32_IRQ_TIM6_PRIORITY 1 +#define STM32_IRQ_TIM21_PRIORITY 1 +#define STM32_IRQ_TIM22_PRIORITY 1 + /* * ADC driver system settings. * Note, IRQ is shared with EXT channels 21 and 22. @@ -113,10 +119,6 @@ #define STM32_GPT_USE_TIM6 FALSE #define STM32_GPT_USE_TIM21 FALSE #define STM32_GPT_USE_TIM22 FALSE -#define STM32_GPT_TIM2_IRQ_PRIORITY 2 -#define STM32_GPT_TIM6_IRQ_PRIORITY 2 -#define STM32_GPT_TIM21_IRQ_PRIORITY 2 -#define STM32_GPT_TIM22_IRQ_PRIORITY 2 /* * I2C driver system settings. @@ -141,9 +143,6 @@ #define STM32_ICU_USE_TIM2 FALSE #define STM32_ICU_USE_TIM21 FALSE #define STM32_ICU_USE_TIM22 FALSE -#define STM32_ICU_TIM2_IRQ_PRIORITY 3 -#define STM32_ICU_TIM21_IRQ_PRIORITY 3 -#define STM32_ICU_TIM22_IRQ_PRIORITY 3 /* * PWM driver system settings. @@ -151,9 +150,6 @@ #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM21 FALSE #define STM32_PWM_USE_TIM22 FALSE -#define STM32_PWM_TIM2_IRQ_PRIORITY 3 -#define STM32_PWM_TIM21_IRQ_PRIORITY 3 -#define STM32_PWM_TIM22_IRQ_PRIORITY 3 /* * SERIAL driver system settings. @@ -195,6 +191,8 @@ #define STM32_UART_USE_USART2 FALSE #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) diff --git a/demos/STM32/RT-STM32L073RZ-NUCLEO64/cfg/mcuconf.h b/demos/STM32/RT-STM32L073RZ-NUCLEO64/cfg/mcuconf.h index e76ba6300..3c81c73ca 100644 --- a/demos/STM32/RT-STM32L073RZ-NUCLEO64/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32L073RZ-NUCLEO64/cfg/mcuconf.h @@ -82,11 +82,19 @@ #define STM32_IRQ_EXTI16_PRIORITY 3 #define STM32_IRQ_EXTI17_20_PRIORITY 3 #define STM32_IRQ_EXTI21_22_PRIORITY 3 + #define STM32_IRQ_USART1_PRIORITY 3 #define STM32_IRQ_USART2_PRIORITY 3 -#define STM32_IRQ_UART4_5_PRIORITY 3 +#define STM32_IRQ_USART4_5_PRIORITY 3 #define STM32_IRQ_LPUART1_PRIORITY 3 +#define STM32_IRQ_TIM2_PRIORITY 1 +#define STM32_IRQ_TIM3_PRIORITY 1 +#define STM32_IRQ_TIM6_PRIORITY 1 +#define STM32_IRQ_TIM7_PRIORITY 1 +#define STM32_IRQ_TIM21_PRIORITY 1 +#define STM32_IRQ_TIM22_PRIORITY 1 + /* * ADC driver system settings. * Note, IRQ is shared with EXT channels 21 and 22. @@ -120,12 +128,6 @@ #define STM32_GPT_USE_TIM7 FALSE #define STM32_GPT_USE_TIM21 FALSE #define STM32_GPT_USE_TIM22 FALSE -#define STM32_GPT_TIM2_IRQ_PRIORITY 2 -#define STM32_GPT_TIM3_IRQ_PRIORITY 2 -#define STM32_GPT_TIM6_IRQ_PRIORITY 2 -#define STM32_GPT_TIM7_IRQ_PRIORITY 2 -#define STM32_GPT_TIM21_IRQ_PRIORITY 2 -#define STM32_GPT_TIM22_IRQ_PRIORITY 2 /* * I2C driver system settings. @@ -156,10 +158,6 @@ #define STM32_ICU_USE_TIM3 FALSE #define STM32_ICU_USE_TIM21 FALSE #define STM32_ICU_USE_TIM22 FALSE -#define STM32_ICU_TIM2_IRQ_PRIORITY 3 -#define STM32_ICU_TIM3_IRQ_PRIORITY 3 -#define STM32_ICU_TIM21_IRQ_PRIORITY 3 -#define STM32_ICU_TIM22_IRQ_PRIORITY 3 /* * PWM driver system settings. @@ -168,10 +166,6 @@ #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM21 FALSE #define STM32_PWM_USE_TIM22 FALSE -#define STM32_PWM_TIM2_IRQ_PRIORITY 3 -#define STM32_PWM_TIM3_IRQ_PRIORITY 3 -#define STM32_PWM_TIM21_IRQ_PRIORITY 3 -#define STM32_PWM_TIM22_IRQ_PRIORITY 3 /* * SERIAL driver system settings. @@ -219,6 +213,9 @@ #define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_UART4_DMA_PRIORITY 0 #define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 +#define STM32_UART_USART4_5_IRQ_PRIORITY 3 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) diff --git a/demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST/cfg/chconf.h b/demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST/cfg/chconf.h index 1db6757f0..fc7525859 100644 --- a/demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST/cfg/chconf.h +++ b/demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST/cfg/chconf.h @@ -729,6 +729,7 @@ /* Port-specific settings (override port settings defaulted in chcore.h). */ /*===========================================================================*/ +#define PORT_USE_SYSCALL TRUE #endif /* CHCONF_H */ /** @} */ diff --git a/os/common/startup/ARMCMx-SB/compilers/GCC/crt0.S b/os/common/startup/ARMCMx-SB/compilers/GCC/crt0.S index cce3548f0..3f8692899 100644 --- a/os/common/startup/ARMCMx-SB/compilers/GCC/crt0.S +++ b/os/common/startup/ARMCMx-SB/compilers/GCC/crt0.S @@ -95,8 +95,8 @@ .section .sandbox, "ax" .align 4 .globl _sandbox -_sandbox: .long 0xFE9154C0U - .long 0x0C4519EFU +_sandbox: .long 0xFE9154C0 + .long 0x0C4519EF .long 16 .long 0 diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim1.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim1.inc index 00285ab02..102b87de4 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim1.inc +++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim1.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_TIM1 not defined in registry" #endif -#if STM32_HAS_TIM1 == FALSE -#error "TIM1 not present" -#endif +#if STM32_HAS_TIM1 /* Priority settings checks.*/ #if !defined(STM32_IRQ_TIM1_UP_PRIORITY) @@ -56,6 +54,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_CC_PRIORITY" #endif +#endif /* STM32_HAS_TIM1 */ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim14.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim14.inc index e77cfbc3e..d390c3d82 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim14.inc +++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim14.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_TIM14 not defined in registry" #endif -#if STM32_HAS_TIM14 == FALSE -#error "TIM14 not present" -#endif +#if STM32_HAS_TIM14 /* Priority settings checks.*/ #if !defined(STM32_IRQ_TIM14_PRIORITY) @@ -48,6 +46,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_TIM14_PRIORITY" #endif +#endif /* STM32_HAS_TIM14 */ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim15.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim15.inc index 15cebfdd2..77c6b94a4 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim15.inc +++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim15.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_TIM15 not defined in registry" #endif -#if STM32_HAS_TIM15 == FALSE -#error "TIM15 not present" -#endif +#if STM32_HAS_TIM15 /* Priority settings checks.*/ #if !defined(STM32_IRQ_TIM15_PRIORITY) @@ -48,6 +46,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_TIM15_PRIORITY" #endif +#endif /* STM32_HAS_TIM15 */ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim16.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim16.inc index ee9e7f4a2..2a12c3bab 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim16.inc +++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim16.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_TIM16 not defined in registry" #endif -#if STM32_HAS_TIM16 == FALSE -#error "TIM16 not present" -#endif +#if STM32_HAS_TIM16 /* Priority settings checks.*/ #if !defined(STM32_IRQ_TIM16_PRIORITY) @@ -48,6 +46,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_TIM16_PRIORITY" #endif +#endif /* STM32_HAS_TIM16 */ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim17.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim17.inc index 09dfe2b98..8411d6155 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim17.inc +++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim17.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_TIM17 not defined in registry" #endif -#if STM32_HAS_TIM17 == FALSE -#error "TIM17 not present" -#endif +#if STM32_HAS_TIM17 /* Priority settings checks.*/ #if !defined(STM32_IRQ_TIM17_PRIORITY) @@ -48,6 +46,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_TIM17_PRIORITY" #endif +#endif /* STM32_HAS_TIM17 */ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim1_15_16_17.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim1_15_16_17.inc index b5862d381..397e8486d 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim1_15_16_17.inc +++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim1_15_16_17.inc @@ -47,21 +47,7 @@ #error "STM32_HAS_TIM17 not defined in registry" #endif -#if STM32_HAS_TIM1 == FALSE -#error "TIM1 not present" -#endif - -#if STM32_HAS_TIM15 == FALSE -#error "TIM15 not present" -#endif - -#if STM32_HAS_TIM16 == FALSE -#error "TIM16 not present" -#endif - -#if STM32_HAS_TIM17 == FALSE -#error "TIM17 not present" -#endif +#if STM32_HAS_TIM1 || STM32_HAS_TIM15 || STM32_HAS_TIM16 || STM32_HAS_TIM17 /* Priority settings checks.*/ #if !defined(STM32_IRQ_TIM1_BRK_TIM15_PRIORITY) @@ -96,6 +82,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_CC_PRIORITY" #endif +#endif /* STM32_HAS_TIM1 || STM32_HAS_TIM15 || STM32_HAS_TIM16 || STM32_HAS_TIM17 */ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim2.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim2.inc index a1709b446..bccae562e 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim2.inc +++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim2.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_TIM2 not defined in registry" #endif -#if STM32_HAS_TIM2 == FALSE -#error "TIM2 not present" -#endif +#if STM32_HAS_TIM1 /* Priority settings checks.*/ #if !defined(STM32_IRQ_TIM2_PRIORITY) @@ -48,6 +46,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_TIM2_PRIORITY" #endif +#endif /* STM32_HAS_TIM2 */ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim20.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim20.inc index a4d2a09c6..019d29616 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim20.inc +++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim20.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_TIM20 not defined in registry" #endif -#if STM32_HAS_TIM20 == FALSE -#error "TIM20 not present" -#endif +#if STM32_HAS_TIM20 /* Priority settings checks.*/ #if !defined(STM32_IRQ_TIM20_UP_PRIORITY) @@ -56,6 +54,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_TIM20_CC_PRIORITY" #endif +#endif /* STM32_HAS_TIM20 */ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim21.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim21.inc new file mode 100644 index 000000000..f7ee1676a --- /dev/null +++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim21.inc @@ -0,0 +1,104 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIMv1/stm32_tim22.inc + * @brief Shared TIM22 handler. + * + * @addtogroup STM32_TIM22_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(STM32_HAS_TIM22) +#error "STM32_HAS_TIM22 not defined in registry" +#endif + +#if STM32_HAS_TIM22 + +/* Priority settings checks.*/ +#if !defined(STM32_IRQ_TIM22_PRIORITY) +#error "STM32_IRQ_TIM22_PRIORITY not defined in mcuconf.h" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM22_PRIORITY) +#error "Invalid IRQ priority assigned to STM32_IRQ_TIM22_PRIORITY" +#endif + +#endif /* STM32_HAS_TIM22 */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void tim22_irq_init(void) { +#if defined(STM32_TIM22_IS_USED) + nvicEnableVector(STM32_TIM22_NUMBER, STM32_IRQ_TIM22_PRIORITY); +#endif +} + +static inline void tim22_irq_deinit(void) { +#if defined(STM32_TIM22_IS_USED) + nvicDisableVector(STM32_TIM22_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (HAL_USE_GPT && STM32_GPT_USE_TIM22) || \ + defined(__DOXYGEN__) +/** + * @brief TIM22 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_TIM22_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_GPT +#if STM32_GPT_USE_TIM22 + gpt_lld_serve_interrupt(&GPTD22); +#endif +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim22.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim22.inc new file mode 100644 index 000000000..3889364a3 --- /dev/null +++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim22.inc @@ -0,0 +1,104 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIMv1/stm32_tim21.inc + * @brief Shared TIM21 handler. + * + * @addtogroup STM32_TIM21_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(STM32_HAS_TIM21) +#error "STM32_HAS_TIM21 not defined in registry" +#endif + +#if STM32_HAS_TIM21 + +/* Priority settings checks.*/ +#if !defined(STM32_IRQ_TIM21_PRIORITY) +#error "STM32_IRQ_TIM21_PRIORITY not defined in mcuconf.h" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM21_PRIORITY) +#error "Invalid IRQ priority assigned to STM32_IRQ_TIM21_PRIORITY" +#endif + +#endif /* STM32_HAS_TIM21 */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void tim21_irq_init(void) { +#if defined(STM32_TIM21_IS_USED) + nvicEnableVector(STM32_TIM21_NUMBER, STM32_IRQ_TIM21_PRIORITY); +#endif +} + +static inline void tim21_irq_deinit(void) { +#if defined(STM32_TIM21_IS_USED) + nvicDisableVector(STM32_TIM21_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (HAL_USE_GPT && STM32_GPT_USE_TIM21) || \ + defined(__DOXYGEN__) +/** + * @brief TIM21 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_TIM21_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_GPT +#if STM32_GPT_USE_TIM21 + gpt_lld_serve_interrupt(&GPTD21); +#endif +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim3.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim3.inc index 135610e87..8c2e375b5 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim3.inc +++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim3.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_TIM3 not defined in registry" #endif -#if STM32_HAS_TIM3 == FALSE -#error "TIM3 not present" -#endif +#if STM32_HAS_TIM3 /* Priority settings checks.*/ #if !defined(STM32_IRQ_TIM3_PRIORITY) @@ -48,6 +46,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_TIM3_PRIORITY" #endif +#endif /* STM32_HAS_TIM3 */ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim4.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim4.inc index b7a610383..7153d5cf5 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim4.inc +++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim4.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_TIM4 not defined in registry" #endif -#if STM32_HAS_TIM4 == FALSE -#error "TIM4 not present" -#endif +#if STM32_HAS_TIM4 /* Priority settings checks.*/ #if !defined(STM32_IRQ_TIM4_PRIORITY) @@ -48,6 +46,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_TIM4_PRIORITY" #endif +#endif /* STM32_HAS_TIM4 */ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim5.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim5.inc index 7d521d59b..89b5fd4f5 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim5.inc +++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim5.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_TIM5 not defined in registry" #endif -#if STM32_HAS_TIM5 == FALSE -#error "TIM5 not present" -#endif +#if STM32_HAS_TIM5 /* Priority settings checks.*/ #if !defined(STM32_IRQ_TIM5_PRIORITY) @@ -48,6 +46,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_TIM5_PRIORITY" #endif +#endif /* STM32_HAS_TIM5 */ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim6.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim6.inc index 49b850698..c48d5465b 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim6.inc +++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim6.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_TIM6 not defined in registry" #endif -#if STM32_HAS_TIM6 == FALSE -#error "TIM6 not present" -#endif +#if STM32_HAS_TIM6 /* Priority settings checks.*/ #if !defined(STM32_IRQ_TIM6_PRIORITY) @@ -48,6 +46,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_TIM6_PRIORITY" #endif +#endif /* STM32_HAS_TIM6 */ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim7.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim7.inc index e205b19fc..4a952ea34 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim7.inc +++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim7.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_TIM7 not defined in registry" #endif -#if STM32_HAS_TIM7 == FALSE -#error "TIM7 not present" -#endif +#if STM32_HAS_TIM7 /* Priority settings checks.*/ #if !defined(STM32_IRQ_TIM7_PRIORITY) @@ -48,6 +46,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_TIM7_PRIORITY" #endif +#endif /* STM32_HAS_TIM7 */ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim8.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim8.inc index c82e56018..cde3c5beb 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim8.inc +++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim8.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_TIM8 not defined in registry" #endif -#if STM32_HAS_TIM8 == FALSE -#error "TIM8 not present" -#endif +#if STM32_HAS_TIM8 /* Priority settings checks.*/ #if !defined(STM32_IRQ_TIM8_UP_PRIORITY) @@ -56,6 +54,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_TIM8_CC_PRIORITY" #endif +#endif /* STM32_HAS_TIM8 */ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/USARTv2/stm32_lpuart1.inc b/os/hal/ports/STM32/LLD/USARTv2/stm32_lpuart1.inc index df25eabf2..223ce2e12 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/stm32_lpuart1.inc +++ b/os/hal/ports/STM32/LLD/USARTv2/stm32_lpuart1.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_LPUART1 not defined in registry" #endif -#if STM32_HAS_LPUART1 == FALSE -#error "LPUART1 not present" -#endif +#if STM32_HAS_LPUART1 /* Priority settings checks.*/ #if !defined(STM32_IRQ_LPUART1_PRIORITY) @@ -48,6 +46,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_LPUART1_PRIORITY" #endif +#endif /* STM32_HAS_LPUART1 */ + /* Other checks.*/ #if (HAL_USE_SERIAL && STM32_SERIAL_USE_LPUART1) #define STM32_LPUART1_IS_USED TRUE diff --git a/os/hal/ports/STM32/LLD/USARTv2/stm32_uart4.inc b/os/hal/ports/STM32/LLD/USARTv2/stm32_uart4.inc index b602eea68..5dd7b5101 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/stm32_uart4.inc +++ b/os/hal/ports/STM32/LLD/USARTv2/stm32_uart4.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_UART4 not defined in registry" #endif -#if STM32_HAS_UART4 == FALSE -#error "UART4 not present" -#endif +#if STM32_HAS_UART4 /* Priority settings checks.*/ #if !defined(STM32_IRQ_UART4_PRIORITY) @@ -48,6 +46,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_UART4_PRIORITY" #endif +#endif /* STM32_HAS_UART4 */ + /* Other checks.*/ #if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART4) && \ (HAL_USE_UART && STM32_UART_USE_UART4) diff --git a/os/hal/ports/STM32/LLD/USARTv2/stm32_uart5.inc b/os/hal/ports/STM32/LLD/USARTv2/stm32_uart5.inc index a109d1d91..b382d849d 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/stm32_uart5.inc +++ b/os/hal/ports/STM32/LLD/USARTv2/stm32_uart5.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_UART5 not defined in registry" #endif -#if STM32_HAS_UART5 == FALSE -#error "UART5 not present" -#endif +#if STM32_HAS_UART5 /* Priority settings checks.*/ #if !defined(STM32_IRQ_UART5_PRIORITY) @@ -48,6 +46,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_UART5_PRIORITY" #endif +#endif /* STM32_HAS_UART5 */ + /* Other checks.*/ #if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART5) && \ (HAL_USE_UART && STM32_UART_USE_UART5) diff --git a/os/hal/ports/STM32/LLD/USARTv2/stm32_usart1.inc b/os/hal/ports/STM32/LLD/USARTv2/stm32_usart1.inc index affe5917a..19aac1008 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/stm32_usart1.inc +++ b/os/hal/ports/STM32/LLD/USARTv2/stm32_usart1.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_USART1 not defined in registry" #endif -#if STM32_HAS_USART1 == FALSE -#error "USART1 not present" -#endif +#if STM32_HAS_USART1 /* Priority settings checks.*/ #if !defined(STM32_IRQ_USART1_PRIORITY) @@ -48,6 +46,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_USART1_PRIORITY" #endif +#endif /* STM32_HAS_USART1 */ + /* Other checks.*/ #if (HAL_USE_SERIAL && STM32_SERIAL_USE_USART1) && \ (HAL_USE_UART && STM32_UART_USE_USART1) diff --git a/os/hal/ports/STM32/LLD/USARTv2/stm32_usart2.inc b/os/hal/ports/STM32/LLD/USARTv2/stm32_usart2.inc index 17dacef50..c4b900017 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/stm32_usart2.inc +++ b/os/hal/ports/STM32/LLD/USARTv2/stm32_usart2.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_USART2 not defined in registry" #endif -#if STM32_HAS_USART2 == FALSE -#error "USART2 not present" -#endif +#if STM32_HAS_USART2 /* Priority settings checks.*/ #if !defined(STM32_IRQ_USART2_PRIORITY) @@ -48,6 +46,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_USART2_PRIORITY" #endif +#endif /* STM32_HAS_USART2 */ + /* Other checks.*/ #if (HAL_USE_SERIAL && STM32_SERIAL_USE_USART2) && \ (HAL_USE_UART && STM32_UART_USE_USART2) diff --git a/os/hal/ports/STM32/LLD/USARTv2/stm32_usart3.inc b/os/hal/ports/STM32/LLD/USARTv2/stm32_usart3.inc index 71d6423b9..ff5dbda86 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/stm32_usart3.inc +++ b/os/hal/ports/STM32/LLD/USARTv2/stm32_usart3.inc @@ -35,9 +35,7 @@ #error "STM32_HAS_USART3 not defined in registry" #endif -#if STM32_HAS_USART3 == FALSE -#error "USART3 not present" -#endif +#if STM32_HAS_USART3 /* Priority settings checks.*/ #if !defined(STM32_IRQ_USART3_PRIORITY) @@ -48,6 +46,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_USART3_PRIORITY" #endif +#endif /* STM32_HAS_USART3 */ + /* Other checks.*/ #if (HAL_USE_SERIAL && STM32_SERIAL_USE_USART3) && \ (HAL_USE_UART && STM32_UART_USE_USART3) diff --git a/os/hal/ports/STM32/LLD/USARTv2/stm32_usart3_4_lp1.inc b/os/hal/ports/STM32/LLD/USARTv2/stm32_usart3_4_lp1.inc index 793eaaff8..596237fb2 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/stm32_usart3_4_lp1.inc +++ b/os/hal/ports/STM32/LLD/USARTv2/stm32_usart3_4_lp1.inc @@ -43,17 +43,7 @@ #error "STM32_HAS_LPUART1 not defined in registry" #endif -#if STM32_HAS_USART3 == FALSE -#error "USART3 not present" -#endif - -#if STM32_HAS_UART4 == FALSE -#error "USART4 not present" -#endif - -#if STM32_HAS_LPUART1 == FALSE -#error "LPUART1 not present" -#endif +#if STM32_HAS_USART3 || STM32_HAS_UART4 || STM32_HAS_LPUART1 /* Priority settings checks.*/ #if !defined(STM32_IRQ_USART3_4_LP1_PRIORITY) @@ -64,6 +54,8 @@ #error "Invalid IRQ priority assigned to STM32_IRQ_USART3_4_LP1_PRIORITY" #endif +#endif /* STM32_HAS_USART3 || STM32_HAS_UART4 || STM32_HAS_LPUART1 */ + /* Other checks.*/ #if (HAL_USE_SERIAL && STM32_SERIAL_USE_USART3) && \ (HAL_USE_UART && STM32_UART_USE_USART3) diff --git a/os/hal/ports/STM32/LLD/USARTv2/stm32_usart4_5.inc b/os/hal/ports/STM32/LLD/USARTv2/stm32_usart4_5.inc new file mode 100644 index 000000000..7d003a3c6 --- /dev/null +++ b/os/hal/ports/STM32/LLD/USARTv2/stm32_usart4_5.inc @@ -0,0 +1,144 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file USARTv2/stm32_usart4_5.inc + * @brief Shared USART4, USART5 handler. + * + * @addtogroup STM32_USART4_5_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(STM32_HAS_UART4) +#error "STM32_HAS_UART4 not defined in registry" +#endif + +#if !defined(STM32_HAS_UART5) +#error "STM32_HAS_UART5 not defined in registry" +#endif + +#if STM32_HAS_UART4 || STM32_HAS_UART5 + +/* Priority settings checks.*/ +#if !defined(STM32_IRQ_USART4_5_PRIORITY) +#error "STM32_IRQ_USART4_5_PRIORITY not defined in mcuconf.h" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART4_5_PRIORITY) +#error "Invalid IRQ priority assigned to STM32_IRQ_USART4_5_PRIORITY" +#endif + +#endif /* STM32_HAS_UART4 || STM32_HAS_UART5 */ + +/* Other checks.*/ +#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART4) && \ + (HAL_USE_UART && STM32_UART_USE_UART4) +#error "USART4 used by multiple drivers" +#endif + +#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART5) && \ + (HAL_USE_UART && STM32_UART_USE_UART5) +#error "USART5 used by multiple drivers" +#endif + +#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART4) || \ + (HAL_USE_UART && STM32_UART_USE_UART4) +#define STM32_USART4_IS_USED TRUE +#else +#define STM32_USART4_IS_USED FALSE +#endif + +#if (HAL_USE_SERIAL && STM32_SERIAL_USE_UART5) || \ + (HAL_USE_UART && STM32_UART_USE_UART45) +#define STM32_USART5_IS_USED TRUE +#else +#define STM32_USART5_IS_USED FALSE +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void usart4_usart5_irq_init(void) { +#if STM32_USART4_IS_USED || STM32_USART5_IS_USED + nvicEnableVector(STM32_USART4_5_NUMBER, STM32_IRQ_USART4_5_PRIORITY); +#endif +} + +static inline void usart4_usart5_irq_deinit(void) { +#if STM32_USART4_IS_USED || STM32_USART5_IS_USED + nvicDisableVector(STM32_USART4_5_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_USART4_IS_USED || STM32_USART5_IS_USED || \ + defined(__DOXYGEN__) +/** + * @brief USART4, USART5, LPUART1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_USART4_5_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_SERIAL +#if STM32_SERIAL_USE_UART4 + sd_lld_serve_interrupt(&SD4); +#endif +#if STM32_SERIAL_USE_UART5 + sd_lld_serve_interrupt(&SD5); +#endif +#endif +#if HAL_USE_UART +#if STM32_UART_USE_UART4 + uart_lld_serve_interrupt(&UARTD4); +#endif +#if STM32_UART_USE_UART5 + uart_lld_serve_interrupt(&UARTD5); +#endif +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32G0xx/stm32_isr.c b/os/hal/ports/STM32/STM32G0xx/stm32_isr.c index 53a7cbf31..14f0418ba 100644 --- a/os/hal/ports/STM32/STM32G0xx/stm32_isr.c +++ b/os/hal/ports/STM32/STM32G0xx/stm32_isr.c @@ -62,12 +62,8 @@ #include "stm32_usart2.inc" #include "stm32_usart3_4_lp1.inc" -#if STM32_HAS_TIM1 #include "stm32_tim1.inc" -#endif -#if STM32_HAS_TIM2 #include "stm32_tim2.inc" -#endif #include "stm32_tim3.inc" #include "stm32_tim6.inc" #include "stm32_tim7.inc" @@ -91,12 +87,8 @@ void irqInit(void) { exti2_3_irq_init(); exti4_15_irq_init(); -#if STM32_HAS_TIM1 tim1_irq_init(); -#endif -#if STM32_HAS_TIM2 tim2_irq_init(); -#endif tim3_irq_init(); tim6_irq_init(); tim7_irq_init(); @@ -121,12 +113,8 @@ void irqDeinit(void) { exti2_3_irq_deinit(); exti4_15_irq_deinit(); -#if STM32_HAS_TIM1 tim1_irq_deinit(); -#endif -#if STM32_HAS_TIM2 tim2_irq_deinit(); -#endif tim3_irq_deinit(); tim6_irq_deinit(); tim7_irq_deinit(); diff --git a/os/hal/ports/STM32/STM32G4xx/stm32_isr.c b/os/hal/ports/STM32/STM32G4xx/stm32_isr.c index 3b12a36c2..2507bd741 100644 --- a/os/hal/ports/STM32/STM32G4xx/stm32_isr.c +++ b/os/hal/ports/STM32/STM32G4xx/stm32_isr.c @@ -63,24 +63,18 @@ #include "stm32_usart2.inc" #include "stm32_usart3.inc" #include "stm32_uart4.inc" -#if STM32_HAS_UART5 #include "stm32_uart5.inc" -#endif #include "stm32_lpuart1.inc" #include "stm32_tim1_15_16_17.inc" #include "stm32_tim2.inc" #include "stm32_tim3.inc" #include "stm32_tim4.inc" -#if STM32_HAS_TIM5 #include "stm32_tim5.inc" -#endif #include "stm32_tim6.inc" #include "stm32_tim7.inc" #include "stm32_tim8.inc" -#if STM32_HAS_TIM20 #include "stm32_tim20.inc" -#endif /*===========================================================================*/ /* Driver exported functions. */ @@ -105,23 +99,17 @@ void irqInit(void) { tim2_irq_init(); tim3_irq_init(); tim4_irq_init(); -#if STM32_HAS_TIM5 tim5_irq_init(); -#endif tim6_irq_init(); tim7_irq_init(); tim8_irq_init(); -#if STM32_HAS_TIM20 tim20_irq_init(); -#endif usart1_irq_init(); usart2_irq_init(); usart3_irq_init(); uart4_irq_init(); -#if STM32_HAS_UART5 uart5_irq_init(); -#endif lpuart1_irq_init(); } @@ -144,23 +132,17 @@ void irqDeinit(void) { tim2_irq_deinit(); tim3_irq_deinit(); tim4_irq_deinit(); -#if STM32_HAS_TIM5 tim5_irq_deinit(); -#endif tim6_irq_deinit(); tim7_irq_deinit(); tim8_irq_deinit(); -#if STM32_HAS_TIM20 tim20_irq_deinit(); -#endif usart1_irq_deinit(); usart2_irq_deinit(); usart3_irq_deinit(); uart4_irq_deinit(); -#if STM32_HAS_UART5 uart5_irq_deinit(); -#endif lpuart1_irq_deinit(); } diff --git a/os/hal/ports/STM32/STM32L0xx/hal_lld.c b/os/hal/ports/STM32/STM32L0xx/hal_lld.c index 11404bf0f..14b09e169 100644 --- a/os/hal/ports/STM32/STM32L0xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L0xx/hal_lld.c @@ -85,60 +85,6 @@ static void hal_lld_backup_domain_init(void) { /* Driver interrupt handlers. */ /*===========================================================================*/ -#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) -#if defined(STM32_DMA1_CH23_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA1 streams 2 and 3 shared ISR. - * @note It is declared here because this device has a non-standard - * DMA shared IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH23_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - /* Check on channel 2.*/ - dmaServeInterrupt(STM32_DMA1_STREAM2); - - /* Check on channel 3.*/ - dmaServeInterrupt(STM32_DMA1_STREAM3); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* defined(STM32_DMA1_CH23_HANDLER) */ - -#if defined(STM32_DMA1_CH4567_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA1 streams 4, 5, 6 and 7 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH4567_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - /* Check on channel 4.*/ - dmaServeInterrupt(STM32_DMA1_STREAM4); - - /* Check on channel 5.*/ - dmaServeInterrupt(STM32_DMA1_STREAM5); - -#if STM32_DMA1_NUM_CHANNELS > 5 - /* Check on channel 6.*/ - dmaServeInterrupt(STM32_DMA1_STREAM6); -#endif - -#if STM32_DMA1_NUM_CHANNELS > 6 - /* Check on channel 7.*/ - dmaServeInterrupt(STM32_DMA1_STREAM7); -#endif - - OSAL_IRQ_EPILOGUE(); -} -#endif /* defined(STM32_DMA1_CH4567_HANDLER) */ -#endif /* defined(STM32_DMA_REQUIRED) */ - /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_isr.c b/os/hal/ports/STM32/STM32L0xx/stm32_isr.c index 0aa502727..aad602daf 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_isr.c +++ b/os/hal/ports/STM32/STM32L0xx/stm32_isr.c @@ -28,6 +28,13 @@ /* Driver local definitions. */ /*===========================================================================*/ +#define exti_serve_irq(pr, channel) { \ + \ + if ((pr) & (1U << (channel))) { \ + _pal_isr_code(channel); \ + } \ +} + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -40,197 +47,28 @@ /* Driver local functions. */ /*===========================================================================*/ -#define exti_serve_irq(pr, channel) { \ - \ - if ((pr) & (1U << (channel))) { \ - _pal_isr_code(channel); \ - } \ -} - /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ -#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__) -#if !defined(STM32_DISABLE_EXTI0_1_HANDLER) -/** - * @brief EXTI[0]...EXTI[1] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector54) { - uint32_t pr; +#include "stm32_dma1_ch23.inc" +#include "stm32_dma1_ch4567.inc" - OSAL_IRQ_PROLOGUE(); +#include "stm32_exti0_1.inc" +#include "stm32_exti2_3.inc" +#include "stm32_exti4_15.inc" - pr = EXTI->PR; - pr &= ((1U << 0) | (1U << 1)); - EXTI->PR = pr; +#include "stm32_usart1.inc" +#include "stm32_usart2.inc" +#include "stm32_usart4_5.inc" +#include "stm32_lpuart1.inc" - exti_serve_irq(pr, 0); - exti_serve_irq(pr, 1); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/** - * @brief EXTI[2]...EXTI[3] interrupt handler. - * - * @isr - */ -#if !defined(STM32_DISABLE_EXTI2_3_HANDLER) -OSAL_IRQ_HANDLER(Vector58) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= ((1U << 2) | (1U << 3)); - EXTI->PR = pr; - - exti_serve_irq(pr, 2); - exti_serve_irq(pr, 3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI4_15_HANDLER) -/** - * @brief EXTI[4]...EXTI[15] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector5C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= ((1U << 4) | (1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | - (1U << 9) | (1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | - (1U << 14) | (1U << 15)); - EXTI->PR = pr; - - exti_serve_irq(pr, 4); - exti_serve_irq(pr, 5); - exti_serve_irq(pr, 6); - exti_serve_irq(pr, 7); - exti_serve_irq(pr, 8); - exti_serve_irq(pr, 9); - exti_serve_irq(pr, 10); - exti_serve_irq(pr, 11); - exti_serve_irq(pr, 12); - exti_serve_irq(pr, 13); - exti_serve_irq(pr, 14); - exti_serve_irq(pr, 15); - - OSAL_IRQ_EPILOGUE(); -} -#endif -#endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */ - -#if HAL_USE_SERIAL || HAL_USE_UART || defined(__DOXYGEN__) -#if !defined(STM32_DISABLE_USART1_HANDLER) -/** - * @brief USART1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - -#if HAL_USE_SERIAL -#if STM32_SERIAL_USE_USART1 - sd_lld_serve_interrupt(&SD1); -#endif -#endif -#if HAL_USE_UART -#if STM32_UART_USE_USART1 - uart_lld_serve_interrupt(&UARTD1); -#endif -#endif - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_USART2_HANDLER) -/** - * @brief USART2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - -#if HAL_USE_SERIAL -#if STM32_SERIAL_USE_USART2 - sd_lld_serve_interrupt(&SD2); -#endif -#endif -#if HAL_USE_UART -#if STM32_UART_USE_USART2 - uart_lld_serve_interrupt(&UARTD2); -#endif -#endif - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_UART4_5_HANDLER) -/** - * @brief UART4 and 5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_UART4_5_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - -#if HAL_USE_SERIAL -#if STM32_SERIAL_USE_UART4 - sd_lld_serve_interrupt(&SD4); -#endif -#if STM32_SERIAL_USE_UART5 - sd_lld_serve_interrupt(&SD5); -#endif -#endif -#if HAL_USE_UART -#if STM32_UART_USE_UART4 - uart_lld_serve_interrupt(&UARTD4); -#endif -#if STM32_UART_USE_UART5 - uart_lld_serve_interrupt(&UARTD5); -#endif -#endif - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_LPUART1_HANDLER) -/** - * @brief LPUART1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_LPUART1_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - -#if STM32_SERIAL_USE_LPUART1 - sd_lld_serve_interrupt(&LPSD1); -#endif - - OSAL_IRQ_EPILOGUE(); -} -#endif -#endif /* HAL_USE_SERIAL || HAL_USE_UART */ +#include "stm32_tim2.inc" +#include "stm32_tim3.inc" +#include "stm32_tim6.inc" +#include "stm32_tim7.inc" +#include "stm32_tim21.inc" +#include "stm32_tim22.inc" /*===========================================================================*/ /* Driver exported functions. */ @@ -243,18 +81,20 @@ OSAL_IRQ_HANDLER(STM32_LPUART1_HANDLER) { */ void irqInit(void) { -#if HAL_USE_PAL - nvicEnableVector(STM32_EXTI_LINE01_NUMBER, STM32_IRQ_EXTI0_1_PRIORITY); - nvicEnableVector(STM32_EXTI_LINE23_NUMBER, STM32_IRQ_EXTI2_3_PRIORITY); - nvicEnableVector(STM32_EXTI_LINE4_15_NUMBER, STM32_IRQ_EXTI4_15_PRIORITY); -#endif + exti0_1_irq_init(); + exti2_3_irq_init(); + exti4_15_irq_init(); -#if HAL_USE_SERIAL || HAL_USE_UART - nvicEnableVector(STM32_USART1_NUMBER, STM32_IRQ_USART1_PRIORITY); - nvicEnableVector(STM32_USART2_NUMBER, STM32_IRQ_USART2_PRIORITY); - nvicEnableVector(STM32_UART4_5_NUMBER, STM32_IRQ_UART4_5_PRIORITY); - nvicEnableVector(STM32_LPUART1_NUMBER, STM32_IRQ_LPUART1_PRIORITY); -#endif + tim2_irq_init(); + tim3_irq_init(); + tim6_irq_init(); + tim7_irq_init(); + tim21_irq_init(); + tim22_irq_init(); + + usart1_irq_init(); + usart2_irq_init(); + usart4_usart5_irq_init(); } /** @@ -264,18 +104,20 @@ void irqInit(void) { */ void irqDeinit(void) { -#if HAL_USE_PAL - nvicDisableVector(STM32_EXTI_LINE01_NUMBER); - nvicDisableVector(STM32_EXTI_LINE23_NUMBER); - nvicDisableVector(STM32_EXTI_LINE4_15_NUMBER); -#endif + exti0_1_irq_deinit(); + exti2_3_irq_deinit(); + exti4_15_irq_deinit(); -#if HAL_USE_SERIAL || HAL_USE_UART - nvicDisableVector(STM32_USART1_NUMBER); - nvicDisableVector(STM32_USART2_NUMBER); - nvicDisableVector(STM32_UART4_5_NUMBER); - nvicDisableVector(STM32_LPUART1_NUMBER); -#endif + tim2_irq_deinit(); + tim3_irq_deinit(); + tim6_irq_deinit(); + tim7_irq_deinit(); + tim21_irq_deinit(); + tim22_irq_deinit(); + + usart1_irq_deinit(); + usart2_irq_deinit(); + usart4_usart5_irq_deinit(); } /** @} */ diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_isr.h b/os/hal/ports/STM32/STM32L0xx/stm32_isr.h index 4d445c973..841b58dd0 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_isr.h @@ -44,6 +44,35 @@ * @name ISR names and numbers remapping * @{ */ +/* + * ADC unit. + */ +#define STM32_ADC1_HANDLER Vector70 +#define STM32_ADC1_NUMBER 12 + +/* + * DMA unit. + */ +#define STM32_DMA1_CH1_HANDLER Vector64 +#define STM32_DMA1_CH23_HANDLER Vector68 +#define STM32_DMA1_CH4567_HANDLER Vector6C +#define STM32_DMA1_CH1_NUMBER 9 +#define STM32_DMA1_CH23_NUMBER 10 +#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER +#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER +#define STM32_DMA1_CH4567_NUMBER 11 +#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER +#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER +#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER +#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER + +#define STM32_DMA1_CH2_CMASK 0x00000006U +#define STM32_DMA1_CH3_CMASK 0x00000006U +#define STM32_DMA1_CH4_CMASK 0x00000078U +#define STM32_DMA1_CH5_CMASK 0x00000078U +#define STM32_DMA1_CH6_CMASK 0x00000078U +#define STM32_DMA1_CH7_CMASK 0x00000078U + /* * EXTI unit. */ @@ -61,6 +90,34 @@ #define STM32_EXTI_LINE171920_NUMBER 2 #define STM32_EXTI_LINE2122_NUMBER 12 +/* + * I2C units. + */ +#define STM32_I2C1_GLOBAL_HANDLER Vector9C +#define STM32_I2C2_GLOBAL_HANDLER VectorA0 +#define STM32_I2C3_GLOBAL_HANDLER Vector94 + +#define STM32_I2C1_GLOBAL_NUMBER 23 +#define STM32_I2C2_GLOBAL_NUMBER 24 +#define STM32_I2C3_GLOBAL_NUMBER 21 + +/* + * TIM units. + */ +#define STM32_TIM2_HANDLER Vector7C +#define STM32_TIM3_HANDLER Vector80 +#define STM32_TIM6_HANDLER Vector84 +#define STM32_TIM7_HANDLER Vector88 +#define STM32_TIM21_HANDLER Vector90 +#define STM32_TIM22_HANDLER Vector98 + +#define STM32_TIM2_NUMBER 15 +#define STM32_TIM3_NUMBER 16 +#define STM32_TIM6_NUMBER 17 +#define STM32_TIM7_NUMBER 18 +#define STM32_TIM21_NUMBER 20 +#define STM32_TIM22_NUMBER 22 + /* * USART/UART units. */ @@ -68,136 +125,30 @@ #define STM32_USART2_HANDLER VectorB0 #define STM32_UART4_5_HANDLER Vector78 #define STM32_LPUART1_HANDLER VectorB4 + #define STM32_USART1_NUMBER 27 #define STM32_USART2_NUMBER 28 #define STM32_UART4_5_NUMBER 14 #define STM32_LPUART1_NUMBER 29 + +/* + * USB units. + */ +#define STM32_USB1_LP_HANDLER VectorBC +#define STM32_USB1_HP_HANDLER VectorBC + +#define STM32_USB1_LP_NUMBER 31 +#define STM32_USB1_HP_NUMBER 31 /** @} */ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ -/** - * @name Configuration options - * @{ - */ -/** - * @brief EXTI0..1 interrupt priority level setting. - */ -#if !defined(STM32_IRQ_EXTI0_1_PRIORITY) || defined(__DOXYGEN__) -#define STM32_IRQ_EXTI0_1_PRIORITY 3 -#endif - -/** - * @brief EXTI2..3 interrupt priority level setting. - */ -#if !defined(STM32_IRQ_EXTI2_3_PRIORITY) || defined(__DOXYGEN__) -#define STM32_IRQ_EXTI2_3_PRIORITY 3 -#endif - -/** - * @brief EXTI4..15 interrupt priority level setting. - */ -#if !defined(STM32_IRQ_EXTI4_15_PRIORITY) || defined(__DOXYGEN__) -#define STM32_IRQ_EXTI4_15_PRIORITY 3 -#endif - -/** - * @brief EXTI16 (PVD) interrupt priority level setting. - */ -#if !defined(STM32_IRQ_EXTI16_PRIORITY) || defined(__DOXYGEN__) -#define STM32_IRQ_EXTI16_PRIORITY 3 -#endif - -/** - * @brief EXTI17,19,20 interrupt priority level setting. - */ -#if !defined(STM32_IRQ_EXTI17_20_PRIORITY) || defined(__DOXYGEN__) -#define STM32_IRQ_EXTI17_20_PRIORITY 3 -#endif - -/** - * @brief EXTI21,22 interrupt priority level setting. - */ -#if !defined(STM32_IRQ_EXTI21_22_PRIORITY) || defined(__DOXYGEN__) -#define STM32_IRQ_EXTI21_22_PRIORITY 3 -#endif - -/** - * @brief USART1 interrupt priority level setting. - */ -#if !defined(STM32_IRQ_USART1_PRIORITY) || defined(__DOXYGEN__) -#define STM32_IRQ_USART1_PRIORITY 3 -#endif - -/** - * @brief USART2 interrupt priority level setting. - */ -#if !defined(STM32_IRQ_USART2_PRIORITY) || defined(__DOXYGEN__) -#define STM32_IRQ_USART2_PRIORITY 3 -#endif - -/** - * @brief UART4 and 5 interrupt priority level setting. - */ -#if !defined(STM32_IRQ_UART4_5_PRIORITY) || defined(__DOXYGEN__) -#define STM32_IRQ_UART4_5_PRIORITY 3 -#endif - -/** - * @brief LPUART1 interrupt priority level setting. - */ -#if !defined(STM32_IRQ_LPUART1_PRIORITY) || defined(__DOXYGEN__) -#define STM32_IRQ_LPUART1_PRIORITY 3 -#endif -/** @} */ - /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ -/* IRQ priority checks.*/ -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI0_1_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI0_1_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI2_3_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI2_3_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI4_15_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI4_15_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI16_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI16_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI17_20_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI17_20_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI21_22_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI21_22_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART1_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_USART1_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART2_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_USART2_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_UART4_5_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_UART4_5_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_LPUART1_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_LPUART1_PRIORITY" -#endif - /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h index 73bc85ae4..82cf0f583 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h @@ -64,8 +64,6 @@ #define STM32_HAS_ADC1 TRUE #define STM32_ADC_SUPPORTS_PRESCALER TRUE #define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE -#define STM32_ADC1_HANDLER Vector70 -#define STM32_ADC1_NUMBER 12 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ STM32_DMA_STREAM_ID_MSK(1, 2)) #define STM32_ADC1_DMA_CHN 0x00000000 @@ -91,26 +89,6 @@ #define STM32_DMA_SUPPORTS_CSELR TRUE #define STM32_DMA1_NUM_CHANNELS 5 #define STM32_DMA2_NUM_CHANNELS 0 -#define STM32_DMA1_CH1_HANDLER Vector64 -#define STM32_DMA1_CH23_HANDLER Vector68 -#define STM32_DMA1_CH4567_HANDLER Vector6C -#define STM32_DMA1_CH1_NUMBER 9 -#define STM32_DMA1_CH23_NUMBER 10 -#define STM32_DMA1_CH4567_NUMBER 11 - -#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER -#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER -#define STM32_DMA1_CH2_CMASK 0x00000006U -#define STM32_DMA1_CH3_CMASK 0x00000006U - -#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH4_CMASK 0x00000078U -#define STM32_DMA1_CH5_CMASK 0x00000078U -#define STM32_DMA1_CH6_CMASK 0x00000078U -#define STM32_DMA1_CH7_CMASK 0x00000078U /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -137,8 +115,6 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_GLOBAL_HANDLER Vector9C -#define STM32_I2C1_GLOBAL_NUMBER 23 #define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ STM32_DMA_STREAM_ID_MSK(1, 7)) #define STM32_I2C1_RX_DMA_CHN 0x06000600 @@ -176,14 +152,10 @@ #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS FALSE #define STM32_TIM2_CHANNELS 4 -#define STM32_TIM2_HANDLER Vector7C -#define STM32_TIM2_NUMBER 15 #define STM32_HAS_TIM21 TRUE #define STM32_TIM21_IS_32BITS FALSE #define STM32_TIM21_CHANNELS 2 -#define STM32_TIM21_HANDLER Vector90 -#define STM32_TIM21_NUMBER 20 #define STM32_HAS_TIM1 FALSE #define STM32_HAS_TIM3 FALSE @@ -256,8 +228,6 @@ #define STM32_HAS_ADC1 TRUE #define STM32_ADC_SUPPORTS_PRESCALER TRUE #define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE -#define STM32_ADC1_HANDLER Vector70 -#define STM32_ADC1_NUMBER 12 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ STM32_DMA_STREAM_ID_MSK(1, 2)) #define STM32_ADC1_DMA_CHN 0x00000000 @@ -283,26 +253,6 @@ #define STM32_DMA_SUPPORTS_CSELR TRUE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA2_NUM_CHANNELS 0 -#define STM32_DMA1_CH1_HANDLER Vector64 -#define STM32_DMA1_CH23_HANDLER Vector68 -#define STM32_DMA1_CH4567_HANDLER Vector6C -#define STM32_DMA1_CH1_NUMBER 9 -#define STM32_DMA1_CH23_NUMBER 10 -#define STM32_DMA1_CH4567_NUMBER 11 - -#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER -#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER -#define STM32_DMA1_CH2_CMASK 0x00000006U -#define STM32_DMA1_CH3_CMASK 0x00000006U - -#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH4_CMASK 0x00000078U -#define STM32_DMA1_CH5_CMASK 0x00000078U -#define STM32_DMA1_CH6_CMASK 0x00000078U -#define STM32_DMA1_CH7_CMASK 0x00000078U /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -330,8 +280,6 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_GLOBAL_HANDLER Vector9C -#define STM32_I2C1_GLOBAL_NUMBER 23 #define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ STM32_DMA_STREAM_ID_MSK(1, 7)) #define STM32_I2C1_RX_DMA_CHN 0x06000600 @@ -366,20 +314,14 @@ #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS FALSE #define STM32_TIM2_CHANNELS 4 -#define STM32_TIM2_HANDLER Vector7C -#define STM32_TIM2_NUMBER 15 #define STM32_HAS_TIM21 TRUE #define STM32_TIM21_IS_32BITS FALSE #define STM32_TIM21_CHANNELS 2 -#define STM32_TIM21_HANDLER Vector90 -#define STM32_TIM21_NUMBER 20 #define STM32_HAS_TIM22 TRUE #define STM32_TIM22_IS_32BITS FALSE #define STM32_TIM22_CHANNELS 2 -#define STM32_TIM22_HANDLER Vector98 -#define STM32_TIM22_NUMBER 22 #define STM32_HAS_TIM1 FALSE #define STM32_HAS_TIM3 FALSE @@ -451,8 +393,6 @@ #define STM32_HAS_ADC1 TRUE #define STM32_ADC_SUPPORTS_PRESCALER TRUE #define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE -#define STM32_ADC1_HANDLER Vector70 -#define STM32_ADC1_NUMBER 12 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ STM32_DMA_STREAM_ID_MSK(1, 2)) #define STM32_ADC1_DMA_CHN 0x00000000 @@ -478,26 +418,6 @@ #define STM32_DMA_SUPPORTS_CSELR TRUE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA2_NUM_CHANNELS 0 -#define STM32_DMA1_CH1_HANDLER Vector64 -#define STM32_DMA1_CH23_HANDLER Vector68 -#define STM32_DMA1_CH4567_HANDLER Vector6C -#define STM32_DMA1_CH1_NUMBER 9 -#define STM32_DMA1_CH23_NUMBER 10 -#define STM32_DMA1_CH4567_NUMBER 11 - -#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER -#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER -#define STM32_DMA1_CH2_CMASK 0x00000006U -#define STM32_DMA1_CH3_CMASK 0x00000006U - -#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH4_CMASK 0x00000078U -#define STM32_DMA1_CH5_CMASK 0x00000078U -#define STM32_DMA1_CH6_CMASK 0x00000078U -#define STM32_DMA1_CH7_CMASK 0x00000078U /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -526,8 +446,6 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_GLOBAL_HANDLER Vector9C -#define STM32_I2C1_GLOBAL_NUMBER 23 #define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ STM32_DMA_STREAM_ID_MSK(1, 7)) #define STM32_I2C1_RX_DMA_CHN 0x06000600 @@ -536,8 +454,6 @@ #define STM32_I2C1_TX_DMA_CHN 0x00600060 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_GLOBAL_HANDLER VectorA0 -#define STM32_I2C2_GLOBAL_NUMBER 24 #define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) #define STM32_I2C2_RX_DMA_CHN 0x00070000 #define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) @@ -578,26 +494,18 @@ #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS FALSE #define STM32_TIM2_CHANNELS 4 -#define STM32_TIM2_HANDLER Vector7C -#define STM32_TIM2_NUMBER 15 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 -#define STM32_TIM6_HANDLER Vector84 -#define STM32_TIM6_NUMBER 17 #define STM32_HAS_TIM21 TRUE #define STM32_TIM21_IS_32BITS FALSE #define STM32_TIM21_CHANNELS 2 -#define STM32_TIM21_HANDLER Vector90 -#define STM32_TIM21_NUMBER 20 #define STM32_HAS_TIM22 TRUE #define STM32_TIM22_IS_32BITS FALSE #define STM32_TIM22_CHANNELS 2 -#define STM32_TIM22_HANDLER Vector98 -#define STM32_TIM22_NUMBER 22 #define STM32_HAS_TIM1 FALSE #define STM32_HAS_TIM3 FALSE @@ -677,8 +585,6 @@ #define STM32_HAS_ADC1 TRUE #define STM32_ADC_SUPPORTS_PRESCALER TRUE #define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE -#define STM32_ADC1_HANDLER Vector70 -#define STM32_ADC1_NUMBER 12 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ STM32_DMA_STREAM_ID_MSK(1, 2)) #define STM32_ADC1_DMA_CHN 0x00000000 @@ -707,26 +613,6 @@ #define STM32_DMA_SUPPORTS_CSELR TRUE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA2_NUM_CHANNELS 0 -#define STM32_DMA1_CH1_HANDLER Vector64 -#define STM32_DMA1_CH23_HANDLER Vector68 -#define STM32_DMA1_CH4567_HANDLER Vector6C -#define STM32_DMA1_CH1_NUMBER 9 -#define STM32_DMA1_CH23_NUMBER 10 -#define STM32_DMA1_CH4567_NUMBER 11 - -#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER -#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER -#define STM32_DMA1_CH2_CMASK 0x00000006U -#define STM32_DMA1_CH3_CMASK 0x00000006U - -#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH4_CMASK 0x00000078U -#define STM32_DMA1_CH5_CMASK 0x00000078U -#define STM32_DMA1_CH6_CMASK 0x00000078U -#define STM32_DMA1_CH7_CMASK 0x00000078U /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -755,8 +641,6 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_GLOBAL_HANDLER Vector9C -#define STM32_I2C1_GLOBAL_NUMBER 23 #define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ STM32_DMA_STREAM_ID_MSK(1, 7)) #define STM32_I2C1_RX_DMA_CHN 0x06000600 @@ -765,8 +649,6 @@ #define STM32_I2C1_TX_DMA_CHN 0x00600060 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_GLOBAL_HANDLER VectorA0 -#define STM32_I2C2_GLOBAL_NUMBER 24 #define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) #define STM32_I2C2_RX_DMA_CHN 0x00070000 #define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) @@ -803,26 +685,18 @@ #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS FALSE #define STM32_TIM2_CHANNELS 4 -#define STM32_TIM2_HANDLER Vector7C -#define STM32_TIM2_NUMBER 15 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 -#define STM32_TIM6_HANDLER Vector84 -#define STM32_TIM6_NUMBER 17 #define STM32_HAS_TIM21 TRUE #define STM32_TIM21_IS_32BITS FALSE #define STM32_TIM21_CHANNELS 2 -#define STM32_TIM21_HANDLER Vector90 -#define STM32_TIM21_NUMBER 20 #define STM32_HAS_TIM22 TRUE #define STM32_TIM22_IS_32BITS FALSE #define STM32_TIM22_CHANNELS 2 -#define STM32_TIM22_HANDLER Vector98 -#define STM32_TIM22_NUMBER 22 #define STM32_HAS_TIM1 FALSE #define STM32_HAS_TIM3 FALSE @@ -874,10 +748,6 @@ #define STM32_USB_ACCESS_SCHEME_2x16 TRUE #define STM32_USB_PMA_SIZE 1024 #define STM32_USB_HAS_BCDR TRUE -#define STM32_USB1_LP_HANDLER VectorBC -#define STM32_USB1_LP_NUMBER 31 -#define STM32_USB1_HP_HANDLER VectorBC -#define STM32_USB1_HP_NUMBER 31 #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE @@ -908,8 +778,6 @@ #define STM32_HAS_ADC1 TRUE #define STM32_ADC_SUPPORTS_PRESCALER TRUE #define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE -#define STM32_ADC1_HANDLER Vector70 -#define STM32_ADC1_NUMBER 12 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ STM32_DMA_STREAM_ID_MSK(1, 2)) #define STM32_ADC1_DMA_CHN 0x00000000 @@ -940,26 +808,6 @@ #define STM32_DMA_SUPPORTS_CSELR TRUE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA2_NUM_CHANNELS 0 -#define STM32_DMA1_CH1_HANDLER Vector64 -#define STM32_DMA1_CH23_HANDLER Vector68 -#define STM32_DMA1_CH4567_HANDLER Vector6C -#define STM32_DMA1_CH1_NUMBER 9 -#define STM32_DMA1_CH23_NUMBER 10 -#define STM32_DMA1_CH4567_NUMBER 11 - -#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER -#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER -#define STM32_DMA1_CH2_CMASK 0x00000006U -#define STM32_DMA1_CH3_CMASK 0x00000006U - -#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH4_CMASK 0x00000078U -#define STM32_DMA1_CH5_CMASK 0x00000078U -#define STM32_DMA1_CH6_CMASK 0x00000078U -#define STM32_DMA1_CH7_CMASK 0x00000078U /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -989,8 +837,6 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_GLOBAL_HANDLER Vector9C -#define STM32_I2C1_GLOBAL_NUMBER 23 #define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ STM32_DMA_STREAM_ID_MSK(1, 7)) #define STM32_I2C1_RX_DMA_CHN 0x06000600 @@ -999,16 +845,12 @@ #define STM32_I2C1_TX_DMA_CHN 0x00600060 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_GLOBAL_HANDLER VectorA0 -#define STM32_I2C2_GLOBAL_NUMBER 24 #define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) #define STM32_I2C2_RX_DMA_CHN 0x00070000 #define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) #define STM32_I2C2_TX_DMA_CHN 0x00007000 #define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_GLOBAL_HANDLER Vector94 -#define STM32_I2C3_GLOBAL_NUMBER 21 #define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ STM32_DMA_STREAM_ID_MSK(1, 5)) #define STM32_I2C3_RX_DMA_CHN 0x00E0E000 @@ -1045,38 +887,26 @@ #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS FALSE #define STM32_TIM2_CHANNELS 4 -#define STM32_TIM2_HANDLER Vector7C -#define STM32_TIM2_NUMBER 15 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 -#define STM32_TIM3_HANDLER Vector80 -#define STM32_TIM3_NUMBER 16 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 -#define STM32_TIM6_HANDLER Vector84 -#define STM32_TIM6_NUMBER 17 #define STM32_HAS_TIM7 TRUE #define STM32_TIM7_IS_32BITS FALSE #define STM32_TIM7_CHANNELS 0 -#define STM32_TIM7_HANDLER Vector88 -#define STM32_TIM7_NUMBER 18 #define STM32_HAS_TIM21 TRUE #define STM32_TIM21_IS_32BITS FALSE #define STM32_TIM21_CHANNELS 2 -#define STM32_TIM21_HANDLER Vector90 -#define STM32_TIM21_NUMBER 20 #define STM32_HAS_TIM22 TRUE #define STM32_TIM22_IS_32BITS FALSE #define STM32_TIM22_CHANNELS 2 -#define STM32_TIM22_HANDLER Vector98 -#define STM32_TIM22_NUMBER 22 #define STM32_HAS_TIM1 FALSE #define STM32_HAS_TIM4 FALSE @@ -1166,8 +996,6 @@ #define STM32_HAS_ADC1 TRUE #define STM32_ADC_SUPPORTS_PRESCALER TRUE #define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE -#define STM32_ADC1_HANDLER Vector70 -#define STM32_ADC1_NUMBER 12 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ STM32_DMA_STREAM_ID_MSK(1, 2)) #define STM32_ADC1_DMA_CHN 0x00000000 @@ -1198,26 +1026,6 @@ #define STM32_DMA_SUPPORTS_CSELR TRUE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA2_NUM_CHANNELS 0 -#define STM32_DMA1_CH1_HANDLER Vector64 -#define STM32_DMA1_CH23_HANDLER Vector68 -#define STM32_DMA1_CH4567_HANDLER Vector6C -#define STM32_DMA1_CH1_NUMBER 9 -#define STM32_DMA1_CH23_NUMBER 10 -#define STM32_DMA1_CH4567_NUMBER 11 - -#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER -#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER -#define STM32_DMA1_CH2_CMASK 0x00000006U -#define STM32_DMA1_CH3_CMASK 0x00000006U - -#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER -#define STM32_DMA1_CH4_CMASK 0x00000078U -#define STM32_DMA1_CH5_CMASK 0x00000078U -#define STM32_DMA1_CH6_CMASK 0x00000078U -#define STM32_DMA1_CH7_CMASK 0x00000078U /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -1247,8 +1055,6 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_GLOBAL_HANDLER Vector9C -#define STM32_I2C1_GLOBAL_NUMBER 23 #define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ STM32_DMA_STREAM_ID_MSK(1, 7)) #define STM32_I2C1_RX_DMA_CHN 0x06000600 @@ -1257,16 +1063,12 @@ #define STM32_I2C1_TX_DMA_CHN 0x00600060 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_GLOBAL_HANDLER VectorA0 -#define STM32_I2C2_GLOBAL_NUMBER 24 #define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) #define STM32_I2C2_RX_DMA_CHN 0x00070000 #define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) #define STM32_I2C2_TX_DMA_CHN 0x00007000 #define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_GLOBAL_HANDLER Vector94 -#define STM32_I2C3_GLOBAL_NUMBER 21 #define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ STM32_DMA_STREAM_ID_MSK(1, 5)) #define STM32_I2C3_RX_DMA_CHN 0x00E0E000 @@ -1303,38 +1105,26 @@ #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS FALSE #define STM32_TIM2_CHANNELS 4 -#define STM32_TIM2_HANDLER Vector7C -#define STM32_TIM2_NUMBER 15 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 -#define STM32_TIM3_HANDLER Vector80 -#define STM32_TIM3_NUMBER 16 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 -#define STM32_TIM6_HANDLER Vector84 -#define STM32_TIM6_NUMBER 17 #define STM32_HAS_TIM7 TRUE #define STM32_TIM7_IS_32BITS FALSE #define STM32_TIM7_CHANNELS 0 -#define STM32_TIM7_HANDLER Vector88 -#define STM32_TIM7_NUMBER 18 #define STM32_HAS_TIM21 TRUE #define STM32_TIM21_IS_32BITS FALSE #define STM32_TIM21_CHANNELS 2 -#define STM32_TIM21_HANDLER Vector90 -#define STM32_TIM21_NUMBER 20 #define STM32_HAS_TIM22 TRUE #define STM32_TIM22_IS_32BITS FALSE #define STM32_TIM22_CHANNELS 2 -#define STM32_TIM22_HANDLER Vector98 -#define STM32_TIM22_NUMBER 22 #define STM32_HAS_TIM1 FALSE #define STM32_HAS_TIM4 FALSE @@ -1398,10 +1188,6 @@ #define STM32_USB_ACCESS_SCHEME_2x16 TRUE #define STM32_USB_PMA_SIZE 1024 #define STM32_USB_HAS_BCDR TRUE -#define STM32_USB1_LP_HANDLER VectorBC -#define STM32_USB1_LP_NUMBER 31 -#define STM32_USB1_HP_HANDLER VectorBC -#define STM32_USB1_HP_NUMBER 31 #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE diff --git a/testhal/STM32/STM32L0xx/ADC/mcuconf.h b/testhal/STM32/STM32L0xx/ADC/mcuconf.h index 3af69d2c3..2c74f3b1e 100644 --- a/testhal/STM32/STM32L0xx/ADC/mcuconf.h +++ b/testhal/STM32/STM32L0xx/ADC/mcuconf.h @@ -83,10 +83,16 @@ #define STM32_IRQ_EXTI16_PRIORITY 3 #define STM32_IRQ_EXTI17_20_PRIORITY 3 #define STM32_IRQ_EXTI21_22_PRIORITY 3 + #define STM32_IRQ_USART1_PRIORITY 3 #define STM32_IRQ_USART2_PRIORITY 3 #define STM32_IRQ_LPUART1_PRIORITY 3 +#define STM32_IRQ_TIM2_PRIORITY 1 +#define STM32_IRQ_TIM6_PRIORITY 1 +#define STM32_IRQ_TIM21_PRIORITY 1 +#define STM32_IRQ_TIM22_PRIORITY 1 + /* * ADC driver system settings. * Note, IRQ is shared with EXT channels 21 and 22. @@ -113,10 +119,6 @@ #define STM32_GPT_USE_TIM6 FALSE #define STM32_GPT_USE_TIM21 FALSE #define STM32_GPT_USE_TIM22 FALSE -#define STM32_GPT_TIM2_IRQ_PRIORITY 2 -#define STM32_GPT_TIM6_IRQ_PRIORITY 2 -#define STM32_GPT_TIM21_IRQ_PRIORITY 2 -#define STM32_GPT_TIM22_IRQ_PRIORITY 2 /* * I2C driver system settings. @@ -141,9 +143,6 @@ #define STM32_ICU_USE_TIM2 FALSE #define STM32_ICU_USE_TIM21 FALSE #define STM32_ICU_USE_TIM22 FALSE -#define STM32_ICU_TIM2_IRQ_PRIORITY 3 -#define STM32_ICU_TIM21_IRQ_PRIORITY 3 -#define STM32_ICU_TIM22_IRQ_PRIORITY 3 /* * PWM driver system settings. @@ -151,9 +150,6 @@ #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM21 FALSE #define STM32_PWM_USE_TIM22 FALSE -#define STM32_PWM_TIM2_IRQ_PRIORITY 3 -#define STM32_PWM_TIM21_IRQ_PRIORITY 3 -#define STM32_PWM_TIM22_IRQ_PRIORITY 3 /* * SERIAL driver system settings. @@ -195,6 +191,8 @@ #define STM32_UART_USE_USART2 FALSE #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) diff --git a/testhal/STM32/STM32L0xx/SPI/mcuconf.h b/testhal/STM32/STM32L0xx/SPI/mcuconf.h index cccf0bd8a..0db03caa8 100644 --- a/testhal/STM32/STM32L0xx/SPI/mcuconf.h +++ b/testhal/STM32/STM32L0xx/SPI/mcuconf.h @@ -83,10 +83,16 @@ #define STM32_IRQ_EXTI16_PRIORITY 3 #define STM32_IRQ_EXTI17_20_PRIORITY 3 #define STM32_IRQ_EXTI21_22_PRIORITY 3 + #define STM32_IRQ_USART1_PRIORITY 3 #define STM32_IRQ_USART2_PRIORITY 3 #define STM32_IRQ_LPUART1_PRIORITY 3 +#define STM32_IRQ_TIM2_PRIORITY 1 +#define STM32_IRQ_TIM6_PRIORITY 1 +#define STM32_IRQ_TIM21_PRIORITY 1 +#define STM32_IRQ_TIM22_PRIORITY 1 + /* * ADC driver system settings. * Note, IRQ is shared with EXT channels 21 and 22. @@ -113,10 +119,6 @@ #define STM32_GPT_USE_TIM6 FALSE #define STM32_GPT_USE_TIM21 FALSE #define STM32_GPT_USE_TIM22 FALSE -#define STM32_GPT_TIM2_IRQ_PRIORITY 2 -#define STM32_GPT_TIM6_IRQ_PRIORITY 2 -#define STM32_GPT_TIM21_IRQ_PRIORITY 2 -#define STM32_GPT_TIM22_IRQ_PRIORITY 2 /* * I2C driver system settings. @@ -141,9 +143,6 @@ #define STM32_ICU_USE_TIM2 FALSE #define STM32_ICU_USE_TIM21 FALSE #define STM32_ICU_USE_TIM22 FALSE -#define STM32_ICU_TIM2_IRQ_PRIORITY 3 -#define STM32_ICU_TIM21_IRQ_PRIORITY 3 -#define STM32_ICU_TIM22_IRQ_PRIORITY 3 /* * PWM driver system settings. @@ -151,9 +150,6 @@ #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM21 FALSE #define STM32_PWM_USE_TIM22 FALSE -#define STM32_PWM_TIM2_IRQ_PRIORITY 3 -#define STM32_PWM_TIM21_IRQ_PRIORITY 3 -#define STM32_PWM_TIM22_IRQ_PRIORITY 3 /* * SERIAL driver system settings. @@ -195,6 +191,8 @@ #define STM32_UART_USE_USART2 FALSE #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) diff --git a/testhal/STM32/STM32L0xx/USB_CDC/mcuconf.h b/testhal/STM32/STM32L0xx/USB_CDC/mcuconf.h index 075ef55db..9d829defc 100644 --- a/testhal/STM32/STM32L0xx/USB_CDC/mcuconf.h +++ b/testhal/STM32/STM32L0xx/USB_CDC/mcuconf.h @@ -83,10 +83,16 @@ #define STM32_IRQ_EXTI16_PRIORITY 3 #define STM32_IRQ_EXTI17_20_PRIORITY 3 #define STM32_IRQ_EXTI21_22_PRIORITY 3 + #define STM32_IRQ_USART1_PRIORITY 3 #define STM32_IRQ_USART2_PRIORITY 3 #define STM32_IRQ_LPUART1_PRIORITY 3 +#define STM32_IRQ_TIM2_PRIORITY 1 +#define STM32_IRQ_TIM6_PRIORITY 1 +#define STM32_IRQ_TIM21_PRIORITY 1 +#define STM32_IRQ_TIM22_PRIORITY 1 + /* * ADC driver system settings. * Note, IRQ is shared with EXT channels 21 and 22. @@ -113,10 +119,6 @@ #define STM32_GPT_USE_TIM6 FALSE #define STM32_GPT_USE_TIM21 FALSE #define STM32_GPT_USE_TIM22 FALSE -#define STM32_GPT_TIM2_IRQ_PRIORITY 2 -#define STM32_GPT_TIM6_IRQ_PRIORITY 2 -#define STM32_GPT_TIM21_IRQ_PRIORITY 2 -#define STM32_GPT_TIM22_IRQ_PRIORITY 2 /* * I2C driver system settings. @@ -141,9 +143,6 @@ #define STM32_ICU_USE_TIM2 FALSE #define STM32_ICU_USE_TIM21 FALSE #define STM32_ICU_USE_TIM22 FALSE -#define STM32_ICU_TIM2_IRQ_PRIORITY 3 -#define STM32_ICU_TIM21_IRQ_PRIORITY 3 -#define STM32_ICU_TIM22_IRQ_PRIORITY 3 /* * PWM driver system settings. @@ -151,9 +150,6 @@ #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM21 FALSE #define STM32_PWM_USE_TIM22 FALSE -#define STM32_PWM_TIM2_IRQ_PRIORITY 3 -#define STM32_PWM_TIM21_IRQ_PRIORITY 3 -#define STM32_PWM_TIM22_IRQ_PRIORITY 3 /* * SERIAL driver system settings. @@ -195,6 +191,8 @@ #define STM32_UART_USE_USART2 FALSE #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) diff --git a/testhal/STM32/multi/PAL/cfg/stm32l053_discovery/mcuconf.h b/testhal/STM32/multi/PAL/cfg/stm32l053_discovery/mcuconf.h index ee5a9b763..e0a250745 100644 --- a/testhal/STM32/multi/PAL/cfg/stm32l053_discovery/mcuconf.h +++ b/testhal/STM32/multi/PAL/cfg/stm32l053_discovery/mcuconf.h @@ -83,10 +83,16 @@ #define STM32_IRQ_EXTI16_PRIORITY 3 #define STM32_IRQ_EXTI17_20_PRIORITY 3 #define STM32_IRQ_EXTI21_22_PRIORITY 3 + #define STM32_IRQ_USART1_PRIORITY 3 #define STM32_IRQ_USART2_PRIORITY 3 #define STM32_IRQ_LPUART1_PRIORITY 3 +#define STM32_IRQ_TIM2_PRIORITY 1 +#define STM32_IRQ_TIM6_PRIORITY 1 +#define STM32_IRQ_TIM21_PRIORITY 1 +#define STM32_IRQ_TIM22_PRIORITY 1 + /* * ADC driver system settings. * Note, IRQ is shared with EXT channels 21 and 22. @@ -113,10 +119,6 @@ #define STM32_GPT_USE_TIM6 FALSE #define STM32_GPT_USE_TIM21 FALSE #define STM32_GPT_USE_TIM22 FALSE -#define STM32_GPT_TIM2_IRQ_PRIORITY 2 -#define STM32_GPT_TIM6_IRQ_PRIORITY 2 -#define STM32_GPT_TIM21_IRQ_PRIORITY 2 -#define STM32_GPT_TIM22_IRQ_PRIORITY 2 /* * I2C driver system settings. @@ -141,9 +143,6 @@ #define STM32_ICU_USE_TIM2 FALSE #define STM32_ICU_USE_TIM21 FALSE #define STM32_ICU_USE_TIM22 FALSE -#define STM32_ICU_TIM2_IRQ_PRIORITY 3 -#define STM32_ICU_TIM21_IRQ_PRIORITY 3 -#define STM32_ICU_TIM22_IRQ_PRIORITY 3 /* * PWM driver system settings. @@ -151,9 +150,6 @@ #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM21 FALSE #define STM32_PWM_USE_TIM22 FALSE -#define STM32_PWM_TIM2_IRQ_PRIORITY 3 -#define STM32_PWM_TIM21_IRQ_PRIORITY 3 -#define STM32_PWM_TIM22_IRQ_PRIORITY 3 /* * SERIAL driver system settings. @@ -195,6 +191,8 @@ #define STM32_UART_USE_USART2 FALSE #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) diff --git a/testhal/STM32/multi/RTC/cfg/stm32l053_discovery/mcuconf.h b/testhal/STM32/multi/RTC/cfg/stm32l053_discovery/mcuconf.h index ee5a9b763..e0a250745 100644 --- a/testhal/STM32/multi/RTC/cfg/stm32l053_discovery/mcuconf.h +++ b/testhal/STM32/multi/RTC/cfg/stm32l053_discovery/mcuconf.h @@ -83,10 +83,16 @@ #define STM32_IRQ_EXTI16_PRIORITY 3 #define STM32_IRQ_EXTI17_20_PRIORITY 3 #define STM32_IRQ_EXTI21_22_PRIORITY 3 + #define STM32_IRQ_USART1_PRIORITY 3 #define STM32_IRQ_USART2_PRIORITY 3 #define STM32_IRQ_LPUART1_PRIORITY 3 +#define STM32_IRQ_TIM2_PRIORITY 1 +#define STM32_IRQ_TIM6_PRIORITY 1 +#define STM32_IRQ_TIM21_PRIORITY 1 +#define STM32_IRQ_TIM22_PRIORITY 1 + /* * ADC driver system settings. * Note, IRQ is shared with EXT channels 21 and 22. @@ -113,10 +119,6 @@ #define STM32_GPT_USE_TIM6 FALSE #define STM32_GPT_USE_TIM21 FALSE #define STM32_GPT_USE_TIM22 FALSE -#define STM32_GPT_TIM2_IRQ_PRIORITY 2 -#define STM32_GPT_TIM6_IRQ_PRIORITY 2 -#define STM32_GPT_TIM21_IRQ_PRIORITY 2 -#define STM32_GPT_TIM22_IRQ_PRIORITY 2 /* * I2C driver system settings. @@ -141,9 +143,6 @@ #define STM32_ICU_USE_TIM2 FALSE #define STM32_ICU_USE_TIM21 FALSE #define STM32_ICU_USE_TIM22 FALSE -#define STM32_ICU_TIM2_IRQ_PRIORITY 3 -#define STM32_ICU_TIM21_IRQ_PRIORITY 3 -#define STM32_ICU_TIM22_IRQ_PRIORITY 3 /* * PWM driver system settings. @@ -151,9 +150,6 @@ #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM21 FALSE #define STM32_PWM_USE_TIM22 FALSE -#define STM32_PWM_TIM2_IRQ_PRIORITY 3 -#define STM32_PWM_TIM21_IRQ_PRIORITY 3 -#define STM32_PWM_TIM22_IRQ_PRIORITY 3 /* * SERIAL driver system settings. @@ -195,6 +191,8 @@ #define STM32_UART_USE_USART2 FALSE #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) diff --git a/tools/ftl/processors/conf/mcuconf_stm32l05xxx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32l05xxx/mcuconf.h.ftl index 9fbbe9160..dfff6347a 100644 --- a/tools/ftl/processors/conf/mcuconf_stm32l05xxx/mcuconf.h.ftl +++ b/tools/ftl/processors/conf/mcuconf_stm32l05xxx/mcuconf.h.ftl @@ -94,10 +94,16 @@ #define STM32_IRQ_EXTI16_PRIORITY ${doc.STM32_IRQ_EXTI16_PRIORITY!"3"} #define STM32_IRQ_EXTI17_20_PRIORITY ${doc.STM32_IRQ_EXTI17_20_PRIORITY!"3"} #define STM32_IRQ_EXTI21_22_PRIORITY ${doc.STM32_IRQ_EXTI21_22_PRIORITY!"3"} + #define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"3"} #define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"3"} #define STM32_IRQ_LPUART1_PRIORITY ${doc.STM32_IRQ_LPUART1_PRIORITY!"3"} +#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"1"} +#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"1"} +#define STM32_IRQ_TIM21_PRIORITY ${doc.STM32_IRQ_TIM21_PRIORITY!"1"} +#define STM32_IRQ_TIM22_PRIORITY ${doc.STM32_IRQ_TIM22_PRIORITY!"1"} + /* * ADC driver system settings. * Note, IRQ is shared with EXT channels 21 and 22. @@ -124,10 +130,6 @@ #define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"} #define STM32_GPT_USE_TIM21 ${doc.STM32_GPT_USE_TIM21!"FALSE"} #define STM32_GPT_USE_TIM22 ${doc.STM32_GPT_USE_TIM22!"FALSE"} -#define STM32_GPT_TIM2_IRQ_PRIORITY ${doc.STM32_GPT_TIM2_IRQ_PRIORITY!"2"} -#define STM32_GPT_TIM6_IRQ_PRIORITY ${doc.STM32_GPT_TIM6_IRQ_PRIORITY!"2"} -#define STM32_GPT_TIM21_IRQ_PRIORITY ${doc.STM32_GPT_TIM21_IRQ_PRIORITY!"2"} -#define STM32_GPT_TIM22_IRQ_PRIORITY ${doc.STM32_GPT_TIM22_IRQ_PRIORITY!"2"} /* * I2C driver system settings. @@ -152,9 +154,6 @@ #define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"} #define STM32_ICU_USE_TIM21 ${doc.STM32_ICU_USE_TIM21!"FALSE"} #define STM32_ICU_USE_TIM22 ${doc.STM32_ICU_USE_TIM22!"FALSE"} -#define STM32_ICU_TIM2_IRQ_PRIORITY ${doc.STM32_ICU_TIM2_IRQ_PRIORITY!"3"} -#define STM32_ICU_TIM21_IRQ_PRIORITY ${doc.STM32_ICU_TIM21_IRQ_PRIORITY!"3"} -#define STM32_ICU_TIM22_IRQ_PRIORITY ${doc.STM32_ICU_TIM22_IRQ_PRIORITY!"3"} /* * PWM driver system settings. @@ -162,9 +161,6 @@ #define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"} #define STM32_PWM_USE_TIM21 ${doc.STM32_PWM_USE_TIM21!"FALSE"} #define STM32_PWM_USE_TIM22 ${doc.STM32_PWM_USE_TIM22!"FALSE"} -#define STM32_PWM_TIM2_IRQ_PRIORITY ${doc.STM32_PWM_TIM2_IRQ_PRIORITY!"3"} -#define STM32_PWM_TIM21_IRQ_PRIORITY ${doc.STM32_PWM_TIM21_IRQ_PRIORITY!"3"} -#define STM32_PWM_TIM22_IRQ_PRIORITY ${doc.STM32_PWM_TIM22_IRQ_PRIORITY!"3"} /* * SERIAL driver system settings. @@ -206,6 +202,8 @@ #define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"} #define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"} #define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"} +#define STM32_UART_USART1_IRQ_PRIORITY ${doc.STM32_UART_USART1_IRQ_PRIORITY!"3"} +#define STM32_UART_USART2_IRQ_PRIORITY ${doc.STM32_UART_USART2_IRQ_PRIORITY!"3"} #define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"} #define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"} #define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"} diff --git a/tools/ftl/processors/conf/mcuconf_stm32l07xxx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32l07xxx/mcuconf.h.ftl index 614319359..bbd4fd50f 100644 --- a/tools/ftl/processors/conf/mcuconf_stm32l07xxx/mcuconf.h.ftl +++ b/tools/ftl/processors/conf/mcuconf_stm32l07xxx/mcuconf.h.ftl @@ -93,11 +93,19 @@ #define STM32_IRQ_EXTI16_PRIORITY ${doc.STM32_IRQ_EXTI16_PRIORITY!"3"} #define STM32_IRQ_EXTI17_20_PRIORITY ${doc.STM32_IRQ_EXTI17_20_PRIORITY!"3"} #define STM32_IRQ_EXTI21_22_PRIORITY ${doc.STM32_IRQ_EXTI21_22_PRIORITY!"3"} + #define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"3"} #define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"3"} -#define STM32_IRQ_UART4_5_PRIORITY ${doc.STM32_IRQ_UART4_5_PRIORITY!"3"} +#define STM32_IRQ_USART4_5_PRIORITY ${doc.STM32_IRQ_USART4_5_PRIORITY!"3"} #define STM32_IRQ_LPUART1_PRIORITY ${doc.STM32_IRQ_LPUART1_PRIORITY!"3"} +#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"1"} +#define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"1"} +#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"1"} +#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"1"} +#define STM32_IRQ_TIM21_PRIORITY ${doc.STM32_IRQ_TIM21_PRIORITY!"1"} +#define STM32_IRQ_TIM22_PRIORITY ${doc.STM32_IRQ_TIM22_PRIORITY!"1"} + /* * ADC driver system settings. * Note, IRQ is shared with EXT channels 21 and 22. @@ -131,12 +139,6 @@ #define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"} #define STM32_GPT_USE_TIM21 ${doc.STM32_GPT_USE_TIM21!"FALSE"} #define STM32_GPT_USE_TIM22 ${doc.STM32_GPT_USE_TIM22!"FALSE"} -#define STM32_GPT_TIM2_IRQ_PRIORITY ${doc.STM32_GPT_TIM2_IRQ_PRIORITY!"2"} -#define STM32_GPT_TIM3_IRQ_PRIORITY ${doc.STM32_GPT_TIM3_IRQ_PRIORITY!"2"} -#define STM32_GPT_TIM6_IRQ_PRIORITY ${doc.STM32_GPT_TIM6_IRQ_PRIORITY!"2"} -#define STM32_GPT_TIM7_IRQ_PRIORITY ${doc.STM32_GPT_TIM7_IRQ_PRIORITY!"2"} -#define STM32_GPT_TIM21_IRQ_PRIORITY ${doc.STM32_GPT_TIM21_IRQ_PRIORITY!"2"} -#define STM32_GPT_TIM22_IRQ_PRIORITY ${doc.STM32_GPT_TIM22_IRQ_PRIORITY!"2"} /* * I2C driver system settings. @@ -167,10 +169,6 @@ #define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"} #define STM32_ICU_USE_TIM21 ${doc.STM32_ICU_USE_TIM21!"FALSE"} #define STM32_ICU_USE_TIM22 ${doc.STM32_ICU_USE_TIM22!"FALSE"} -#define STM32_ICU_TIM2_IRQ_PRIORITY ${doc.STM32_ICU_TIM2_IRQ_PRIORITY!"3"} -#define STM32_ICU_TIM3_IRQ_PRIORITY ${doc.STM32_ICU_TIM3_IRQ_PRIORITY!"3"} -#define STM32_ICU_TIM21_IRQ_PRIORITY ${doc.STM32_ICU_TIM21_IRQ_PRIORITY!"3"} -#define STM32_ICU_TIM22_IRQ_PRIORITY ${doc.STM32_ICU_TIM22_IRQ_PRIORITY!"3"} /* * PWM driver system settings. @@ -179,10 +177,6 @@ #define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"} #define STM32_PWM_USE_TIM21 ${doc.STM32_PWM_USE_TIM21!"FALSE"} #define STM32_PWM_USE_TIM22 ${doc.STM32_PWM_USE_TIM22!"FALSE"} -#define STM32_PWM_TIM2_IRQ_PRIORITY ${doc.STM32_PWM_TIM2_IRQ_PRIORITY!"3"} -#define STM32_PWM_TIM3_IRQ_PRIORITY ${doc.STM32_PWM_TIM3_IRQ_PRIORITY!"3"} -#define STM32_PWM_TIM21_IRQ_PRIORITY ${doc.STM32_PWM_TIM21_IRQ_PRIORITY!"3"} -#define STM32_PWM_TIM22_IRQ_PRIORITY ${doc.STM32_PWM_TIM22_IRQ_PRIORITY!"3"} /* * SERIAL driver system settings. @@ -230,6 +224,9 @@ #define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"} #define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"} #define STM32_UART_UART5_DMA_PRIORITY ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"} +#define STM32_UART_USART1_IRQ_PRIORITY ${doc.STM32_UART_USART1_IRQ_PRIORITY!"3"} +#define STM32_UART_USART2_IRQ_PRIORITY ${doc.STM32_UART_USART2_IRQ_PRIORITY!"3"} +#define STM32_UART_USART4_5_IRQ_PRIORITY ${doc.STM32_UART_USART4_5_IRQ_PRIORITY!"3"} #define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"} #define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"} #define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}