diff --git a/os/hal/ports/STM32/STM32G0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32G0xx/stm32_rcc.h new file mode 100644 index 000000000..4597bd187 --- /dev/null +++ b/os/hal/ports/STM32/STM32G0xx/stm32_rcc.h @@ -0,0 +1,826 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32G0xx/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32g0xx.h. + * + * @addtogroup STM32G0xx_RCC + * @{ + */ +#ifndef STM32_RCC_H +#define STM32_RCC_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB bus (R1). + * + * @param[in] mask APB R1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPBR1(mask, lp) { \ + RCC->APBENR1 |= (mask); \ + if (lp) \ + RCC->APBSMENR1 |= (mask); \ + else \ + RCC->APBSMENR1 &= ~(mask); \ + (void)RCC->APBSMENR1; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB bus (R1). + * + * @param[in] mask APB R1 peripherals mask + * + * @api + */ +#define rccDisableAPBR1(mask) { \ + RCC->APBENR1 &= ~(mask); \ + RCC->APBSMENR1 &= ~(mask); \ + (void)RCC->APBSMENR1; \ +} + +/** + * @brief Resets one or more peripheral on the APB bus (R1). + * + * @param[in] mask APB R1 peripherals mask + * + * @api + */ +#define rccResetAPBR1(mask) { \ + RCC->APBRSTR1 |= (mask); \ + RCC->APBRSTR1 &= ~(mask); \ + (void)RCC->APBRSTR1; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB bus (R2). + * + * @param[in] mask APB R2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPBR2(mask, lp) { \ + RCC->APBENR2 |= (mask); \ + if (lp) \ + RCC->APBSMENR2 |= (mask); \ + else \ + RCC->APBSMENR2 &= ~(mask); \ + (void)RCC->APBSMENR2; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB bus (R2). + * + * @param[in] mask APB R2 peripherals mask + * + * @api + */ +#define rccDisableAPBR2(mask) { \ + RCC->APBENR2 &= ~(mask); \ + RCC->APBSMENR2 &= ~(mask); \ + (void)RCC->APBSMENR2; \ +} + +/** + * @brief Resets one or more peripheral on the APB bus (R2). + * + * @param[in] mask APB R2 peripherals mask + * + * @api + */ +#define rccResetAPBR2(mask) { \ + RCC->APBRSTR2 |= (mask); \ + RCC->APBRSTR2 &= ~(mask); \ + (void)RCC->APBRSTR2; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB(mask, lp) { \ + RCC->AHBENR |= (mask); \ + if (lp) \ + RCC->AHBSMENR |= (mask); \ + else \ + RCC->AHBSMENR &= ~(mask); \ + (void)RCC->AHBSMENR; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccDisableAHB(mask) { \ + RCC->AHBENR &= ~(mask); \ + RCC->AHBSMENR &= ~(mask); \ + (void)RCC->AHBSMENR; \ +} + +/** + * @brief Resets one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccResetAHB(mask) { \ + RCC->AHBRSTR |= (mask); \ + RCC->AHBRSTR &= ~(mask); \ + (void)RCC->AHBRSTR; \ +} +/** @} */ + +/** + * @name ADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC1(lp) rccEnableAPBR2(RCC_APBENR2_ADCEN, lp) + +/** + * @brief Disables the ADC peripheral clock. + * + * @api + */ +#define rccDisableADC1() rccDisableAPBR2(RCC_APBENR2_ADCEN) + +/** + * @brief Resets the ADC peripheral. + * + * @api + */ +#define rccResetADC1() rccResetAPBR2(RCC_APBRSTR2_ADCRST) +/** @} */ + +/** + * @name DAC peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DAC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDAC1(lp) rccEnableAPBR1(RCC_APBENR1_DAC1EN, lp) + +/** + * @brief Disables the DAC1 peripheral clock. + * + * @api + */ +#define rccDisableDAC1() rccDisableAPBR1(RCC_APBENR1_DAC1EN) + +/** + * @brief Resets the DAC1 peripheral. + * + * @api + */ +#define rccResetDAC1() rccResetAPBR1(RCC_APBRSTR1_DAC1RST) +/** @} */ + +/** + * @name DMA peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * + * @api + */ +#define rccDisableDMA1() rccDisableAHB(RCC_AHBENR_DMA1EN) + +/** + * @brief Resets the DMA1 peripheral. + * + * @api + */ +#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST) +/** @} */ + +/** + * @name DMAMUX peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DMAMUX peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMAMUX(lp) + +/** + * @brief Disables the DMAMUX peripheral clock. + * + * @api + */ +#define rccDisableDMAMUX() + +/** + * @brief Resets the DMAMUX peripheral. + * + * @api + */ +#define rccResetDMAMUX() +/** @} */ + +/** + * @name PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPBR1(RCC_APBENR1_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * + * @api + */ +#define rccDisablePWRInterface() rccDisableAPBR1(RCC_APBENR1_PWREN) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPBR1(RCC_APBRSTR1_PWRRST) +/** @} */ + +/** + * @name I2C peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPBR1(RCC_APBENR1_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * + * @api + */ +#define rccDisableI2C1() rccDisableAPBR1(RCC_APBENR1_I2C1EN) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPBR1(RCC_APBRSTR1_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C2(lp) rccEnableAPBR1(RCC_APBENR1_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * + * @api + */ +#define rccDisableI2C2() rccDisableAPBR1(RCC_APBENR1_I2C2EN) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define rccResetI2C2() rccResetAPBR1(RCC_APBRSTR1_I2C2RST) +/** @} */ + +/** + * @name RNG peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the RNG peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableRNG(lp) rccEnableAHB(RCC_AHBENR_RNGEN, lp) + +/** + * @brief Disables the RNG peripheral clock. + * + * @api + */ +#define rccDisableRNG() rccDisableAHB(RCC_AHBENR_RNGEN) + +/** + * @brief Resets the RNG peripheral. + * + * @api + */ +#define rccResetRNG() rccResetAHB(RCC_AHBRSTR_RNGRST) +/** @} */ + +/** + * @name SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPBR2(RCC_APBENR2_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * + * @api + */ +#define rccDisableSPI1() rccDisableAPBR2(RCC_APBENR2_SPI1EN) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB(RCC_APBRSTR2_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPBR1(RCC_APBENR1_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * + * @api + */ +#define rccDisableSPI2() rccDisableAPBR1(RCC_APBENR1_SPI2EN) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPBR1(RCC_APBRSTR1_SPI2RST) +/** @} */ + +/** + * @name TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM1(lp) rccEnableAPBR2(RCC_APBENR2_TIM1EN, lp) + +/** + * @brief Disables the TIM1 peripheral clock. + * + * @api + */ +#define rccDisableTIM1() rccDisableAPBR2(RCC_APBENR2_TIM1EN) + +/** + * @brief Resets the TIM1 peripheral. + * + * @api + */ +#define rccResetTIM1() rccResetAPBR2(RCC_APBRSTR2_TIM1RST) + +/** + * @brief Enables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPBR1(RCC_APBENR1_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * + * @api + */ +#define rccDisableTIM2() rccDisableAPBR1(RCC_APBENR1_TIM2EN) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPBR1(RCC_APBRSTR1_TIM2RST) + +/** + * @brief Enables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM3(lp) rccEnableAPBR1(RCC_APBENR1_TIM3EN, lp) + +/** + * @brief Disables the TIM3 peripheral clock. + * + * @api + */ +#define rccDisableTIM3() rccDisableAPBR1(RCC_APBENR1_TIM3EN) + +/** + * @brief Resets the TIM3 peripheral. + * + * @api + */ +#define rccResetTIM3() rccResetAPBR1(RCC_APBRSTR1_TIM3RST) + +/** + * @brief Enables the TIM6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM6(lp) rccEnableAPBR1(RCC_APBENR1_TIM6EN, lp) + +/** + * @brief Disables the TIM6 peripheral clock. + * + * @api + */ +#define rccDisableTIM6() rccDisableAPBR1(RCC_APBENR1_TIM6EN) + +/** + * @brief Resets the TIM6 peripheral. + * + * @api + */ +#define rccResetTIM6() rccResetAPBR1(RCC_APBRSTR1_TIM6RST) + +/** + * @brief Enables the TIM7 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM7(lp) rccEnableAPBR1(RCC_APBENR1_TIM7EN, lp) + +/** + * @brief Disables the TIM7 peripheral clock. + * + * @api + */ +#define rccDisableTIM7() rccDisableAPBR1(RCC_APBENR1_TIM7EN) + +/** + * @brief Resets the TIM7 peripheral. + * + * @api + */ +#define rccResetTIM7() rccResetAPBR1(RCC_APBRSTR1_TIM7RST) + +/** + * @brief Enables the TIM14 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM14(lp) rccEnableAPBR2(RCC_APBENR2_TIM14EN, lp) + +/** + * @brief Disables the TIM14 peripheral clock. + * + * @api + */ +#define rccDisableTIM14() rccDisableAPBR2(RCC_APBENR2_TIM14EN) + +/** + * @brief Resets the TIM14 peripheral. + * + * @api + */ +#define rccResetTIM14() rccResetAPBR2(RCC_APBRSTR2_TIM14RST) + +/** + * @brief Enables the TIM15 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM15(lp) rccEnableAPBR2(RCC_APBENR2_TIM15EN, lp) + +/** + * @brief Disables the TIM15 peripheral clock. + * + * @api + */ +#define rccDisableTIM15() rccDisableAPBR2(RCC_APBENR2_TIM15EN) + +/** + * @brief Resets the TIM15 peripheral. + * + * @api + */ +#define rccResetTIM15() rccResetAPBR2(RCC_APBRSTR2_TIM15RST) + +/** + * @brief Enables the TIM16 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM16(lp) rccEnableAPB(RCC_APBENR2_TIM16EN, lp) + +/** + * @brief Disables the TIM16 peripheral clock. + * + * @api + */ +#define rccDisableTIM16() rccDisableAPBR2(RCC_APBENR2_TIM16EN) + +/** + * @brief Resets the TIM16 peripheral. + * + * @api + */ +#define rccResetTIM16() rccResetAPBR2(RCC_APBRSTR2_TIM16RST) + +/** + * @brief Enables the TIM17 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM17(lp) rccEnableAPBR2(RCC_APBENR2_TIM17EN, lp) + +/** + * @brief Disables the TIM17 peripheral clock. + * + * @api + */ +#define rccDisableTIM17() rccDisableAPBR2(RCC_APBENR2_TIM17EN) + +/** + * @brief Resets the TIM17 peripheral. + * + * @api + */ +#define rccResetTIM17() rccResetAPBR2(RCC_APBRSTR2_TIM17RST) +/** @} */ + +/** + * @name USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPBR2(RCC_APBENR2_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * + * @api + */ +#define rccDisableUSART1() rccDisableAPBR2(RCC_APBENR2_USART1EN) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPBR2(RCC_APBRSTR2_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART2(lp) rccEnableAPBR1(RCC_APBENR1_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * + * @api + */ +#define rccDisableUSART2() rccDisableAPBR1(RCC_APBENR1_USART2EN) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define rccResetUSART2() rccResetAPBR1(RCC_APBRSTR1_USART2RST) + +/** + * @brief Enables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART3(lp) rccEnableAPBR1(RCC_APBENR1_USART3EN, lp) + +/** + * @brief Disables the USART3 peripheral clock. + * + * @api + */ +#define rccDisableUSART3() rccDisableAPBR1(RCC_APBENR1_USART3EN) + +/** + * @brief Resets the USART3 peripheral. + * + * @api + */ +#define rccResetUSART3() rccResetAPBR1(RCC_APBRSTR1_USART3RST) + +/** + * @brief Enables the UART4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART4(lp) rccEnableAPBR1(RCC_APBENR1_UART4EN, lp) + +/** + * @brief Disables the UART4 peripheral clock. + * + * @api + */ +#define rccDisableUART4() rccDisableAPBR1(RCC_APBENR1_UART4EN) + +/** + * @brief Resets the UART4 peripheral. + * + * @api + */ +#define rccResetUART4() rccResetAPBR1(RCC_APBRSTR1_UART4RST) + +/** + * @brief Enables the LPUART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableLPUART1(lp) rccEnableAPBR2(RCC_APBENR2_LPUART1EN, lp) + +/** + * @brief Disables the LPUART1 peripheral clock. + * + * @api + */ +#define rccDisableLPUART1() rccDisableAPBR2(RCC_APBENR2_LPUART1EN) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetLPUART1() rccResetAPBR2(RCC_APBRSTR2_LPUART1RST) +/** @} */ + +/** + * @name CRC peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the CRC peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp) + +/** + * @brief Disables the CRC peripheral clock. + * + * @api + */ +#define rccDisableCRC() rccDisableAHB(RCC_AHBENR_CRCEN) + +/** + * @brief Resets the CRC peripheral. + * + * @api + */ +#define rccResetCRC() rccResetAHB(RCC_AHBRSTR_CRCRST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* STM32_RCC_H */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32G0xx/stm32_registry.h b/os/hal/ports/STM32/STM32G0xx/stm32_registry.h new file mode 100644 index 000000000..7fc04c88d --- /dev/null +++ b/os/hal/ports/STM32/STM32G0xx/stm32_registry.h @@ -0,0 +1,289 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32G0xx/stm32_registry.h + * @brief STM32G0xx capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef STM32_REGISTRY_H +#define STM32_REGISTRY_H + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32G0xx capabilities + * @{ + */ + +/*===========================================================================*/ +/* Common. */ +/*===========================================================================*/ + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE +#define STM32_RTC_NUM_ALARMS 2 +#define STM32_RTC_STORAGE_SIZE 20 +#define STM32_RTC_COMMON_HANDLER Vector48 +#define STM32_RTC_COMMON_NUMBER 2 +#define STM32_RTC_ALARM_EXTI 18 +#define STM32_RTC_TAMP_STAMP_EXTI 19 +#define STM32_RTC_WKUP_EXTI 20 +#define STM32_RTC_IRQ_ENABLE() do { \ + nvicEnableVector(STM32_RTC_COMMON_NUMBER, \ + STM32_IRQ_EXTI19_21_IRQ_PRIORITY); \ +} while (false) + +#if defined(STM32G081xx) || defined(__DOXYGEN__) +#define STM32_HAS_RNG1 TRUE +#define STM32_HAS_HASH1 FALSE +#define STM32_HAS_AES1 TRUE +#else +#define STM32_HAS_RNG1 FALSE +#define STM32_HAS_HASH1 FALSE +#define STM32_HAS_AES1 FALSE +#endif + +/*===========================================================================*/ +/* STM32G070xx. */ +/*===========================================================================*/ + +#if defined(STM32G070xx) || defined(__DOXYGEN__) + +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_HANDLER Vector70 +#define STM32_ADC1_NUMBER 12 + +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE +#define STM32_HAS_CAN3 FALSE + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 FALSE +#define STM32_HAS_DAC1_CH2 FALSE +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_DMA_SUPPORTS_DMAMUX TRUE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector64 +#define STM32_DMA1_CH23_HANDLER Vector68 +#define STM32_DMA1_CH4567_HANDLER Vector6C +#define STM32_DMA1_CH1_NUMBER 9 +#define STM32_DMA1_CH23_NUMBER 10 +#define STM32_DMA1_CH4567_NUMBER 11 + +#define STM32_DMA2_NUM_CHANNELS 0 + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_LINES 16 +#define STM32_EXTI_IMR1_MASK 0xFFF80000U + +#define STM32_EXTI_LINE01_HANDLER Vector54 +#define STM32_EXTI_LINE23_HANDLER Vector58 +#define STM32_EXTI_LINE4_15_HANDLER Vector5C +#define STM32_EXTI_LINE16_HANDLER Vector44 +#define STM32_EXTI_LINE1921_HANDLER Vector48 + +#define STM32_EXTI_LINE01_NUMBER 5 +#define STM32_EXTI_LINE23_NUMBER 6 +#define STM32_EXTI_LINE4_15_NUMBER 7 +#define STM32_EXTI_LINE16_NUMBER 1 +#define STM32_EXTI_LINE1921_NUMBER 2 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE FALSE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOJ FALSE +#define STM32_HAS_GPIOK FALSE +#define STM32_GPIO_EN_MASK (RCC_IOPENR_GPIOAEN | \ + RCC_IOPENR_GPIOBEN | \ + RCC_IOPENR_GPIOCEN | \ + RCC_IOPENR_GPIODEN | \ + RCC_IOPENR_GPIOFEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_GLOBAL_HANDLER Vector9C +#define STM32_I2C1_GLOBAL_NUMBER 23 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C1_GLOBAL_HANDLER VectorA0 +#define STM32_I2C1_GLOBAL_NUMBER 24 + +#define STM32_HAS_I2C3 FALSE +#define STM32_HAS_I2C4 FALSE + +/* OCTOSPI attributes.*/ +#define STM32_HAS_OCTOSPI1 FALSE +#define STM32_HAS_OCTOSPI2 FALSE + +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 FALSE + +/* SDMMC attributes.*/ +#define STM32_HAS_SDMMC1 FALSE +#define STM32_HAS_SDMMC2 FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S TRUE + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S FALSE + +#define STM32_HAS_SPI3 FALSE +#define STM32_HAS_SPI4 FALSE +#define STM32_HAS_SPI5 FALSE +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 6 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 6 +#define STM32_TIM1_UP_HANDLER Vector74 +#define STM32_TIM1_CC_HANDLER Vector78 +#define STM32_TIM1_UP_NUMBER 13 +#define STM32_TIM1_CC_NUMBER 14 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 +#define STM32_TIM3_HANDLER VectorB4 +#define STM32_TIM3_NUMBER 29 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 +#define STM32_TIM6_HANDLER Vector84 +#define STM32_TIM6_NUMBER 17 + +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 +#define STM32_TIM7_HANDLER Vector88 +#define STM32_TIM7_NUMBER 18 + +#define STM32_HAS_TIM14 TRUE +#define STM32_TIM14_IS_32BITS FALSE +#define STM32_TIM14_CHANNELS 1 +#define STM32_TIM14_HANDLER Vector8C +#define STM32_TIM14_NUMBER 19 + +#define STM32_HAS_TIM15 TRUE +#define STM32_TIM15_IS_32BITS FALSE +#define STM32_TIM15_CHANNELS 2 +#define STM32_TIM15_HANDLER Vector90 +#define STM32_TIM15_NUMBER 20 + +#define STM32_HAS_TIM16 TRUE +#define STM32_TIM16_IS_32BITS FALSE +#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_HANDLER Vector94 +#define STM32_TIM16_NUMBER 21 + +#define STM32_HAS_TIM17 TRUE +#define STM32_TIM17_IS_32BITS FALSE +#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_HANDLER Vector98 +#define STM32_TIM17_NUMBER 22 + +#define STM32_HAS_TIM2 FALSE +#define STM32_HAS_TIM4 FALSE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM20 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_HAS_USART2 TRUE +#define STM32_HAS_USART3 TRUE +#define STM32_HAS_UART4 TRUE +#define STM32_HAS_LPUART1 TRUE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE +#define STM32_HAS_UART7 FALSE +#define STM32_HAS_UART8 FALSE + +/* USB attributes.*/ +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +#define STM32_HAS_USB FALSE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED TRUE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC FALSE + +/* CRC attributes.*/ +#define STM32_HAS_CRC FALSE + +/* DCMI attributes.*/ +#define STM32_HAS_DCMI FALSE + +#endif /* defined(STM32G070xx) */ + +/** @} */ + +#endif /* STM32_REGISTRY_H */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h b/os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h index d88c378f4..71d954b0a 100644 --- a/os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h @@ -701,7 +701,7 @@ * * @api */ -#define rccResetRNG() rccResetAHB3(RCC_AHB2RSTR_RNGRST) +#define rccResetRNG() rccResetAHB2(RCC_AHB2RSTR_RNGRST) /** @} */ /** diff --git a/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h index 654131a96..0a43f778e 100644 --- a/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h @@ -265,7 +265,7 @@ #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 4 +#define STM32_TIM1_CHANNELS 6 #define STM32_TIM1_UP_HANDLER VectorA4 #define STM32_TIM1_CC_HANDLER VectorAC #define STM32_TIM1_UP_NUMBER 25 diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h index a48e305f8..7d66a2289 100644 --- a/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h @@ -650,7 +650,7 @@ * * @api */ -#define rccResetRNG() rccResetAHB3(RCC_AHB2RSTR_RNGRST) +#define rccResetRNG() rccResetAHB2(RCC_AHB2RSTR_RNGRST) /** @} */ /** diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h index 6549074e6..087afd477 100644 --- a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h @@ -279,7 +279,7 @@ #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 4 +#define STM32_TIM1_CHANNELS 6 #define STM32_TIM1_UP_HANDLER VectorA4 #define STM32_TIM1_CC_HANDLER VectorAC #define STM32_TIM1_UP_NUMBER 25 @@ -632,7 +632,7 @@ #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 4 +#define STM32_TIM1_CHANNELS 6 #define STM32_TIM1_UP_HANDLER VectorA4 #define STM32_TIM1_CC_HANDLER VectorAC #define STM32_TIM1_UP_NUMBER 25 @@ -1000,7 +1000,7 @@ #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 4 +#define STM32_TIM1_CHANNELS 6 #define STM32_TIM1_UP_HANDLER VectorA4 #define STM32_TIM1_CC_HANDLER VectorAC #define STM32_TIM1_UP_NUMBER 25 @@ -1425,7 +1425,7 @@ #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 4 +#define STM32_TIM1_CHANNELS 6 #define STM32_TIM1_UP_HANDLER VectorA4 #define STM32_TIM1_CC_HANDLER VectorAC #define STM32_TIM1_UP_NUMBER 25