diff --git a/demos/PPC-SPC560B-GCC/mcuconf.h b/demos/PPC-SPC560B-GCC/mcuconf.h
index 572f13f5a..f0bde5dfa 100644
--- a/demos/PPC-SPC560B-GCC/mcuconf.h
+++ b/demos/PPC-SPC560B-GCC/mcuconf.h
@@ -35,9 +35,9 @@
 #define SPC5_FMPLL0_IDF_VALUE               1
 #define SPC5_FMPLL0_NDIV_VALUE              32
 #define SPC5_FMPLL0_ODF                     SPC5_FMPLL_ODF_DIV4
-#define SPC5_PHERIPERAL1_CLK_DIV_VALUE      2
-#define SPC5_PHERIPERAL2_CLK_DIV_VALUE      2
-#define SPC5_PHERIPERAL3_CLK_DIV_VALUE      2
+#define SPC5_PERIPHERAL1_CLK_DIV_VALUE      2
+#define SPC5_PERIPHERAL2_CLK_DIV_VALUE      2
+#define SPC5_PERIPHERAL3_CLK_DIV_VALUE      2
 #define SPC5_ME_ME_BITS                     (SPC5_ME_ME_RUN1 |              \
                                              SPC5_ME_ME_RUN2 |              \
                                              SPC5_ME_ME_RUN3 |              \
diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.h b/os/hal/platforms/SPC560BCxx/hal_lld.h
index d92fb53bf..a0294a731 100644
--- a/os/hal/platforms/SPC560BCxx/hal_lld.h
+++ b/os/hal/platforms/SPC560BCxx/hal_lld.h
@@ -287,24 +287,24 @@
  * @brief   Peripherals Set 1 clock divider value.
  * @note    Zero means disabled clock.
  */
-#if !defined(SPC5_PHERIPERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_PHERIPERAL1_CLK_DIV_VALUE      2
+#if !defined(SPC5_PERIPHERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL1_CLK_DIV_VALUE      2
 #endif
 
 /**
  * @brief   Peripherals Set 2 clock divider value.
  * @note    Zero means disabled clock.
  */
-#if !defined(SPC5_PHERIPERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_PHERIPERAL2_CLK_DIV_VALUE      2
+#if !defined(SPC5_PERIPHERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL2_CLK_DIV_VALUE      2
 #endif
 
 /**
  * @brief   Peripherals Set 3 clock divider value.
  * @note    Zero means disabled clock.
  */
-#if !defined(SPC5_PHERIPERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_PHERIPERAL3_CLK_DIV_VALUE      2
+#if !defined(SPC5_PERIPHERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL3_CLK_DIV_VALUE      2
 #endif
 
 /**
@@ -703,33 +703,33 @@
 #endif
 
 /* Check on the peripherals set 1 clock divider settings.*/
-#if SPC5_PHERIPERAL1_CLK_DIV_VALUE == 0
+#if SPC5_PERIPHERAL1_CLK_DIV_VALUE == 0
 #define SPC5_CGM_SC_DC0         0
-#elif (SPC5_PHERIPERAL1_CLK_DIV_VALUE >= 1) &&                              \
-      (SPC5_PHERIPERAL1_CLK_DIV_VALUE <= 16)
-#define SPC5_CGM_SC_DC0         (0x80 | (SPC5_PHERIPERAL1_CLK_DIV_VALUE - 1))
+#elif (SPC5_PERIPHERAL1_CLK_DIV_VALUE >= 1) &&                              \
+      (SPC5_PERIPHERAL1_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC0         (0x80 | (SPC5_PERIPHERAL1_CLK_DIV_VALUE - 1))
 #else
-#error "invalid SPC5_PHERIPERAL1_CLK_DIV_VALUE value specified"
+#error "invalid SPC5_PERIPHERAL1_CLK_DIV_VALUE value specified"
 #endif
 
 /* Check on the peripherals set 2 clock divider settings.*/
-#if SPC5_PHERIPERAL2_CLK_DIV_VALUE == 0
+#if SPC5_PERIPHERAL2_CLK_DIV_VALUE == 0
 #define SPC5_CGM_SC_DC1         0
-#elif (SPC5_PHERIPERAL2_CLK_DIV_VALUE >= 1) &&                              \
-      (SPC5_PHERIPERAL2_CLK_DIV_VALUE <= 16)
-#define SPC5_CGM_SC_DC1         (0x80 | (SPC5_PHERIPERAL2_CLK_DIV_VALUE - 1))
+#elif (SPC5_PERIPHERAL2_CLK_DIV_VALUE >= 1) &&                              \
+      (SPC5_PERIPHERAL2_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC1         (0x80 | (SPC5_PERIPHERAL2_CLK_DIV_VALUE - 1))
 #else
-#error "invalid SPC5_PHERIPERAL2_CLK_DIV_VALUE value specified"
+#error "invalid SPC5_PERIPHERAL2_CLK_DIV_VALUE value specified"
 #endif
 
 /* Check on the peripherals set 3 clock divider settings.*/
-#if SPC5_PHERIPERAL3_CLK_DIV_VALUE == 0
+#if SPC5_PERIPHERAL3_CLK_DIV_VALUE == 0
 #define SPC5_CGM_SC_DC2         0
-#elif (SPC5_PHERIPERAL3_CLK_DIV_VALUE >= 1) &&                              \
-      (SPC5_PHERIPERAL3_CLK_DIV_VALUE <= 16)
-#define SPC5_CGM_SC_DC2         (0x80 | (SPC5_PHERIPERAL3_CLK_DIV_VALUE - 1))
+#elif (SPC5_PERIPHERAL3_CLK_DIV_VALUE >= 1) &&                              \
+      (SPC5_PERIPHERAL3_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC2         (0x80 | (SPC5_PERIPHERAL3_CLK_DIV_VALUE - 1))
 #else
-#error "invalid SPC5_PHERIPERAL3_CLK_DIV_VALUE value specified"
+#error "invalid SPC5_PERIPHERAL3_CLK_DIV_VALUE value specified"
 #endif
 
 /*===========================================================================*/