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Artery AT32F4xx port

This commit is contained in:
Andrey Gusakov 2023-05-29 22:33:59 +03:00 committed by rusefillc
parent 600ebfeec0
commit deadc35124
11 changed files with 10374 additions and 0 deletions
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179
os/hal/ports/AT32/AT32F4xx/at32_isr.c Normal file
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F4xx/stm32_isr.c
* @brief STM32F4xx ISR handler code.
*
* @addtogroup STM32F4xx_ISR
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
#define exti_serve_irq(pr, channel) { \
\
if ((pr) & (1U << (channel))) { \
_pal_isr_code(channel); \
} \
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#include "stm32_exti0.inc"
#include "stm32_exti1.inc"
#include "stm32_exti2.inc"
#include "stm32_exti3.inc"
#include "stm32_exti4.inc"
#include "stm32_exti5_9.inc"
#include "stm32_exti10_15.inc"
#include "stm32_exti16.inc"
#include "stm32_exti17.inc"
#include "stm32_exti18.inc"
#include "stm32_exti19.inc"
#include "stm32_exti20.inc"
#include "stm32_exti21.inc"
#include "stm32_exti22.inc"
#include "stm32_usart1.inc"
#include "stm32_usart2.inc"
#include "stm32_usart3.inc"
#include "stm32_uart4.inc"
#include "stm32_uart5.inc"
#include "stm32_usart6.inc"
#include "stm32_uart7.inc"
#include "stm32_uart8.inc"
#include "stm32_uart9.inc"
#include "stm32_uart10.inc"
#include "stm32_tim1_9_10_11.inc"
#include "stm32_tim2.inc"
#include "stm32_tim3.inc"
#include "stm32_tim4.inc"
#include "stm32_tim5.inc"
#include "stm32_tim6.inc"
#include "stm32_tim7.inc"
#include "stm32_tim8_12_13_14.inc"
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Enables IRQ sources.
*
* @notapi
*/
void irqInit(void) {
exti0_irq_init();
exti1_irq_init();
exti2_irq_init();
exti3_irq_init();
exti4_irq_init();
exti5_9_irq_init();
exti10_15_irq_init();
exti16_irq_init();
exti17_irq_init();
exti18_irq_init();
exti19_irq_init();
exti20_irq_init();
exti21_irq_init();
exti22_irq_init();
tim1_tim9_tim10_tim11_irq_init();
tim2_irq_init();
tim3_irq_init();
tim4_irq_init();
tim5_irq_init();
tim6_irq_init();
tim7_irq_init();
tim8_tim12_tim13_tim14_irq_init();
usart1_irq_init();
usart2_irq_init();
usart3_irq_init();
uart4_irq_init();
uart5_irq_init();
usart6_irq_init();
uart7_irq_init();
uart8_irq_init();
uart9_irq_init();
uart10_irq_init();
}
/**
* @brief Disables IRQ sources.
*
* @notapi
*/
void irqDeinit(void) {
exti0_irq_deinit();
exti1_irq_deinit();
exti2_irq_deinit();
exti3_irq_deinit();
exti4_irq_deinit();
exti5_9_irq_deinit();
exti10_15_irq_deinit();
exti16_irq_deinit();
exti17_irq_deinit();
exti18_irq_deinit();
exti19_irq_deinit();
exti20_irq_deinit();
exti21_irq_deinit();
exti22_irq_deinit();
tim1_tim9_tim10_tim11_irq_deinit();
tim2_irq_deinit();
tim3_irq_deinit();
tim4_irq_deinit();
tim5_irq_deinit();
tim6_irq_deinit();
tim7_irq_deinit();
tim8_tim12_tim13_tim14_irq_deinit();
usart1_irq_deinit();
usart2_irq_deinit();
usart3_irq_deinit();
uart4_irq_deinit();
uart5_irq_deinit();
usart6_irq_deinit();
uart7_irq_deinit();
uart8_irq_deinit();
uart9_irq_deinit();
uart10_irq_deinit();
}
/** @} */

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os/hal/ports/AT32/AT32F4xx/at32_isr.h Normal file
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F4xx/stm32_isr.h
* @brief STM32F4xx ISR handler header.
*
* @addtogroup STM32F4xx_ISR
* @{
*/
#ifndef STM32_ISR_H
#define STM32_ISR_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISRs suppressed in standard drivers
* @{
*/
#define STM32_TIM1_SUPPRESS_ISR
#define STM32_TIM2_SUPPRESS_ISR
#define STM32_TIM3_SUPPRESS_ISR
#define STM32_TIM4_SUPPRESS_ISR
#define STM32_TIM5_SUPPRESS_ISR
#define STM32_TIM6_SUPPRESS_ISR
#define STM32_TIM7_SUPPRESS_ISR
#define STM32_TIM8_SUPPRESS_ISR
#define STM32_TIM9_SUPPRESS_ISR
#define STM32_TIM10_SUPPRESS_ISR
#define STM32_TIM11_SUPPRESS_ISR
#define STM32_TIM12_SUPPRESS_ISR
#define STM32_TIM13_SUPPRESS_ISR
#define STM32_TIM14_SUPPRESS_ISR
#define STM32_USART1_SUPPRESS_ISR
#define STM32_USART2_SUPPRESS_ISR
#define STM32_USART3_SUPPRESS_ISR
#define STM32_UART4_SUPPRESS_ISR
#define STM32_UART5_SUPPRESS_ISR
#define STM32_USART6_SUPPRESS_ISR
#define STM32_UART7_SUPPRESS_ISR
#define STM32_UART8_SUPPRESS_ISR
#define STM32_UART9_SUPPRESS_ISR
#define STM32_UART10_SUPPRESS_ISR
/** @} */
/**
* @name ISR names and numbers
* @{
*/
/*
* CAN units.
*/
#define STM32_CAN1_TX_HANDLER Vector8C
#define STM32_CAN1_RX0_HANDLER Vector90
#define STM32_CAN1_RX1_HANDLER Vector94
#define STM32_CAN1_SCE_HANDLER Vector98
#define STM32_CAN2_TX_HANDLER Vector13C
#define STM32_CAN2_RX0_HANDLER Vector140
#define STM32_CAN2_RX1_HANDLER Vector144
#define STM32_CAN2_SCE_HANDLER Vector148
#define STM32_CAN3_TX_HANDLER Vector168
#define STM32_CAN3_RX0_HANDLER Vector16C
#define STM32_CAN3_RX1_HANDLER Vector170
#define STM32_CAN3_SCE_HANDLER Vector174
#define STM32_CAN1_TX_NUMBER 19
#define STM32_CAN1_RX0_NUMBER 20
#define STM32_CAN1_RX1_NUMBER 21
#define STM32_CAN1_SCE_NUMBER 22
#define STM32_CAN2_TX_NUMBER 63
#define STM32_CAN2_RX0_NUMBER 64
#define STM32_CAN2_RX1_NUMBER 65
#define STM32_CAN2_SCE_NUMBER 66
#define STM32_CAN3_TX_NUMBER 74
#define STM32_CAN3_RX0_NUMBER 75
#define STM32_CAN3_RX1_NUMBER 76
#define STM32_CAN3_SCE_NUMBER 77
/*
* EXTI unit.
*/
#define STM32_EXTI0_HANDLER Vector58
#define STM32_EXTI1_HANDLER Vector5C
#define STM32_EXTI2_HANDLER Vector60
#define STM32_EXTI3_HANDLER Vector64
#define STM32_EXTI4_HANDLER Vector68
#define STM32_EXTI5_9_HANDLER Vector9C
#define STM32_EXTI10_15_HANDLER VectorE0
#define STM32_EXTI16_HANDLER Vector44 /* PVD */
#define STM32_EXTI17_HANDLER VectorE4 /* RTC ALARM */
#define STM32_EXTI18_HANDLER VectorE8 /* USB FS WAKEUP */
#define STM32_EXTI19_HANDLER Vector138 /* ETH WAKEUP */
#define STM32_EXTI20_HANDLER Vector170 /* USB HS WAKEUP */
#define STM32_EXTI21_HANDLER Vector48 /* RTC TAMPER */
#define STM32_EXTI22_HANDLER Vector4C /* RTC WAKEUP */
#define STM32_EXTI0_NUMBER 6
#define STM32_EXTI1_NUMBER 7
#define STM32_EXTI2_NUMBER 8
#define STM32_EXTI3_NUMBER 9
#define STM32_EXTI4_NUMBER 10
#define STM32_EXTI5_9_NUMBER 23
#define STM32_EXTI10_15_NUMBER 40
#define STM32_EXTI16_NUMBER 1
#define STM32_EXTI17_NUMBER 41
#define STM32_EXTI18_NUMBER 42
#define STM32_EXTI19_NUMBER 62
#define STM32_EXTI20_NUMBER 76
#define STM32_EXTI21_NUMBER 2
#define STM32_EXTI22_NUMBER 3
/*
* I2C units.
*/
#define STM32_I2C1_EVENT_HANDLER VectorBC
#define STM32_I2C1_ERROR_HANDLER VectorC0
#define STM32_I2C2_EVENT_HANDLER VectorC4
#define STM32_I2C2_ERROR_HANDLER VectorC8
#define STM32_I2C3_EVENT_HANDLER Vector160
#define STM32_I2C3_ERROR_HANDLER Vector164
#define STM32_I2C1_EVENT_NUMBER 31
#define STM32_I2C1_ERROR_NUMBER 32
#define STM32_I2C2_EVENT_NUMBER 33
#define STM32_I2C2_ERROR_NUMBER 34
#define STM32_I2C3_EVENT_NUMBER 72
#define STM32_I2C3_ERROR_NUMBER 73
/*
* OTG units.
*/
#define STM32_OTG1_HANDLER Vector14C
#define STM32_OTG2_HANDLER Vector174
#define STM32_OTG2_EP1OUT_HANDLER Vector168
#define STM32_OTG2_EP1IN_HANDLER Vector16C
#define STM32_OTG1_NUMBER 67
#define STM32_OTG2_NUMBER 77
#define STM32_OTG2_EP1OUT_NUMBER 74
#define STM32_OTG2_EP1IN_NUMBER 75
/*
* SDIO unit.
*/
#define STM32_SDIO_HANDLER Vector104
#define STM32_SDIO_NUMBER 49
/*
* TIM units.
*/
#define STM32_TIM1_BRK_TIM9_HANDLER VectorA0
#define STM32_TIM1_UP_TIM10_HANDLER VectorA4
#define STM32_TIM1_TRGCO_TIM11_HANDLER VectorA8
#define STM32_TIM1_CC_HANDLER VectorAC
#define STM32_TIM2_HANDLER VectorB0
#define STM32_TIM3_HANDLER VectorB4
#define STM32_TIM4_HANDLER VectorB8
#define STM32_TIM5_HANDLER Vector108
#define STM32_TIM6_HANDLER Vector118
#define STM32_TIM7_HANDLER Vector11C
#define STM32_TIM8_BRK_TIM12_HANDLER VectorEC
#define STM32_TIM8_UP_TIM13_HANDLER VectorF0
#define STM32_TIM8_TRGCO_TIM14_HANDLER VectorF4
#define STM32_TIM8_CC_HANDLER VectorF8
#define STM32_TIM1_BRK_TIM9_NUMBER 24
#define STM32_TIM1_UP_TIM10_NUMBER 25
#define STM32_TIM1_TRGCO_TIM11_NUMBER 26
#define STM32_TIM1_CC_NUMBER 27
#define STM32_TIM2_NUMBER 28
#define STM32_TIM3_NUMBER 29
#define STM32_TIM4_NUMBER 30
#define STM32_TIM5_NUMBER 50
#define STM32_TIM6_NUMBER 54
#define STM32_TIM7_NUMBER 55
#define STM32_TIM8_BRK_TIM12_NUMBER 43
#define STM32_TIM8_UP_TIM13_NUMBER 44
#define STM32_TIM8_TRGCO_TIM14_NUMBER 45
#define STM32_TIM8_CC_NUMBER 46
/*
* LPTIM units.
*/
#define STM32_LPTIM1_HANDLER Vector1C4
#define STM32_LPTIM1_NUMBER 97
/*
* USART units.
*/
#define STM32_USART1_HANDLER VectorD4
#define STM32_USART2_HANDLER VectorD8
#define STM32_USART3_HANDLER VectorDC
#define STM32_UART4_HANDLER Vector110
#define STM32_UART5_HANDLER Vector114
#define STM32_USART6_HANDLER Vector15C
#define STM32_UART7_HANDLER Vector188
#define STM32_UART8_HANDLER Vector18C
#define STM32_UART9_HANDLER Vector1A0
#define STM32_UART10_HANDLER Vector1A4
#define STM32_USART1_NUMBER 37
#define STM32_USART2_NUMBER 38
#define STM32_USART3_NUMBER 39
#define STM32_UART4_NUMBER 52
#define STM32_UART5_NUMBER 53
#define STM32_USART6_NUMBER 71
#define STM32_UART7_NUMBER 82
#define STM32_UART8_NUMBER 83
#define STM32_UART9_NUMBER 88
#define STM32_UART10_NUMBER 89
/*
* Ethernet
*/
#define ETH_IRQHandler Vector134
/*
* FSMC
*/
#define STM32_FSMC_HANDLER Vector100
#define STM32_FSMC_NUMBER 48
/*
* LTDC
*/
#define STM32_LTDC_EV_HANDLER Vector1A0
#define STM32_LTDC_ER_HANDLER Vector1A4
#define STM32_LTDC_EV_NUMBER 88
#define STM32_LTDC_ER_NUMBER 89
/*
* DMA2D
*/
#define STM32_DMA2D_HANDLER Vector1A8
#define STM32_DMA2D_NUMBER 90
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void irqInit(void);
void irqDeinit(void);
#ifdef __cplusplus
}
#endif
#endif /* STM32_ISR_H */
/** @} */

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os/hal/ports/AT32/AT32F4xx/at32_registry.h Normal file
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/*
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_efl_lld.c
* @brief STM32F4xx Embedded Flash subsystem low level driver source.
*
* @addtogroup HAL_EFL
* @{
*/
#include <string.h>
#include "hal.h"
#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#define STM32_FLASH_LINE_SIZE (1 << STM32_FLASH_PSIZE)
#define STM32_FLASH_LINE_MASK (STM32_FLASH_LINE_SIZE - 1U)
#define FLASH_PDKEY1 0x04152637U
#define FLASH_PDKEY2 0xFAFBFCFDU
#define FLASH_KEY1 0x45670123U
#define FLASH_KEY2 0xCDEF89ABU
#define FLASH_OPTKEY1 0x08192A3BU
#define FLASH_OPTKEY2 0x4C5D6E7FU
#if !defined(FLASH_SR_OPERR)
#define FLASH_SR_OPERR FLASH_SR_SOP
#endif
#if !defined(STM32_FLASH_DUAL_BANK_PERMANENT)
#define STM32_FLASH_DUAL_BANK_PERMANENT FALSE
#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/**
* @brief EFL1 driver identifier.
*/
EFlashDriver EFLD1;
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
#if defined(STM32F413xx) || defined(STM32F412xx) || \
defined(STM32F40_41xxx) || defined(__DOXYGEN__)
/* Sector table for 1.5M device. */
static const flash_sector_descriptor_t efl_lld_sect1[STM32_FLASH1_SECTORS_TOTAL] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
{ 4 * 16384 + 65536, 131072}, /* Sector 5. */
{ 4 * 16384 + 65536 + 1 * 131072, 131072}, /* Sector 6. */
{ 4 * 16384 + 65536 + 2 * 131072, 131072}, /* Sector 7. */
{ 4 * 16384 + 65536 + 3 * 131072, 131072}, /* Sector 8. */
{ 4 * 16384 + 65536 + 4 * 131072, 131072}, /* Sector 9. */
{ 4 * 16384 + 65536 + 5 * 131072, 131072}, /* Sector 10. */
{ 4 * 16384 + 65536 + 6 * 131072, 131072}, /* Sector 11. */
{ 4 * 16384 + 65536 + 7 * 131072, 131072}, /* Sector 12. */
{ 4 * 16384 + 65536 + 8 * 131072, 131072}, /* Sector 13. */
{ 4 * 16384 + 65536 + 9 * 131072, 131072}, /* Sector 14. */
{ 4 * 16384 + 65536 + 10 * 131072, 131072} /* Sector 15. */
};
/* Sector table for 1M device. */
static const flash_sector_descriptor_t efl_lld_sect2[STM32_FLASH2_SECTORS_TOTAL] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
{ 4 * 16384 + 65536, 131072}, /* Sector 5. */
{ 4 * 16384 + 65536 + 1 * 131072, 131072}, /* Sector 6. */
{ 4 * 16384 + 65536 + 2 * 131072, 131072}, /* Sector 7. */
{ 4 * 16384 + 65536 + 3 * 131072, 131072}, /* Sector 8. */
{ 4 * 16384 + 65536 + 4 * 131072, 131072}, /* Sector 9. */
{ 4 * 16384 + 65536 + 5 * 131072, 131072}, /* Sector 10. */
{ 4 * 16384 + 65536 + 6 * 131072, 131072} /* Sector 11. */
};
/* The descriptors for 1.5M device. */
static const flash_descriptor_t efl_lld_size1[STM32_FLASH_NUMBER_OF_BANKS] = {
{ /* Single bank organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH1_SECTORS_TOTAL,
.sectors = efl_lld_sect1,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH1_SIZE * STM32_FLASH_SIZE_SCALE
}
};
/* The descriptors for 1M device. */
static const flash_descriptor_t efl_lld_size2[STM32_FLASH_NUMBER_OF_BANKS] = {
{ /* Single bank organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH2_SECTORS_TOTAL,
.sectors = efl_lld_sect2,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH2_SIZE * STM32_FLASH_SIZE_SCALE
}
};
/* Table describing possible flash sizes and descriptors for this device. */
static const efl_lld_size_t efl_lld_flash_sizes[] = {
{
.desc = efl_lld_size1
},
{
.desc = efl_lld_size2
}
};
#elif defined(STM32F401xx) || defined(STM32F411xx) || \
defined(__DOXYGEN__)
/* Sector table for 128k device. */
static const flash_sector_descriptor_t efl_lld_sect1[STM32_FLASH1_SECTORS_TOTAL] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
};
/* Sector table for 256k device. */
static const flash_sector_descriptor_t efl_lld_sect2[STM32_FLASH2_SECTORS_TOTAL] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
{ 4 * 16384 + 65536, 131072}, /* Sector 5. */
};
/* Sector table for 384k device. */
static const flash_sector_descriptor_t efl_lld_sect3[STM32_FLASH3_SECTORS_TOTAL] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
{ 4 * 16384 + 65536, 131072}, /* Sector 5. */
{ 4 * 16384 + 65536 + 1 * 131072, 131072}, /* Sector 6. */
};
/* Sector table for 512k device. */
static const flash_sector_descriptor_t efl_lld_sect4[STM32_FLASH4_SECTORS_TOTAL] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
{ 4 * 16384 + 65536, 131072}, /* Sector 5. */
{ 4 * 16384 + 65536 + 1 * 131072, 131072}, /* Sector 6. */
{ 4 * 16384 + 65536 + 2 * 131072, 131072}, /* Sector 7. */
};
/* The descriptors for 128k device. */
static const flash_descriptor_t efl_lld_size1[STM32_FLASH_NUMBER_OF_BANKS] = {
{ /* Single bank organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH1_SECTORS_TOTAL,
.sectors = efl_lld_sect1,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH1_SIZE * STM32_FLASH_SIZE_SCALE
}
};
/* The descriptors for 256k device. */
static const flash_descriptor_t efl_lld_size2[STM32_FLASH_NUMBER_OF_BANKS] = {
{ /* Single bank organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH2_SECTORS_TOTAL,
.sectors = efl_lld_sect2,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH2_SIZE * STM32_FLASH_SIZE_SCALE
}
};
/* The descriptors for 384k device. */
static const flash_descriptor_t efl_lld_size3[STM32_FLASH_NUMBER_OF_BANKS] = {
{ /* Single bank organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH3_SECTORS_TOTAL,
.sectors = efl_lld_sect3,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH3_SIZE * STM32_FLASH_SIZE_SCALE
}
};
/* The descriptors for 512k device. */
static const flash_descriptor_t efl_lld_size4[STM32_FLASH_NUMBER_OF_BANKS] = {
{ /* Single bank organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH4_SECTORS_TOTAL,
.sectors = efl_lld_sect4,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH4_SIZE * STM32_FLASH_SIZE_SCALE
}
};
/* Table describing possible flash sizes and descriptors for this device. */
static const efl_lld_size_t efl_lld_flash_sizes[] = {
{
.desc = efl_lld_size1
},
{
.desc = efl_lld_size2
},
{
.desc = efl_lld_size3
},
{
.desc = efl_lld_size4
}
};
#elif defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
defined(__DOXYGEN__)
/* Sector table for 1M device in SBM. */
static const flash_sector_descriptor_t efl_lld_sect_1m_sbm[STM32_FLASH_SECTORS_TOTAL_1M_SBM] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
{ 4 * 16384 + 1 * 65536, 131072}, /* Sector 5. */
{ 4 * 16384 + 1 * 65536 + 1 * 131072, 131072}, /* Sector 6. */
{ 4 * 16384 + 1 * 65536 + 2 * 131072, 131072}, /* Sector 7. */
{ 4 * 16384 + 1 * 65536 + 3 * 131072, 131072}, /* Sector 8. */
{ 4 * 16384 + 1 * 65536 + 4 * 131072, 131072}, /* Sector 9. */
{ 4 * 16384 + 1 * 65536 + 5 * 131072, 131072}, /* Sector 10. */
{ 4 * 16384 + 1 * 65536 + 6 * 131072, 131072} /* Sector 11. */
};
/* Sector table for 1M device in DBM. */
static const flash_sector_descriptor_t efl_lld_sect_1m_dbm[STM32_FLASH_SECTORS_TOTAL_1M_DBM] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
{ 4 * 16384 + 1 * 65536, 131072}, /* Sector 5. */
{ 4 * 16384 + 1 * 65536 + 1 * 131072, 131072}, /* Sector 6. */
{ 4 * 16384 + 1 * 65536 + 2 * 131072, 131072}, /* Sector 7. */
{ 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */
{ 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */
{ 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */
{ 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */
{ 4 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 12. */
{ 5 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 13. */
{ 6 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 14. */
{ 7 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 15. */
{ 8 * 16384 + 1 * 65536 + 3 * 131072, 65536}, /* Sector 16. */
{ 8 * 16384 + 2 * 65536 + 3 * 131072, 131072}, /* Sector 17. */
{ 8 * 16384 + 2 * 65536 + 4 * 131072, 131072}, /* Sector 18. */
{ 8 * 16384 + 2 * 65536 + 5 * 131072, 131072} /* Sector 19. */
};
/* Sector table for 2M device banks. */
static const flash_sector_descriptor_t efl_lld_sect_2m[STM32_FLASH_SECTORS_TOTAL_2M] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
{ 4 * 16384 + 1 * 65536, 131072}, /* Sector 5. */
{ 4 * 16384 + 1 * 65536 + 1 * 131072, 131072}, /* Sector 6. */
{ 4 * 16384 + 1 * 65536 + 2 * 131072, 131072}, /* Sector 7. */
{ 4 * 16384 + 1 * 65536 + 3 * 131072, 131072}, /* Sector 8. */
{ 4 * 16384 + 1 * 65536 + 4 * 131072, 131072}, /* Sector 9. */
{ 4 * 16384 + 1 * 65536 + 5 * 131072, 131072}, /* Sector 10. */
{ 4 * 16384 + 1 * 65536 + 6 * 131072, 131072}, /* Sector 11. */
{ 4 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 12. */
{ 5 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 13. */
{ 6 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 14. */
{ 7 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 15. */
{ 8 * 16384 + 1 * 65536 + 7 * 131072, 65536}, /* Sector 16. */
{ 8 * 16384 + 2 * 65536 + 7 * 131072, 131072}, /* Sector 17. */
{ 8 * 16384 + 2 * 65536 + 8 * 131072, 131072}, /* Sector 18. */
{ 8 * 16384 + 2 * 65536 + 9 * 131072, 131072}, /* Sector 19. */
{ 8 * 16384 + 2 * 65536 + 10 * 131072, 131072}, /* Sector 20. */
{ 8 * 16384 + 2 * 65536 + 11 * 131072, 131072}, /* Sector 21. */
{ 8 * 16384 + 2 * 65536 + 12 * 131072, 131072}, /* Sector 22. */
{ 8 * 16384 + 2 * 65536 + 13 * 131072, 131072} /* Sector 23. */
};
/* The descriptors for 1M device. */
static const flash_descriptor_t efl_lld_size_1m[STM32_FLASH_NUMBER_OF_BANKS] = {
{ /* Bank 1 (SBM) organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH_SECTORS_TOTAL_1M_SBM,
.sectors = efl_lld_sect_1m_sbm,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH_SIZE_1M * STM32_FLASH_SIZE_SCALE
},
{ /* Bank 1 & 2 (DBM) organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH_SECTORS_TOTAL_1M_DBM,
.sectors = efl_lld_sect_1m_dbm,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH_SIZE_1M * STM32_FLASH_SIZE_SCALE
}
};
/* The descriptors for 2M device. */
static const flash_descriptor_t efl_lld_size_2m[STM32_FLASH_NUMBER_OF_BANKS] = {
{ /* Dual bank organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH_SECTORS_TOTAL_2M,
.sectors = efl_lld_sect_2m,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH_SIZE_2M * STM32_FLASH_SIZE_SCALE
},
{ /* Dual bank organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH_SECTORS_TOTAL_2M,
.sectors = efl_lld_sect_2m,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH_SIZE_2M * STM32_FLASH_SIZE_SCALE
}
};
/* Table describing possible flash sizes and descriptors for this device. */
static const efl_lld_size_t efl_lld_flash_sizes[] = {
{
.desc = efl_lld_size_1m
},
{
.desc = efl_lld_size_2m
}
};
#else
#error "This EFL driver does not support the selected device"
#endif
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void stm32_flash_lock(EFlashDriver *eflp) {
eflp->flash->CR |= FLASH_CR_LOCK;
}
static inline void stm32_flash_unlock(EFlashDriver *eflp) {
eflp->flash->KEYR |= FLASH_KEY1;
eflp->flash->KEYR |= FLASH_KEY2;
}
static inline void stm32_flash_enable_pgm(EFlashDriver *eflp) {
/* Set parallelism. */
eflp->flash->CR &= ~FLASH_CR_PSIZE;
eflp->flash->CR |= STM32_FLASH_PSIZE << FLASH_CR_PSIZE_Pos;
/* Enable programming. */
eflp->flash->CR |= FLASH_CR_PG;
}
static inline void stm32_flash_disable_pgm(EFlashDriver *eflp) {
eflp->flash->CR &= ~FLASH_CR_PG;
}
static inline void stm32_flash_clear_status(EFlashDriver *eflp) {
eflp->flash->SR = 0x0000FFFFU;
}
static inline void stm32_flash_wait_busy(EFlashDriver *eflp) {
/* Wait for busy bit clear.*/
while ((eflp->flash->SR & FLASH_SR_BSY) != 0U) {
}
}
static inline size_t stm32_flash_get_size(void) {
return *(uint16_t*)((uint32_t) STM32_FLASH_SIZE_REGISTER) * STM32_FLASH_SIZE_SCALE;
}
static inline bool stm32_flash_dual_bank(EFlashDriver *eflp) {
#if STM32_FLASH_NUMBER_OF_BANKS > 1
return ((eflp->flash->OPTCR & FLASH_OPTCR_DB1M) != 0U || STM32_FLASH_DUAL_BANK_PERMANENT);
#endif
(void)eflp;
return false;
}
static inline flash_error_t stm32_flash_check_errors(EFlashDriver *eflp) {
uint32_t sr = eflp->flash->SR;
/* Clearing error conditions.*/
eflp->flash->SR = sr & 0x0000FFFFU;
/* Some errors are only caught by assertion.*/
osalDbgAssert((sr & 0) == 0U, "unexpected flash error");
/* Decoding relevant errors.*/
if ((sr & FLASH_SR_WRPERR) != 0U) {
return FLASH_ERROR_HW_FAILURE;
}
if ((sr & (FLASH_SR_PGAERR | FLASH_SR_PGPERR | FLASH_SR_OPERR)) != 0U) {
return eflp->state == FLASH_PGM ? FLASH_ERROR_PROGRAM : FLASH_ERROR_ERASE;
}
return FLASH_NO_ERROR;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level Embedded Flash driver initialization.
*
* @notapi
*/
void efl_lld_init(void) {
/* Driver initialization.*/
eflObjectInit(&EFLD1);
EFLD1.flash = FLASH;
/* Find the size of the flash and set descriptor reference. */
uint8_t i;
for (i = 0; i < (sizeof(efl_lld_flash_sizes) / sizeof(efl_lld_size_t)); i++) {
if (efl_lld_flash_sizes[i].desc->size == stm32_flash_get_size()) {
EFLD1.descriptor = efl_lld_flash_sizes[i].desc;
if (stm32_flash_dual_bank(&EFLD1)) {
/* Point to the dual bank descriptor. */
EFLD1.descriptor++;
}
return;
}
}
osalDbgAssert(false, "invalid flash configuration");
}
/**
* @brief Configures and activates the Embedded Flash peripheral.
*
* @param[in] eflp pointer to a @p EFlashDriver structure
*
* @notapi
*/
void efl_lld_start(EFlashDriver *eflp) {
stm32_flash_unlock(eflp);
FLASH->CR = 0x00000000U;
}
/**
* @brief Deactivates the Embedded Flash peripheral.
*
* @param[in] eflp pointer to a @p EFlashDriver structure
*
* @notapi
*/
void efl_lld_stop(EFlashDriver *eflp) {
stm32_flash_lock(eflp);
}
/**
* @brief Gets the flash descriptor structure.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @return A flash device descriptor.
* @retval Pointer to single bank if DBM not enabled.
* @retval Pointer to bank1 if DBM enabled.
*
* @notapi
*/
const flash_descriptor_t *efl_lld_get_descriptor(void *instance) {
EFlashDriver *devp = (EFlashDriver *)instance;
return devp->descriptor;
}
/**
* @brief Read operation.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @param[in] offset offset within full flash address space
* @param[in] n number of bytes to be read
* @param[out] rp pointer to the data buffer
* @return An error code.
* @retval FLASH_NO_ERROR if there is no erase operation in progress.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_READ if the read operation failed.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @notapi
*/
flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
size_t n, uint8_t *rp) {
EFlashDriver *devp = (EFlashDriver *)instance;
flash_error_t err = FLASH_NO_ERROR;
osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U));
const flash_descriptor_t *bank = efl_lld_get_descriptor(instance);
osalDbgCheck((size_t)offset + n <= (size_t)bank->size);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
/* No reading while erasing.*/
if (devp->state == FLASH_ERASE) {
return FLASH_BUSY_ERASING;
}
/* FLASH_READ state while the operation is performed.*/
devp->state = FLASH_READ;
/* Clearing error status bits.*/
stm32_flash_clear_status(devp);
/* Actual read implementation.*/
memcpy((void *)rp, (const void *)efl_lld_get_descriptor(instance)->address
+ offset, n);
#if defined(FLASH_CR_RDERR)
/* Checking for errors after reading.*/
if ((devp->flash->SR & FLASH_SR_RDERR) != 0U) {
err = FLASH_ERROR_READ;
}
#endif
/* Ready state again.*/
devp->state = FLASH_READY;
return err;
}
/**
* @brief Program operation.
* @note Successive write operations are possible without the need of
* an erase when changing bits from one to zero. Writing one requires
* an erase operation.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @param[in] offset offset within full flash address space
* @param[in] n number of bytes to be programmed
* @param[in] pp pointer to the data buffer
* @return An error code.
* @retval FLASH_NO_ERROR if there is no erase operation in progress.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_PROGRAM if the program operation failed.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @notapi
*/
flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
size_t n, const uint8_t *pp) {
EFlashDriver *devp = (EFlashDriver *)instance;
const flash_descriptor_t *bank = efl_lld_get_descriptor(instance);
flash_error_t err = FLASH_NO_ERROR;
osalDbgCheck((instance != NULL) && (pp != NULL) && (n > 0U));
osalDbgCheck((size_t)offset + n <= (size_t)bank->size);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
/* No programming while erasing.*/
if (devp->state == FLASH_ERASE) {
return FLASH_BUSY_ERASING;
}
/* FLASH_PGM state while the operation is performed.*/
devp->state = FLASH_PGM;
/* Clearing error status bits.*/
stm32_flash_clear_status(devp);
/* Enabling PGM mode in the controller.*/
stm32_flash_enable_pgm(devp);
/* Actual program implementation.*/
while (n > 0U) {
volatile uint32_t *address;
/* Create an array of sufficient size to hold line(s). */
union {
uint32_t w[STM32_FLASH_LINE_SIZE / sizeof(uint32_t)];
uint16_t h[STM32_FLASH_LINE_SIZE / sizeof(uint16_t)];
uint8_t b[STM32_FLASH_LINE_SIZE / sizeof(uint8_t)];
} line;
/* Unwritten bytes are initialized to all ones.*/
uint8_t i;
for (i = 0; i < bank->page_size; i++) {
line.b[i] = 0xFF;
}
/* Programming address aligned to flash lines.*/
address = (volatile uint32_t *)(bank->address +
(offset & ~STM32_FLASH_LINE_MASK));
/* Copying data inside the prepared line(s).*/
do {
line.b[offset & STM32_FLASH_LINE_MASK] = *pp;
offset++;
n--;
pp++;
}
while ((n > 0U) & ((offset & STM32_FLASH_LINE_MASK) != 0U));
/* Programming line according to parallelism.*/
switch (STM32_FLASH_LINE_SIZE) {
case 1:
address[0] = line.b[0];
break;
case 2:
address[0] = line.h[0];
break;
case 4:
address[0] = line.w[0];
break;
case 8:
address[0] = line.w[0];
address[1] = line.w[1];
break;
default:
osalDbgAssert(false, "invalid line size");
break;
}
stm32_flash_wait_busy(devp);
err = stm32_flash_check_errors(devp);
if (err != FLASH_NO_ERROR) {
break;
}
}
/* Disabling PGM mode in the controller.*/
stm32_flash_disable_pgm(devp);
/* Ready state again.*/
devp->state = FLASH_READY;
return err;
}
/**
* @brief Starts a whole-device erase operation.
* @note This function only erases the unused bank if in dual bank mode. The
* currently in use bank is not allowed since it is normally where the
* currently running program is executing from.
* Sectors on the in-use bank can be individually erased.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @return An error code.
* @retval FLASH_NO_ERROR if there is no erase operation in progress.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @notapi
*/
flash_error_t efl_lld_start_erase_all(void *instance) {
EFlashDriver *devp = (EFlashDriver *)instance;
osalDbgCheck(instance != NULL);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
/* No erasing while erasing.*/
if (devp->state == FLASH_ERASE) {
return FLASH_BUSY_ERASING;
}
#if defined(FLASH_CR_MER2)
/* If dual bank is active then mass erase bank2. */
if (stm32_flash_dual_bank(devp)) {
/* FLASH_ERASE state while the operation is performed.*/
devp->state = FLASH_ERASE;
/* Clearing error status bits.*/
stm32_flash_clear_status(devp);
/* Erase the currently unused bank, based on Flash Bank Mode */
if ((SYSCFG->MEMRMP & SYSCFG_MEMRMP_UFB_MODE) != 0U) {
/* Bank 2 in use, erase Bank 1 */
devp->flash->CR |= FLASH_CR_MER;
}
else {
/* Bank 1 in use, erase Bank 2 */
devp->flash->CR |= FLASH_CR_MER2;
}
devp->flash->CR |= FLASH_CR_STRT;
return FLASH_NO_ERROR;
}
#endif
/* Mass erase not allowed. */
return FLASH_ERROR_UNIMPLEMENTED;
}
/**
* @brief Starts an sector erase operation.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @param[in] sector sector to be erased
* this is an index within the total sectors
* in a flash bank
* @return An error code.
* @retval FLASH_NO_ERROR if there is no erase operation in progress.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @notapi
*/
flash_error_t efl_lld_start_erase_sector(void *instance,
flash_sector_t sector) {
EFlashDriver *devp = (EFlashDriver *)instance;
const flash_descriptor_t *bank = efl_lld_get_descriptor(instance);
osalDbgCheck(instance != NULL);
osalDbgCheck(sector < bank->sectors_count);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
/* No erasing while erasing.*/
if (devp->state == FLASH_ERASE) {
return FLASH_BUSY_ERASING;
}
/* FLASH_PGM state while the operation is performed.*/
devp->state = FLASH_ERASE;
/* Clearing error status bits.*/
stm32_flash_clear_status(devp);
/* Enable sector erase.*/
devp->flash->CR |= FLASH_CR_SER;
/* Mask off the sector and parallelism selection bits.*/
devp->flash->CR &= ~FLASH_CR_SNB;
devp->flash->CR &= ~FLASH_CR_PSIZE;
#if defined(FLASH_CR_MER2)
/* Adjust sector value for dual-bank devices
* For STM32F42x_43x devices (dual-bank), FLASH_CR_SNB values jump to 0b10000
* for sectors 12 and up.
*/
if (sector >= 12) {
sector -= 12;
sector |= 0x10U;
}
#endif
/* Set sector and parallelism. */
devp->flash->CR |= (sector << FLASH_CR_SNB_Pos) |
(STM32_FLASH_PSIZE << FLASH_CR_PSIZE_Pos);
/* Start the erase.*/
devp->flash->CR |= FLASH_CR_STRT;
return FLASH_NO_ERROR;
}
/**
* @brief Queries the driver for erase operation progress.
*
* @param[in] instance pointer to a @p EFlashDriver instance
* @param[out] msec recommended time, in milliseconds, that
* should be spent before calling this
* function again, can be @p NULL
* @return An error code.
* @retval FLASH_NO_ERROR if there is no erase operation in progress.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_ERASE if the erase operation failed.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @api
*/
flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) {
EFlashDriver *devp = (EFlashDriver *)instance;
flash_error_t err;
/* If there is an erase in progress then the device must be checked.*/
if (devp->state == FLASH_ERASE) {
/* Checking for operation in progress.*/
if ((devp->flash->SR & FLASH_SR_BSY) == 0U) {
/* Disabling the various erase control bits.*/
devp->flash->CR &= ~(FLASH_CR_MER |
#if defined(FLASH_CR_MER2)
FLASH_CR_MER2 |
#endif
FLASH_CR_SER);
/* No operation in progress, checking for errors.*/
err = stm32_flash_check_errors(devp);
/* Back to ready state.*/
devp->state = FLASH_READY;
}
else {
/* Recommended time before polling again. This is a simplified
implementation.*/
if (msec != NULL) {
*msec = (uint32_t)STM32_FLASH_WAIT_TIME_MS;
}
err = FLASH_BUSY_ERASING;
}
}
else {
err = FLASH_NO_ERROR;
}
return err;
}
/**
* @brief Returns the erase state of a sector.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @param[in] sector sector to be verified
* @return An error code.
* @retval FLASH_NO_ERROR if the sector is erased.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_VERIFY if the verify operation failed.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @notapi
*/
flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) {
EFlashDriver *devp = (EFlashDriver *)instance;
uint32_t *address;
const flash_descriptor_t *bank = efl_lld_get_descriptor(instance);
flash_error_t err = FLASH_NO_ERROR;
unsigned i;
osalDbgCheck(instance != NULL);
osalDbgCheck(sector < bank->sectors_count);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
/* No verifying while erasing.*/
if (devp->state == FLASH_ERASE) {
return FLASH_BUSY_ERASING;
}
/* Address of the sector in the bank.*/
address = (uint32_t *)(bank->address +
flashGetSectorOffset(getBaseFlash(devp), sector));
/* FLASH_READ state while the operation is performed.*/
devp->state = FLASH_READ;
/* Scanning the sector space.*/
uint32_t sector_size = flashGetSectorSize(getBaseFlash(devp), sector);
for (i = 0U; i < sector_size / sizeof(uint32_t); i++) {
if (*address != 0xFFFFFFFFU) {
err = FLASH_ERROR_VERIFY;
break;
}
address++;
}
/* Ready state again.*/
devp->state = FLASH_READY;
return err;
}
#endif /* HAL_USE_EFL == TRUE */
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_efl_lld.h
* @brief STM32F4xx Embedded Flash subsystem low level driver header.
*
* @addtogroup HAL_EFL
* @{
*/
#ifndef HAL_EFL_LLD_H
#define HAL_EFL_LLD_H
#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name STM32F412/413 EFL driver configuration options
* @{
*/
/**
* @brief Suggested wait time during erase operations polling.
*/
#if !defined(STM32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__)
#define STM32_FLASH_WAIT_TIME_MS 5
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if defined(STM32F413xx) || defined(STM32F412xx) || \
defined(STM32F40_41xxx) || defined(__DOXYGEN__)
/* Flash size register. */
#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22
#define STM32_FLASH_SIZE_SCALE 1024U
/*
* Device flash size...
*
*/
#define STM32_FLASH_NUMBER_OF_BANKS 1
#define STM32_FLASH1_SIZE 1536U
#define STM32_FLASH2_SIZE 1024U
#define STM32_FLASH1_SECTORS_TOTAL 16
#define STM32_FLASH2_SECTORS_TOTAL 12
#elif defined(STM32F401xx) || defined(STM32F411xx) || \
defined(__DOXYGEN__)
/* Flash size register. */
#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22
#define STM32_FLASH_SIZE_SCALE 1024U
/*
* Device flash size...
*
*/
#define STM32_FLASH_NUMBER_OF_BANKS 1
#define STM32_FLASH1_SIZE 128U
#define STM32_FLASH2_SIZE 512U
#define STM32_FLASH3_SIZE 384U
#define STM32_FLASH4_SIZE 512U
#define STM32_FLASH1_SECTORS_TOTAL 5
#define STM32_FLASH2_SECTORS_TOTAL 6
#define STM32_FLASH3_SECTORS_TOTAL 7
#define STM32_FLASH4_SECTORS_TOTAL 8
#elif defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
defined(__DOXYGEN__)
/* Flash size register. */
#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22
#define STM32_FLASH_SIZE_SCALE 1024U
/*
* Device flash size is:
* 1M for STM32F4x7/4x9 suffix G devices
* 2M for STM32F4x7/4x9 suffix I devices.
*
* For 1M devices SBM is organised as 16K x 4 + 64K + 128K x 7 sectors.
* For 1M devices DBM is organised as 16K x 4 + 64K + 128K x 3 sectors per bank.
*
* For 2M devices are organised as 16K x 4 + 64K + 128K x 7 sectors per bank.
*/
#define STM32_FLASH_NUMBER_OF_BANKS 2
#define STM32_FLASH_SIZE_1M 1024U
#define STM32_FLASH_SIZE_2M 2048U
#define STM32_FLASH_SECTORS_TOTAL_1M_SBM 12
#define STM32_FLASH_SECTORS_TOTAL_1M_DBM 20
#define STM32_FLASH_SECTORS_TOTAL_2M 24
#else
#error "This EFL driver does not support the selected device"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/* A flash size declaration. */
typedef struct {
const flash_descriptor_t* desc;
} efl_lld_size_t;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Low level fields of the embedded flash driver structure.
*/
#define efl_lld_driver_fields \
/* Flash registers.*/ \
FLASH_TypeDef *flash; \
const flash_descriptor_t *descriptor;
/**
* @brief Low level fields of the embedded flash configuration structure.
*/
#define efl_lld_config_fields \
/* Dummy configuration, it is not needed.*/ \
uint32_t dummy
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern EFlashDriver EFLD1;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void efl_lld_init(void);
void efl_lld_start(EFlashDriver *eflp);
void efl_lld_stop(EFlashDriver *eflp);
const flash_descriptor_t *efl_lld_get_descriptor(void *instance);
flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
size_t n, uint8_t *rp);
flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
size_t n, const uint8_t *pp);
flash_error_t efl_lld_start_erase_all(void *instance);
flash_error_t efl_lld_start_erase_sector(void *instance,
flash_sector_t sector);
flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec);
flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_EFL == TRUE */
#endif /* HAL_EFL_LLD_H */
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F4xx/hal_lld.c
* @brief STM32F4xx/STM32F2xx HAL subsystem low level driver source.
*
* @addtogroup HAL
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/**
* @brief CMSIS system core clock variable.
* @note It is declared in system_stm32f4xx.h.
*/
uint32_t SystemCoreClock = STM32_HCLK;
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief Initializes the backup domain.
* @note WARNING! Changing clock source impossible without resetting
* of the whole BKP domain.
*/
static void hal_lld_backup_domain_init(void) {
/* Backup domain access enabled and left open.*/
PWR->CR |= PWR_CR_DBP;
/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0;
}
#if STM32_LSE_ENABLED
#if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/
RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else
/* No LSE Bypass.*/
RCC->BDCR |= RCC_BDCR_LSEON;
#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
#endif
#if HAL_USE_RTC
/* If the backup domain hasn't been initialized yet then proceed with
initialization.*/
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/
RCC->BDCR |= STM32_RTCSEL;
/* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
}
#endif /* HAL_USE_RTC */
#if STM32_BKPRAM_ENABLE
rccEnableBKPSRAM(true);
PWR->CSR |= PWR_CSR_BRE;
while ((PWR->CSR & PWR_CSR_BRR) == 0)
; /* Waits until the regulator is stable */
#else
PWR->CSR &= ~PWR_CSR_BRE;
#endif /* STM32_BKPRAM_ENABLE */
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
/* Reset of all peripherals. AHB3 is not reseted because it could have
been initialized in the board initialization file (board.c).
Note, GPIOs are not reset because initialized before this point in
board files.*/
rccResetAHB1(~STM32_GPIO_EN_MASK);
#if !defined(STM32F410xx)
rccResetAHB2(~0);
#endif
rccResetAPB1(~RCC_APB1RSTR_PWRRST);
rccResetAPB2(~0);
/* PWR clock enabled.*/
rccEnablePWRInterface(true);
/* Initializes the backup domain.*/
hal_lld_backup_domain_init();
/* DMA subsystems initialization.*/
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
/* IRQ subsystem initialization.*/
irqInit();
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
#endif /* STM32_PVD_ENABLE */
}
/**
* @brief STM32F2xx clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function should be invoked just after the system reset.
*
* @special
*/
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* PWR clock enable.*/
#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR_RTCAPBEN)
RCC->APB1ENR = RCC_APB1ENR_PWREN | RCC_APB1ENR_RTCAPBEN;
#else
RCC->APB1ENR = RCC_APB1ENR_PWREN;
#endif
/* PWR initialization.*/
#if defined(STM32F4XX) || defined(__DOXYGEN__)
PWR->CR = STM32_VOS;
#else
PWR->CR = 0;
#endif
/* HSI setup, it enforces the reset situation in order to handle possible
problems with JTAG probes and re-initializations.*/
RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
while (!(RCC->CR & RCC_CR_HSIRDY))
; /* Wait until HSI is stable. */
/* HSI is selected as new source without touching the other fields in
CFGR. Clearing the register has to be postponed after HSI is the
new source.*/
RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW, selecting HSI. */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
; /* Wait until HSI is selected. */
/* Registers finally cleared to reset values.*/
RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
RCC->CFGR = 0; /* CFGR reset value. */
#if STM32_HSE_ENABLED
/* HSE activation.*/
#if defined(STM32_HSE_BYPASS)
/* HSE Bypass.*/
RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
#else
/* No HSE Bypass.*/
RCC->CR |= RCC_CR_HSEON;
#endif
while ((RCC->CR & RCC_CR_HSERDY) == 0)
; /* Waits until HSE is stable. */
#endif
#if STM32_LSI_ENABLED
/* LSI activation.*/
RCC->CSR |= RCC_CSR_LSION;
while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
; /* Waits until LSI is stable. */
#endif
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |
STM32_PLLM;
RCC->CR |= RCC_CR_PLLON;
/* Artery */
#if 0
/* Synchronization with voltage regulator stabilization.*/
#if defined(STM32F4XX)
while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
; /* Waits until power regulator is stable. */
#if STM32_OVERDRIVE_REQUIRED
/* Overdrive activation performed after activating the PLL in order to save
time as recommended in RM in "Entering Over-drive mode" paragraph.*/
PWR->CR |= PWR_CR_ODEN;
while (!(PWR->CSR & PWR_CSR_ODRDY))
;
PWR->CR |= PWR_CR_ODSWEN;
while (!(PWR->CSR & PWR_CSR_ODSWRDY))
;
#endif /* STM32_OVERDRIVE_REQUIRED */
#endif /* defined(STM32F4XX) */
#endif
/* Waiting for PLL lock.*/
while (!(RCC->CR & RCC_CR_PLLRDY))
;
#endif /* STM32_ACTIVATE_PLL */
#if STM32_ACTIVATE_PLLI2S
/* PLLI2S activation.*/
RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN | STM32_PLLI2SP |
STM32_PLLI2SSRC | STM32_PLLI2SQ | STM32_PLLI2SM;
RCC->CR |= RCC_CR_PLLI2SON;
/* Waiting for PLL lock.*/
while (!(RCC->CR & RCC_CR_PLLI2SRDY))
;
#endif /* STM32_ACTIVATE_PLLI2S */
#if STM32_ACTIVATE_PLLSAI
/* PLLSAI activation.*/
RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIN | STM32_PLLSAIP |
STM32_PLLSAIQ | STM32_PLLSAIM;
RCC->CR |= RCC_CR_PLLSAION;
/* Waiting for PLL lock.*/
while (!(RCC->CR & RCC_CR_PLLSAIRDY))
;
#endif /* STM32_ACTIVATE_PLLSAI */
/* Other clock-related settings (dividers, MCO etc).*/
#if !defined(STM32F413xx)
RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
STM32_I2SSRC | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
STM32_HPRE;
#else
RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
STM32_HPRE;
#endif
#if STM32_HAS_RCC_DCKCFGR
/* DCKCFGR register initialization, note, must take care of the _OFF
pseudo settings.*/
{
uint32_t dckcfgr = 0;
#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
dckcfgr |= STM32_SAI2SEL;
#endif
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
dckcfgr |= STM32_SAI1SEL;
#endif
#if (STM32_ACTIVATE_PLLSAI == TRUE) && \
(STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF)
dckcfgr |= STM32_PLLSAIDIVR;
#endif
#if defined(STM32F469xx) || defined(STM32F479xx)
/* Special case, in those devices STM32_CK48MSEL is located in the
DCKCFGR register.*/
dckcfgr |= STM32_CK48MSEL;
#endif
#if !defined(STM32F413xx)
RCC->DCKCFGR = dckcfgr |
STM32_TIMPRE | STM32_PLLSAIDIVQ | STM32_PLLI2SDIVQ;
#else
RCC->DCKCFGR = dckcfgr |
STM32_TIMPRE | STM32_PLLDIVR | STM32_PLLI2SDIVR;
#endif
}
#endif
#if STM32_HAS_RCC_DCKCFGR2
/* DCKCFGR2 register initialization.*/
RCC->DCKCFGR2 = STM32_CK48MSEL;
#endif
#if 0
/* Flash setup.*/
#if !defined(STM32_REMOVE_REVISION_A_FIX)
/* Some old revisions of F4x MCUs randomly crashes with compiler
optimizations enabled AND flash caches enabled. */
if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241))
FLASH->ACR = FLASH_ACR_PRFTEN | STM32_FLASHBITS;
else
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
FLASH_ACR_DCEN | STM32_FLASHBITS;
#else
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
FLASH_ACR_DCEN | STM32_FLASHBITS;
#endif
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
(STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
}
#endif
/* Switching to the configured clock source if it is different from HSI.*/
#if (STM32_SW != STM32_SW_HSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
#endif
#endif /* STM32_NO_INIT */
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
}
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F4xx/hal_lld.h
* @brief STM32F4xx/STM32F2xx HAL subsystem low level driver header.
*
* @addtogroup HAL
* @{
*/
#ifndef HAL_LLD_H
#define HAL_LLD_H
#include "at32_registry.h"
#if defined(STM32F413xx)
#include "hal_lld_type2.h"
#else
#include "hal_lld_type1.h"
#endif
/* Various helpers.*/
#include "nvic.h"
#include "cache.h"
#include "mpu_v7m.h"
#include "at32_isr.h"
#include "stm32_dma.h"
#include "stm32_exti.h"
#include "at32_rcc.h"
#include "stm32_tim.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @brief Requires use of SPIv2 driver model.
*/
#define HAL_LLD_SELECT_SPI_V2 TRUE
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/**
* @brief MCO1 divider clock.
*/
#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)
#define STM32_MCO1DIVCLK STM32_HSICLK
#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE
#define STM32_MCO1DIVCLK STM32_LSECLK
#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE
#define STM32_MCO1DIVCLK STM32_HSECLK
#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL
#define STM32_MCO1DIVCLK STM32_PLLCLKOUT
#else
#error "invalid STM32_MCO1SEL value specified"
#endif
/**
* @brief MCO1 output pin clock.
*/
#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)
#define STM32_MCO1CLK STM32_MCO1DIVCLK
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2)
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3)
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4)
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5)
#else
#error "invalid STM32_MCO1PRE value specified"
#endif
/**
* @brief MCO2 divider clock.
*/
#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)
#define STM32_MCO2DIVCLK STM32_HSECLK
#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL
#define STM32_MCO2DIVCLK STM32_PLLCLKOUT
#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
#define STM32_MCO2DIVCLK STM32_SYSCLK
#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S
#define STM32_MCO2DIVCLK STM32_PLLI2S
#else
#error "invalid STM32_MCO2SEL value specified"
#endif
/**
* @brief MCO2 output pin clock.
*/
#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
#define STM32_MCO2CLK STM32_MCO2DIVCLK
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5)
#else
#error "invalid STM32_MCO2PRE value specified"
#endif
/**
* @brief RTC HSE divider setting.
*/
#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
defined(__DOXYGEN__)
#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16)
#else
#error "invalid STM32_RTCPRE value specified"
#endif
/**
* @brief HSE divider toward RTC clock.
*/
#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
defined(__DOXYGEN__)
#define STM32_HSEDIVCLK (STM32_HSECLK / STM32_RTCPRE_VALUE)
#else
#error "invalid STM32_RTCPRE value specified"
#endif
/**
* @brief RTC clock.
*/
#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
#define STM32_RTCCLK 0
#elif STM32_RTCSEL == STM32_RTCSEL_LSE
#define STM32_RTCCLK STM32_LSECLK
#elif STM32_RTCSEL == STM32_RTCSEL_LSI
#define STM32_RTCCLK STM32_LSICLK
#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
#define STM32_RTCCLK STM32_HSEDIVCLK
#else
#error "invalid STM32_RTCSEL value specified"
#endif
/**
* @brief 48MHz frequency.
*/
#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__)
#if STM32_HAS_RCC_CK48MSEL || defined(__DOXYGEN__)
#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)
#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLALT
#define STM32_PLL48CLK STM32_PLL48CLK_ALTSRC
#else
#error "invalid source selected for PLL48CLK clock"
#endif
#else /* !STM32_HAS_RCC_CK48MSEL */
#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
#endif /* !STM32_HAS_RCC_CK48MSEL */
#else /* !STM32_CLOCK48_REQUIRED */
#define STM32_PLL48CLK 0
#endif /* STM32_CLOCK48_REQUIRED */
#if !STM32_HAS_RCC_DCKCFGR || (STM32_TIMPRE == STM32_TIMPRE_PCLK) || \
defined(__DOXYGEN__)
/**
* @brief Clock of timers connected to APB1
* (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14).
*/
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
#else
#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
#endif
/**
* @brief Clock of timers connected to APB2 (Timers 1, 8, 9, 10, 11).
*/
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
#else
#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
#endif
#else /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || \
(STM32_PPRE1 == STM32_PPRE1_DIV2) || \
((STM32_PPRE1 == STM32_PPRE1_DIV4) && \
(STM32_TIMPRE_PRESCALE4 == TRUE)) || defined(__DOXYGEN__)
#define STM32_TIMCLK1 STM32_HCLK
#else
#define STM32_TIMCLK1 (STM32_PCLK1 * 4)
#endif
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || \
(STM32_PPRE2 == STM32_PPRE2_DIV2) || \
((STM32_PPRE2 == STM32_PPRE2_DIV4) && \
(STM32_TIMPRE_PRESCALE4 == TRUE)) || defined(__DOXYGEN__)
#define STM32_TIMCLK2 STM32_HCLK
#else
#define STM32_TIMCLK2 (STM32_PCLK2 * 4)
#endif
#endif /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */
/**
* @brief Flash settings.
*/
#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
#define STM32_FLASHBITS 0x00000000
#elif STM32_HCLK <= STM32_1WS_THRESHOLD
#define STM32_FLASHBITS 0x00000001
#elif STM32_HCLK <= STM32_2WS_THRESHOLD
#define STM32_FLASHBITS 0x00000002
#elif STM32_HCLK <= STM32_3WS_THRESHOLD
#define STM32_FLASHBITS 0x00000003
#elif STM32_HCLK <= STM32_4WS_THRESHOLD
#define STM32_FLASHBITS 0x00000004
#elif STM32_HCLK <= STM32_5WS_THRESHOLD
#define STM32_FLASHBITS 0x00000005
#elif STM32_HCLK <= STM32_6WS_THRESHOLD
#define STM32_FLASHBITS 0x00000006
#elif STM32_HCLK <= STM32_7WS_THRESHOLD
#define STM32_FLASHBITS 0x00000007
#elif STM32_HCLK <= STM32_8WS_THRESHOLD
#define STM32_FLASHBITS 0x00000008
#else
#error "invalid frequency at specified VDD level"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#endif /* HAL_LLD_H */
/** @} */

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# Required platform files.
PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
$(CHIBIOS)/os/hal/ports/AT32/AT32F4xx/at32_isr.c \
$(CHIBIOS)/os/hal/ports/AT32/AT32F4xx/hal_lld.c \
$(CHIBIOS)/os/hal/ports/AT32/AT32F4xx/hal_efl_lld.c
# Required include directories.
PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
$(CHIBIOS)/os/hal/ports/AT32/AT32F4xx
# Optional platform files.
ifeq ($(USE_SMART_BUILD),yes)
# Configuration files directory
ifeq ($(HALCONFDIR),)
ifeq ($(CONFDIR),)
HALCONFDIR = .
else
HALCONFDIR := $(CONFDIR)
endif
endif
HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define"))
else
endif
# Drivers compatible with the platform.
include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/CRYPv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/driver_v2.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
# Shared variables
ALLCSRC += $(PLATFORMSRC)
ALLINC += $(PLATFORMINC)