git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6197 35acf78f-673a-0410-8e92-d51de3d6d3f4
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F4xx/adc_lld.c
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* @brief STM32F4xx/STM32F2xx ADC subsystem low level driver source.
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*
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* @addtogroup ADC
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_ADC || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#define ADC1_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN)
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#define ADC2_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN)
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#define ADC3_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief ADC1 driver identifier.*/
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#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
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ADCDriver ADCD1;
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#endif
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/** @brief ADC2 driver identifier.*/
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#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__)
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ADCDriver ADCD2;
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#endif
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/** @brief ADC3 driver identifier.*/
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#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
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ADCDriver ADCD3;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief ADC DMA ISR service routine.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
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/* DMA errors handling.*/
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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/* DMA, this could help only if the DMA tries to access an unmapped
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address space or violates alignment rules.*/
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_adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
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}
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else {
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/* It is possible that the conversion group has already be reset by the
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ADC error handler, in this case this interrupt is spurious.*/
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if (adcp->grpp != NULL) {
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if ((flags & STM32_DMA_ISR_HTIF) != 0) {
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/* Half transfer processing.*/
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_adc_isr_half_code(adcp);
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}
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if ((flags & STM32_DMA_ISR_TCIF) != 0) {
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/* Transfer complete processing.*/
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_adc_isr_full_code(adcp);
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}
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}
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || STM32_ADC_USE_ADC3 || \
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defined(__DOXYGEN__)
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/**
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* @brief ADC interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
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uint32_t sr;
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CH_IRQ_PROLOGUE();
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#if STM32_ADC_USE_ADC1
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sr = ADC1->SR;
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ADC1->SR = 0;
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/* Note, an overflow may occur after the conversion ended before the driver
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is able to stop the ADC, this is why the DMA channel is checked too.*/
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if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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to read data fast enough.*/
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if (ADCD1.grpp != NULL)
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_adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
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}
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/* TODO: Add here analog watchdog handling.*/
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#endif /* STM32_ADC_USE_ADC1 */
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#if STM32_ADC_USE_ADC2
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sr = ADC2->SR;
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ADC2->SR = 0;
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/* Note, an overflow may occur after the conversion ended before the driver
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is able to stop the ADC, this is why the DMA channel is checked too.*/
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if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD2.dmastp) > 0)) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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to read data fast enough.*/
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if (ADCD2.grpp != NULL)
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_adc_isr_error_code(&ADCD2, ADC_ERR_OVERFLOW);
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}
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/* TODO: Add here analog watchdog handling.*/
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#endif /* STM32_ADC_USE_ADC2 */
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#if STM32_ADC_USE_ADC3
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sr = ADC3->SR;
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ADC3->SR = 0;
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/* Note, an overflow may occur after the conversion ended before the driver
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is able to stop the ADC, this is why the DMA channel is checked too.*/
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if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD3.dmastp) > 0)) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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to read data fast enough.*/
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if (ADCD3.grpp != NULL)
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_adc_isr_error_code(&ADCD3, ADC_ERR_OVERFLOW);
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}
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/* TODO: Add here analog watchdog handling.*/
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#endif /* STM32_ADC_USE_ADC3 */
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CH_IRQ_EPILOGUE();
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}
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#endif
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level ADC driver initialization.
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*
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* @notapi
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*/
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void adc_lld_init(void) {
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#if STM32_ADC_USE_ADC1
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/* Driver initialization.*/
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adcObjectInit(&ADCD1);
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ADCD1.adc = ADC1;
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ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
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ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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#endif
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#if STM32_ADC_USE_ADC2
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/* Driver initialization.*/
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adcObjectInit(&ADCD2);
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ADCD2.adc = ADC2;
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ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
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ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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#endif
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#if STM32_ADC_USE_ADC3
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/* Driver initialization.*/
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adcObjectInit(&ADCD3);
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ADCD3.adc = ADC3;
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ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
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ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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#endif
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/* The shared vector is initialized on driver initialization and never
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disabled.*/
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nvicEnableVector(ADC_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
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}
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/**
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* @brief Configures and activates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_start(ADCDriver *adcp) {
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/* If in stopped state then enables the ADC and DMA clocks.*/
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if (adcp->state == ADC_STOP) {
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#if STM32_ADC_USE_ADC1
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if (&ADCD1 == adcp) {
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bool_t b;
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b = dmaStreamAllocate(adcp->dmastp,
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STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
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(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
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(void *)adcp);
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chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
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dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
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rccEnableADC1(FALSE);
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}
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#endif /* STM32_ADC_USE_ADC1 */
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#if STM32_ADC_USE_ADC2
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if (&ADCD2 == adcp) {
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bool_t b;
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b = dmaStreamAllocate(adcp->dmastp,
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STM32_ADC_ADC2_DMA_IRQ_PRIORITY,
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(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
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(void *)adcp);
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chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated");
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dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR);
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rccEnableADC2(FALSE);
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}
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#endif /* STM32_ADC_USE_ADC2 */
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#if STM32_ADC_USE_ADC3
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if (&ADCD3 == adcp) {
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bool_t b;
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b = dmaStreamAllocate(adcp->dmastp,
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STM32_ADC_ADC3_DMA_IRQ_PRIORITY,
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(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
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(void *)adcp);
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chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated");
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dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR);
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rccEnableADC3(FALSE);
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}
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#endif /* STM32_ADC_USE_ADC3 */
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/* This is a common register but apparently it requires that at least one
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of the ADCs is clocked in order to allow writing, see bug 3575297.*/
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ADC->CCR = (ADC->CCR & (ADC_CCR_TSVREFE | ADC_CCR_VBATE)) |
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(STM32_ADC_ADCPRE << 16);
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/* ADC initial setup, starting the analog part here in order to reduce
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the latency when starting a conversion.*/
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adcp->adc->CR1 = 0;
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adcp->adc->CR2 = 0;
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adcp->adc->CR2 = ADC_CR2_ADON;
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}
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}
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/**
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* @brief Deactivates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_stop(ADCDriver *adcp) {
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/* If in ready state then disables the ADC clock.*/
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if (adcp->state == ADC_READY) {
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dmaStreamRelease(adcp->dmastp);
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adcp->adc->CR1 = 0;
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adcp->adc->CR2 = 0;
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#if STM32_ADC_USE_ADC1
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if (&ADCD1 == adcp)
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rccDisableADC1(FALSE);
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#endif
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#if STM32_ADC_USE_ADC2
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if (&ADCD2 == adcp)
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rccDisableADC2(FALSE);
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#endif
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#if STM32_ADC_USE_ADC3
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if (&ADCD3 == adcp)
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rccDisableADC3(FALSE);
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#endif
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}
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}
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/**
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* @brief Starts an ADC conversion.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_start_conversion(ADCDriver *adcp) {
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uint32_t mode;
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const ADCConversionGroup *grpp = adcp->grpp;
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/* DMA setup.*/
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mode = adcp->dmamode;
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if (grpp->circular) {
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mode |= STM32_DMA_CR_CIRC;
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}
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if (adcp->depth > 1) {
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/* If the buffer depth is greater than one then the half transfer interrupt
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interrupt is enabled in order to allows streaming processing.*/
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mode |= STM32_DMA_CR_HTIE;
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}
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dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
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dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
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(uint32_t)adcp->depth);
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dmaStreamSetMode(adcp->dmastp, mode);
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dmaStreamEnable(adcp->dmastp);
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/* ADC setup.*/
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adcp->adc->SR = 0;
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adcp->adc->SMPR1 = grpp->smpr1;
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adcp->adc->SMPR2 = grpp->smpr2;
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adcp->adc->SQR1 = grpp->sqr1;
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adcp->adc->SQR2 = grpp->sqr2;
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adcp->adc->SQR3 = grpp->sqr3;
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/* ADC configuration and start, the start is performed using the method
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specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
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adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
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if ((grpp->cr2 & ADC_CR2_SWSTART) != 0)
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adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA |
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ADC_CR2_DDS | ADC_CR2_ADON;
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else
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adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA |
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ADC_CR2_DDS | ADC_CR2_ADON;
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}
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/**
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* @brief Stops an ongoing conversion.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_stop_conversion(ADCDriver *adcp) {
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dmaStreamDisable(adcp->dmastp);
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adcp->adc->CR1 = 0;
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adcp->adc->CR2 = 0;
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adcp->adc->CR2 = ADC_CR2_ADON;
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}
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/**
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* @brief Enables the TSVREFE bit.
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* @details The TSVREFE bit is required in order to sample the internal
|
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* temperature sensor and internal reference voltage.
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* @note This is an STM32-only functionality.
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*/
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void adcSTM32EnableTSVREFE(void) {
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ADC->CCR |= ADC_CCR_TSVREFE;
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}
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/**
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* @brief Disables the TSVREFE bit.
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* @details The TSVREFE bit is required in order to sample the internal
|
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* temperature sensor and internal reference voltage.
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* @note This is an STM32-only functionality.
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*/
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void adcSTM32DisableTSVREFE(void) {
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ADC->CCR &= ~ADC_CCR_TSVREFE;
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}
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/**
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* @brief Enables the VBATE bit.
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* @details The VBATE bit is required in order to sample the VBAT channel.
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* @note This is an STM32-only functionality.
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* @note This function is meant to be called after @p adcStart().
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*/
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void adcSTM32EnableVBATE(void) {
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ADC->CCR |= ADC_CCR_VBATE;
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}
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/**
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* @brief Disables the VBATE bit.
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* @details The VBATE bit is required in order to sample the VBAT channel.
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* @note This is an STM32-only functionality.
|
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* @note This function is meant to be called after @p adcStart().
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*/
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void adcSTM32DisableVBATE(void) {
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ADC->CCR &= ~ADC_CCR_VBATE;
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||||
}
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||||
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#endif /* HAL_USE_ADC */
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||||
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/** @} */
|
|
@ -0,0 +1,567 @@
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/*
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||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F4xx/adc_lld.h
|
||||
* @brief STM32F4xx/STM32F2xx ADC subsystem low level driver header.
|
||||
*
|
||||
* @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _ADC_LLD_H_
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||||
#define _ADC_LLD_H_
|
||||
|
||||
#if HAL_USE_ADC || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Absolute Maximum Ratings
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Minimum ADC clock frequency.
|
||||
*/
|
||||
#define STM32_ADCCLK_MIN 600000
|
||||
|
||||
/**
|
||||
* @brief Maximum ADC clock frequency.
|
||||
*/
|
||||
#if defined(STM32F4XX) || defined(__DOXYGEN__)
|
||||
#define STM32_ADCCLK_MAX 36000000
|
||||
#else
|
||||
#define STM32_ADCCLK_MAX 30000000
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Triggers selection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ADC clock divider settings
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CCR_ADCPRE_DIV2 0
|
||||
#define ADC_CCR_ADCPRE_DIV4 1
|
||||
#define ADC_CCR_ADCPRE_DIV6 2
|
||||
#define ADC_CCR_ADCPRE_DIV8 3
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Available analog channels
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */
|
||||
#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */
|
||||
#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */
|
||||
#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */
|
||||
#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */
|
||||
#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */
|
||||
#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */
|
||||
#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */
|
||||
#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */
|
||||
#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */
|
||||
#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */
|
||||
#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */
|
||||
#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */
|
||||
#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */
|
||||
#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */
|
||||
#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */
|
||||
#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.
|
||||
@note Available onADC1 only. */
|
||||
#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference.
|
||||
@note Available onADC1 only. */
|
||||
#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT.
|
||||
@note Available onADC1 only. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Sampling rates
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SAMPLE_3 0 /**< @brief 3 cycles sampling time. */
|
||||
#define ADC_SAMPLE_15 1 /**< @brief 15 cycles sampling time. */
|
||||
#define ADC_SAMPLE_28 2 /**< @brief 28 cycles sampling time. */
|
||||
#define ADC_SAMPLE_56 3 /**< @brief 56 cycles sampling time. */
|
||||
#define ADC_SAMPLE_84 4 /**< @brief 84 cycles sampling time. */
|
||||
#define ADC_SAMPLE_112 5 /**< @brief 112 cycles sampling time. */
|
||||
#define ADC_SAMPLE_144 6 /**< @brief 144 cycles sampling time. */
|
||||
#define ADC_SAMPLE_480 7 /**< @brief 480 cycles sampling time. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief ADC common clock divider.
|
||||
* @note This setting is influenced by the VDDA voltage and other
|
||||
* external conditions, please refer to the datasheet for more
|
||||
* info.<br>
|
||||
* See section 5.3.20 "12-bit ADC characteristics".
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC1 driver enable switch.
|
||||
* @details If set to @p TRUE the support for ADC1 is included.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC2 driver enable switch.
|
||||
* @details If set to @p TRUE the support for ADC2 is included.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(STM32_ADC_USE_ADC2) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_USE_ADC2 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC3 driver enable switch.
|
||||
* @details If set to @p TRUE the support for ADC3 is included.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_USE_ADC3 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DMA stream used for ADC1 operations.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC1_DMA_STREAM) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DMA stream used for ADC2 operations.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC2_DMA_STREAM) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DMA stream used for ADC3 operations.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC3_DMA_STREAM) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC1 DMA priority (0..3|lowest..highest).
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC2 DMA priority (0..3|lowest..highest).
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC2_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC3 DMA priority (0..3|lowest..highest).
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC interrupt priority level setting.
|
||||
* @note This setting is shared among ADC1, ADC2 and ADC3 because
|
||||
* all ADCs share the same vector.
|
||||
*/
|
||||
#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_IRQ_PRIORITY 5
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC1 DMA interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC2 DMA interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC3 DMA interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
|
||||
#error "ADC1 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC2 && !STM32_HAS_ADC2
|
||||
#error "ADC2 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3
|
||||
#error "ADC3 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3
|
||||
#error "ADC driver activated but no ADC peripheral assigned"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC1 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK)
|
||||
#error "invalid DMA stream associated to ADC1"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC2 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_MSK)
|
||||
#error "invalid DMA stream associated to ADC2"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC3 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_MSK)
|
||||
#error "invalid DMA stream associated to ADC3"
|
||||
#endif
|
||||
|
||||
/* ADC clock related settings and checks.*/
|
||||
#if STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV2
|
||||
#define STM32_ADCCLK (STM32_PCLK2 / 2)
|
||||
#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV4
|
||||
#define STM32_ADCCLK (STM32_PCLK2 / 4)
|
||||
#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV6
|
||||
#define STM32_ADCCLK (STM32_PCLK2 / 6)
|
||||
#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV8
|
||||
#define STM32_ADCCLK (STM32_PCLK2 / 8)
|
||||
#else
|
||||
#error "invalid STM32_ADC_ADCPRE value specified"
|
||||
#endif
|
||||
|
||||
#if (STM32_ADCCLK < STM32_ADCCLK_MIN) || (STM32_ADCCLK > STM32_ADCCLK_MAX)
|
||||
#error "STM32_ADCCLK outside acceptable range (STM32_ADCCLK_MIN...STM32_ADCCLK_MAX)"
|
||||
#endif
|
||||
|
||||
#if !defined(STM32_DMA_REQUIRED)
|
||||
#define STM32_DMA_REQUIRED
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief ADC sample data type.
|
||||
*/
|
||||
typedef uint16_t adcsample_t;
|
||||
|
||||
/**
|
||||
* @brief Channels number in a conversion group.
|
||||
*/
|
||||
typedef uint16_t adc_channels_num_t;
|
||||
|
||||
/**
|
||||
* @brief Possible ADC failure causes.
|
||||
* @note Error codes are architecture dependent and should not relied
|
||||
* upon.
|
||||
*/
|
||||
typedef enum {
|
||||
ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
|
||||
ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */
|
||||
} adcerror_t;
|
||||
|
||||
/**
|
||||
* @brief Type of a structure representing an ADC driver.
|
||||
*/
|
||||
typedef struct ADCDriver ADCDriver;
|
||||
|
||||
/**
|
||||
* @brief ADC notification callback type.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object triggering the
|
||||
* callback
|
||||
* @param[in] buffer pointer to the most recent samples data
|
||||
* @param[in] n number of buffer rows available starting from @p buffer
|
||||
*/
|
||||
typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
|
||||
|
||||
/**
|
||||
* @brief ADC error callback type.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object triggering the
|
||||
* callback
|
||||
* @param[in] err ADC error code
|
||||
*/
|
||||
typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
|
||||
|
||||
/**
|
||||
* @brief Conversion group configuration structure.
|
||||
* @details This implementation-dependent structure describes a conversion
|
||||
* operation.
|
||||
* @note The use of this configuration structure requires knowledge of
|
||||
* STM32 ADC cell registers interface, please refer to the STM32
|
||||
* reference manual for details.
|
||||
*/
|
||||
typedef struct {
|
||||
/**
|
||||
* @brief Enables the circular buffer mode for the group.
|
||||
*/
|
||||
bool_t circular;
|
||||
/**
|
||||
* @brief Number of the analog channels belonging to the conversion group.
|
||||
*/
|
||||
adc_channels_num_t num_channels;
|
||||
/**
|
||||
* @brief Callback function associated to the group or @p NULL.
|
||||
*/
|
||||
adccallback_t end_cb;
|
||||
/**
|
||||
* @brief Error callback or @p NULL.
|
||||
*/
|
||||
adcerrorcallback_t error_cb;
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief ADC CR1 register initialization data.
|
||||
* @note All the required bits must be defined into this field except
|
||||
* @p ADC_CR1_SCAN that is enforced inside the driver.
|
||||
*/
|
||||
uint32_t cr1;
|
||||
/**
|
||||
* @brief ADC CR2 register initialization data.
|
||||
* @note All the required bits must be defined into this field except
|
||||
* @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
|
||||
* enforced inside the driver.
|
||||
*/
|
||||
uint32_t cr2;
|
||||
/**
|
||||
* @brief ADC SMPR1 register initialization data.
|
||||
* @details In this field must be specified the sample times for channels
|
||||
* 10...18.
|
||||
*/
|
||||
uint32_t smpr1;
|
||||
/**
|
||||
* @brief ADC SMPR2 register initialization data.
|
||||
* @details In this field must be specified the sample times for channels
|
||||
* 0...9.
|
||||
*/
|
||||
uint32_t smpr2;
|
||||
/**
|
||||
* @brief ADC SQR1 register initialization data.
|
||||
* @details Conversion group sequence 13...16 + sequence length.
|
||||
*/
|
||||
uint32_t sqr1;
|
||||
/**
|
||||
* @brief ADC SQR2 register initialization data.
|
||||
* @details Conversion group sequence 7...12.
|
||||
*/
|
||||
uint32_t sqr2;
|
||||
/**
|
||||
* @brief ADC SQR3 register initialization data.
|
||||
* @details Conversion group sequence 1...6.
|
||||
*/
|
||||
uint32_t sqr3;
|
||||
} ADCConversionGroup;
|
||||
|
||||
/**
|
||||
* @brief Driver configuration structure.
|
||||
* @note It could be empty on some architectures.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t dummy;
|
||||
} ADCConfig;
|
||||
|
||||
/**
|
||||
* @brief Structure representing an ADC driver.
|
||||
*/
|
||||
struct ADCDriver {
|
||||
/**
|
||||
* @brief Driver state.
|
||||
*/
|
||||
adcstate_t state;
|
||||
/**
|
||||
* @brief Current configuration data.
|
||||
*/
|
||||
const ADCConfig *config;
|
||||
/**
|
||||
* @brief Current samples buffer pointer or @p NULL.
|
||||
*/
|
||||
adcsample_t *samples;
|
||||
/**
|
||||
* @brief Current samples buffer depth or @p 0.
|
||||
*/
|
||||
size_t depth;
|
||||
/**
|
||||
* @brief Current conversion group pointer or @p NULL.
|
||||
*/
|
||||
const ADCConversionGroup *grpp;
|
||||
#if ADC_USE_WAIT || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Waiting thread.
|
||||
*/
|
||||
Thread *thread;
|
||||
#endif
|
||||
#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
|
||||
#if CH_USE_MUTEXES || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Mutex protecting the peripheral.
|
||||
*/
|
||||
Mutex mutex;
|
||||
#elif CH_USE_SEMAPHORES
|
||||
Semaphore semaphore;
|
||||
#endif
|
||||
#endif /* ADC_USE_MUTUAL_EXCLUSION */
|
||||
#if defined(ADC_DRIVER_EXT_FIELDS)
|
||||
ADC_DRIVER_EXT_FIELDS
|
||||
#endif
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief Pointer to the ADCx registers block.
|
||||
*/
|
||||
ADC_TypeDef *adc;
|
||||
/**
|
||||
* @brief Pointer to associated DMA channel.
|
||||
*/
|
||||
const stm32_dma_stream_t *dmastp;
|
||||
/**
|
||||
* @brief DMA mode bit mask.
|
||||
*/
|
||||
uint32_t dmamode;
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Sequences building helper macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Number of channels in a conversion sequence.
|
||||
*/
|
||||
#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
|
||||
|
||||
#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */
|
||||
#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */
|
||||
#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */
|
||||
#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
|
||||
#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
|
||||
#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
|
||||
|
||||
#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */
|
||||
#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */
|
||||
#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */
|
||||
#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/
|
||||
#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/
|
||||
#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/
|
||||
|
||||
#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/
|
||||
#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/
|
||||
#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/
|
||||
#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Sampling rate settings helper macros
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */
|
||||
|
||||
#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */
|
||||
#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
|
||||
sampling time. */
|
||||
#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference
|
||||
sampling time. */
|
||||
#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD1;
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC2 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD2;
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD3;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void adc_lld_init(void);
|
||||
void adc_lld_start(ADCDriver *adcp);
|
||||
void adc_lld_stop(ADCDriver *adcp);
|
||||
void adc_lld_start_conversion(ADCDriver *adcp);
|
||||
void adc_lld_stop_conversion(ADCDriver *adcp);
|
||||
void adcSTM32EnableTSVREFE(void);
|
||||
void adcSTM32DisableTSVREFE(void);
|
||||
void adcSTM32EnableVBATE(void);
|
||||
void adcSTM32DisableVBATE(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_ADC */
|
||||
|
||||
#endif /* _ADC_LLD_H_ */
|
||||
|
||||
/** @} */
|
|
@ -0,0 +1,352 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F4xx/ext_lld_isr.c
|
||||
* @brief STM32F4xx/STM32F2xx EXT subsystem low level driver ISR code.
|
||||
*
|
||||
* @addtogroup EXT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
#if HAL_USE_EXT || defined(__DOXYGEN__)
|
||||
|
||||
#include "ext_lld_isr.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief EXTI[0] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(EXTI0_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 0);
|
||||
EXTD1.config->channels[0].cb(&EXTD1, 0);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[1] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(EXTI1_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 1);
|
||||
EXTD1.config->channels[1].cb(&EXTD1, 1);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[2] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(EXTI2_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 2);
|
||||
EXTD1.config->channels[2].cb(&EXTD1, 2);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[3] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(EXTI3_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 3);
|
||||
EXTD1.config->channels[3].cb(&EXTD1, 3);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[4] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(EXTI4_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 4);
|
||||
EXTD1.config->channels[4].cb(&EXTD1, 4);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[5]...EXTI[9] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
|
||||
uint32_t pr;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
|
||||
EXTI->PR = pr;
|
||||
if (pr & (1 << 5))
|
||||
EXTD1.config->channels[5].cb(&EXTD1, 5);
|
||||
if (pr & (1 << 6))
|
||||
EXTD1.config->channels[6].cb(&EXTD1, 6);
|
||||
if (pr & (1 << 7))
|
||||
EXTD1.config->channels[7].cb(&EXTD1, 7);
|
||||
if (pr & (1 << 8))
|
||||
EXTD1.config->channels[8].cb(&EXTD1, 8);
|
||||
if (pr & (1 << 9))
|
||||
EXTD1.config->channels[9].cb(&EXTD1, 9);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[10]...EXTI[15] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
|
||||
uint32_t pr;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
|
||||
(1 << 15));
|
||||
EXTI->PR = pr;
|
||||
if (pr & (1 << 10))
|
||||
EXTD1.config->channels[10].cb(&EXTD1, 10);
|
||||
if (pr & (1 << 11))
|
||||
EXTD1.config->channels[11].cb(&EXTD1, 11);
|
||||
if (pr & (1 << 12))
|
||||
EXTD1.config->channels[12].cb(&EXTD1, 12);
|
||||
if (pr & (1 << 13))
|
||||
EXTD1.config->channels[13].cb(&EXTD1, 13);
|
||||
if (pr & (1 << 14))
|
||||
EXTD1.config->channels[14].cb(&EXTD1, 14);
|
||||
if (pr & (1 << 15))
|
||||
EXTD1.config->channels[15].cb(&EXTD1, 15);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[16] interrupt handler (PVD).
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(PVD_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 16);
|
||||
EXTD1.config->channels[16].cb(&EXTD1, 16);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[17] interrupt handler (RTC).
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 17);
|
||||
EXTD1.config->channels[17].cb(&EXTD1, 17);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[18] interrupt handler (OTG_FS_WKUP).
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 18);
|
||||
EXTD1.config->channels[18].cb(&EXTD1, 18);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[19] interrupt handler (ETH_WKUP).
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 19);
|
||||
EXTD1.config->channels[19].cb(&EXTD1, 19);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[20] interrupt handler (OTG_HS_WKUP).
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(OTG_HS_WKUP_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 20);
|
||||
EXTD1.config->channels[20].cb(&EXTD1, 20);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[21] interrupt handler (TAMPER_STAMP).
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 21);
|
||||
EXTD1.config->channels[21].cb(&EXTD1, 21);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[22] interrupt handler (RTC_WKUP).
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 22);
|
||||
EXTD1.config->channels[22].cb(&EXTD1, 22);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables EXTI IRQ sources.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void ext_lld_exti_irq_enable(void) {
|
||||
|
||||
nvicEnableVector(EXTI0_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
|
||||
nvicEnableVector(EXTI1_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
|
||||
nvicEnableVector(EXTI2_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
|
||||
nvicEnableVector(EXTI3_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
|
||||
nvicEnableVector(EXTI4_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
|
||||
nvicEnableVector(EXTI9_5_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
|
||||
nvicEnableVector(EXTI15_10_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
|
||||
nvicEnableVector(PVD_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
|
||||
nvicEnableVector(RTC_Alarm_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
|
||||
nvicEnableVector(OTG_FS_WKUP_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
|
||||
nvicEnableVector(ETH_WKUP_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
|
||||
nvicEnableVector(OTG_HS_WKUP_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
|
||||
nvicEnableVector(TAMP_STAMP_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY));
|
||||
nvicEnableVector(RTC_WKUP_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI22_IRQ_PRIORITY));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables EXTI IRQ sources.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void ext_lld_exti_irq_disable(void) {
|
||||
|
||||
nvicDisableVector(EXTI0_IRQn);
|
||||
nvicDisableVector(EXTI1_IRQn);
|
||||
nvicDisableVector(EXTI2_IRQn);
|
||||
nvicDisableVector(EXTI3_IRQn);
|
||||
nvicDisableVector(EXTI4_IRQn);
|
||||
nvicDisableVector(EXTI9_5_IRQn);
|
||||
nvicDisableVector(EXTI15_10_IRQn);
|
||||
nvicDisableVector(PVD_IRQn);
|
||||
nvicDisableVector(RTC_Alarm_IRQn);
|
||||
nvicDisableVector(OTG_FS_WKUP_IRQn);
|
||||
nvicDisableVector(ETH_WKUP_IRQn);
|
||||
nvicDisableVector(OTG_HS_WKUP_IRQn);
|
||||
nvicDisableVector(TAMP_STAMP_IRQn);
|
||||
nvicDisableVector(RTC_WKUP_IRQn);
|
||||
}
|
||||
|
||||
#endif /* HAL_USE_EXT */
|
||||
|
||||
/** @} */
|
|
@ -0,0 +1,170 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F4xx/ext_lld_isr.h
|
||||
* @brief STM32F4xx/STM32F2xx EXT subsystem low level driver ISR header.
|
||||
*
|
||||
* @addtogroup EXT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _EXT_LLD_ISR_H_
|
||||
#define _EXT_LLD_ISR_H_
|
||||
|
||||
#if HAL_USE_EXT || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI0 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI1 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI2 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI3 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI4 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI9..5 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI15..10 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI16 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI17 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI18 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI19 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI20 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI21 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI21_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI21_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI22 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI22_IRQ_PRIORITY 6
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void ext_lld_exti_irq_enable(void);
|
||||
void ext_lld_exti_irq_disable(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_EXT */
|
||||
|
||||
#endif /* _EXT_LLD_ISR_H_ */
|
||||
|
||||
/** @} */
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F4xx/hal_lld.c
|
||||
* @brief STM32F4xx/STM32F2xx HAL subsystem low level driver source.
|
||||
*
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* TODO: LSEBYP like in F3.*/
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the backup domain.
|
||||
* @note WARNING! Changing clock source impossible without resetting
|
||||
* of the whole BKP domain.
|
||||
*/
|
||||
static void hal_lld_backup_domain_init(void) {
|
||||
|
||||
/* Backup domain access enabled and left open.*/
|
||||
PWR->CR |= PWR_CR_DBP;
|
||||
|
||||
/* Reset BKP domain if different clock source selected.*/
|
||||
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
|
||||
/* Backup domain reset.*/
|
||||
RCC->BDCR = RCC_BDCR_BDRST;
|
||||
RCC->BDCR = 0;
|
||||
}
|
||||
|
||||
#if STM32_LSE_ENABLED
|
||||
RCC->BDCR |= RCC_BDCR_LSEON;
|
||||
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
|
||||
; /* Waits until LSE is stable. */
|
||||
#endif
|
||||
|
||||
#if HAL_USE_RTC
|
||||
/* If the backup domain hasn't been initialized yet then proceed with
|
||||
initialization.*/
|
||||
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
|
||||
/* Selects clock source.*/
|
||||
RCC->BDCR |= STM32_RTCSEL;
|
||||
|
||||
/* RTC clock enabled.*/
|
||||
RCC->BDCR |= RCC_BDCR_RTCEN;
|
||||
}
|
||||
#endif /* HAL_USE_RTC */
|
||||
|
||||
#if STM32_BKPRAM_ENABLE
|
||||
rccEnableBKPSRAM(false);
|
||||
|
||||
PWR->CSR |= PWR_CSR_BRE;
|
||||
while ((PWR->CSR & PWR_CSR_BRR) == 0)
|
||||
; /* Waits until the regulator is stable */
|
||||
#else
|
||||
PWR->CSR &= ~PWR_CSR_BRE;
|
||||
#endif /* STM32_BKPRAM_ENABLE */
|
||||
}
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Low level HAL driver initialization.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void hal_lld_init(void) {
|
||||
|
||||
/* Reset of all peripherals. AHB3 is not reseted because it could have
|
||||
been initialized in the board initialization file (board.c).*/
|
||||
rccResetAHB1(~0);
|
||||
rccResetAHB2(~0);
|
||||
rccResetAPB1(~RCC_APB1RSTR_PWRRST);
|
||||
rccResetAPB2(~0);
|
||||
|
||||
/* SysTick initialization using the system clock.*/
|
||||
SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
|
||||
SysTick->VAL = 0;
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk;
|
||||
|
||||
/* DWT cycle counter enable.*/
|
||||
SCS_DEMCR |= SCS_DEMCR_TRCENA;
|
||||
DWT_CTRL |= DWT_CTRL_CYCCNTENA;
|
||||
|
||||
/* PWR clock enabled.*/
|
||||
rccEnablePWRInterface(FALSE);
|
||||
|
||||
/* Initializes the backup domain.*/
|
||||
hal_lld_backup_domain_init();
|
||||
|
||||
#if defined(STM32_DMA_REQUIRED)
|
||||
dmaInit();
|
||||
#endif
|
||||
|
||||
/* Programmable voltage detector enable.*/
|
||||
#if STM32_PVD_ENABLE
|
||||
PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
|
||||
#endif /* STM32_PVD_ENABLE */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief STM32F2xx clocks and PLL initialization.
|
||||
* @note All the involved constants come from the file @p board.h.
|
||||
* @note This function should be invoked just after the system reset.
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
void stm32_clock_init(void) {
|
||||
|
||||
#if !STM32_NO_INIT
|
||||
/* PWR clock enable.*/
|
||||
RCC->APB1ENR = RCC_APB1ENR_PWREN;
|
||||
|
||||
/* PWR initialization.*/
|
||||
#if defined(STM32F4XX) || defined(__DOXYGEN__)
|
||||
PWR->CR = STM32_VOS;
|
||||
while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
|
||||
; /* Waits until power regulator is stable. */
|
||||
#else
|
||||
PWR->CR = 0;
|
||||
#endif
|
||||
|
||||
/* Initial clocks setup and wait for HSI stabilization, the MSI clock is
|
||||
always enabled because it is the fallback clock when PLL the fails.*/
|
||||
RCC->CR |= RCC_CR_HSION;
|
||||
while ((RCC->CR & RCC_CR_HSIRDY) == 0)
|
||||
; /* Waits until HSI is stable. */
|
||||
|
||||
#if STM32_HSE_ENABLED
|
||||
/* HSE activation.*/
|
||||
#if defined(STM32_HSE_BYPASS)
|
||||
/* HSE Bypass.*/
|
||||
RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
|
||||
#else
|
||||
/* No HSE Bypass.*/
|
||||
RCC->CR |= RCC_CR_HSEON;
|
||||
#endif
|
||||
while ((RCC->CR & RCC_CR_HSERDY) == 0)
|
||||
; /* Waits until HSE is stable. */
|
||||
#endif
|
||||
|
||||
#if STM32_LSI_ENABLED
|
||||
/* LSI activation.*/
|
||||
RCC->CSR |= RCC_CSR_LSION;
|
||||
while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
|
||||
; /* Waits until LSI is stable. */
|
||||
#endif
|
||||
|
||||
#if STM32_ACTIVATE_PLL
|
||||
/* PLL activation.*/
|
||||
RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |
|
||||
STM32_PLLM;
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY))
|
||||
; /* Waits until PLL is stable. */
|
||||
#endif
|
||||
|
||||
#if STM32_ACTIVATE_PLLI2S
|
||||
/* PLLI2S activation.*/
|
||||
RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN;
|
||||
RCC->CR |= RCC_CR_PLLI2SON;
|
||||
while (!(RCC->CR & RCC_CR_PLLI2SRDY))
|
||||
; /* Waits until PLLI2S is stable. */
|
||||
#endif
|
||||
|
||||
/* Other clock-related settings (dividers, MCO etc).*/
|
||||
RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
|
||||
STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
|
||||
|
||||
/* Flash setup.*/
|
||||
#if defined(STM32_USE_REVISION_A_FIX)
|
||||
/* Some old revisions of F4x MCUs randomly crashes with compiler
|
||||
optimizations enabled AND flash caches enabled. */
|
||||
if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241))
|
||||
FLASH->ACR = FLASH_ACR_PRFTEN | STM32_FLASHBITS;
|
||||
else
|
||||
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
|
||||
FLASH_ACR_DCEN | STM32_FLASHBITS;
|
||||
#else
|
||||
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
|
||||
FLASH_ACR_DCEN | STM32_FLASHBITS;
|
||||
#endif
|
||||
|
||||
/* Switching to the configured clock source if it is different from MSI.*/
|
||||
#if (STM32_SW != STM32_SW_HSI)
|
||||
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
|
||||
;
|
||||
#endif
|
||||
#endif /* STM32_NO_INIT */
|
||||
|
||||
/* SYSCFG clock enabled here because it is a multi-functional unit shared
|
||||
among multiple drivers.*/
|
||||
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
|
||||
}
|
||||
|
||||
/** @} */
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,30 @@
|
|||
# List of all the STM32F2xx/STM32F4xx platform files.
|
||||
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32F4xx/adc_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32F4xx/ext_lld_isr.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c
|
||||
|
||||
# Required include directories
|
||||
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F4xx \
|
||||
${CHIBIOS}/os/hal/platforms/STM32 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/OTGv1 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1
|
|
@ -0,0 +1,527 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F4xx/stm32_dma.c
|
||||
* @brief Enhanced DMA helper driver code.
|
||||
*
|
||||
* @addtogroup STM32F4xx_DMA
|
||||
* @details DMA sharing helper driver. In the STM32 the DMA streams are a
|
||||
* shared resource, this driver allows to allocate and free DMA
|
||||
* streams at runtime in order to allow all the other device
|
||||
* drivers to coordinate the access to the resource.
|
||||
* @note The DMA ISR handlers are all declared into this module because
|
||||
* sharing, the various device drivers can associate a callback to
|
||||
* ISRs when allocating streams.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
/* The following macro is only defined if some driver requiring DMA services
|
||||
has been enabled.*/
|
||||
#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Mask of the DMA1 streams in @p dma_streams_mask.
|
||||
*/
|
||||
#define STM32_DMA1_STREAMS_MASK 0x000000FF
|
||||
|
||||
/**
|
||||
* @brief Mask of the DMA2 streams in @p dma_streams_mask.
|
||||
*/
|
||||
#define STM32_DMA2_STREAMS_MASK 0x0000FF00
|
||||
|
||||
/**
|
||||
* @brief Post-reset value of the stream CR register.
|
||||
*/
|
||||
#define STM32_DMA_CR_RESET_VALUE 0x00000000
|
||||
|
||||
/**
|
||||
* @brief Post-reset value of the stream FCR register.
|
||||
*/
|
||||
#define STM32_DMA_FCR_RESET_VALUE 0x00000021
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief DMA streams descriptors.
|
||||
* @details This table keeps the association between an unique stream
|
||||
* identifier and the involved physical registers.
|
||||
* @note Don't use this array directly, use the appropriate wrapper macros
|
||||
* instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc.
|
||||
*/
|
||||
const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
|
||||
{DMA1_Stream0, &DMA1->LIFCR, 0, 0, DMA1_Stream0_IRQn},
|
||||
{DMA1_Stream1, &DMA1->LIFCR, 6, 1, DMA1_Stream1_IRQn},
|
||||
{DMA1_Stream2, &DMA1->LIFCR, 16, 2, DMA1_Stream2_IRQn},
|
||||
{DMA1_Stream3, &DMA1->LIFCR, 22, 3, DMA1_Stream3_IRQn},
|
||||
{DMA1_Stream4, &DMA1->HIFCR, 0, 4, DMA1_Stream4_IRQn},
|
||||
{DMA1_Stream5, &DMA1->HIFCR, 6, 5, DMA1_Stream5_IRQn},
|
||||
{DMA1_Stream6, &DMA1->HIFCR, 16, 6, DMA1_Stream6_IRQn},
|
||||
{DMA1_Stream7, &DMA1->HIFCR, 22, 7, DMA1_Stream7_IRQn},
|
||||
{DMA2_Stream0, &DMA2->LIFCR, 0, 8, DMA2_Stream0_IRQn},
|
||||
{DMA2_Stream1, &DMA2->LIFCR, 6, 9, DMA2_Stream1_IRQn},
|
||||
{DMA2_Stream2, &DMA2->LIFCR, 16, 10, DMA2_Stream2_IRQn},
|
||||
{DMA2_Stream3, &DMA2->LIFCR, 22, 11, DMA2_Stream3_IRQn},
|
||||
{DMA2_Stream4, &DMA2->HIFCR, 0, 12, DMA2_Stream4_IRQn},
|
||||
{DMA2_Stream5, &DMA2->HIFCR, 6, 13, DMA2_Stream5_IRQn},
|
||||
{DMA2_Stream6, &DMA2->HIFCR, 16, 14, DMA2_Stream6_IRQn},
|
||||
{DMA2_Stream7, &DMA2->HIFCR, 22, 15, DMA2_Stream7_IRQn},
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief DMA ISR redirector type.
|
||||
*/
|
||||
typedef struct {
|
||||
stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */
|
||||
void *dma_param; /**< @brief DMA callback parameter. */
|
||||
} dma_isr_redir_t;
|
||||
|
||||
/**
|
||||
* @brief Mask of the allocated streams.
|
||||
*/
|
||||
static uint32_t dma_streams_mask;
|
||||
|
||||
/**
|
||||
* @brief DMA IRQ redirectors.
|
||||
*/
|
||||
static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief DMA1 stream 0 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK;
|
||||
DMA1->LIFCR = STM32_DMA_ISR_MASK << 0;
|
||||
if (dma_isr_redir[0].dma_func)
|
||||
dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA1 stream 1 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK;
|
||||
DMA1->LIFCR = STM32_DMA_ISR_MASK << 6;
|
||||
if (dma_isr_redir[1].dma_func)
|
||||
dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA1 stream 2 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK;
|
||||
DMA1->LIFCR = STM32_DMA_ISR_MASK << 16;
|
||||
if (dma_isr_redir[2].dma_func)
|
||||
dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA1 stream 3 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK;
|
||||
DMA1->LIFCR = STM32_DMA_ISR_MASK << 22;
|
||||
if (dma_isr_redir[3].dma_func)
|
||||
dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA1 stream 4 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK;
|
||||
DMA1->HIFCR = STM32_DMA_ISR_MASK << 0;
|
||||
if (dma_isr_redir[4].dma_func)
|
||||
dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA1 stream 5 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK;
|
||||
DMA1->HIFCR = STM32_DMA_ISR_MASK << 6;
|
||||
if (dma_isr_redir[5].dma_func)
|
||||
dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA1 stream 6 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK;
|
||||
DMA1->HIFCR = STM32_DMA_ISR_MASK << 16;
|
||||
if (dma_isr_redir[6].dma_func)
|
||||
dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA1 stream 7 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK;
|
||||
DMA1->HIFCR = STM32_DMA_ISR_MASK << 22;
|
||||
if (dma_isr_redir[7].dma_func)
|
||||
dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA2 stream 0 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK;
|
||||
DMA2->LIFCR = STM32_DMA_ISR_MASK << 0;
|
||||
if (dma_isr_redir[8].dma_func)
|
||||
dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA2 stream 1 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK;
|
||||
DMA2->LIFCR = STM32_DMA_ISR_MASK << 6;
|
||||
if (dma_isr_redir[9].dma_func)
|
||||
dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA2 stream 2 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK;
|
||||
DMA2->LIFCR = STM32_DMA_ISR_MASK << 16;
|
||||
if (dma_isr_redir[10].dma_func)
|
||||
dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA2 stream 3 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK;
|
||||
DMA2->LIFCR = STM32_DMA_ISR_MASK << 22;
|
||||
if (dma_isr_redir[11].dma_func)
|
||||
dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA2 stream 4 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK;
|
||||
DMA2->HIFCR = STM32_DMA_ISR_MASK << 0;
|
||||
if (dma_isr_redir[12].dma_func)
|
||||
dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA2 stream 5 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK;
|
||||
DMA2->HIFCR = STM32_DMA_ISR_MASK << 6;
|
||||
if (dma_isr_redir[13].dma_func)
|
||||
dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA2 stream 6 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK;
|
||||
DMA2->HIFCR = STM32_DMA_ISR_MASK << 16;
|
||||
if (dma_isr_redir[14].dma_func)
|
||||
dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA2 stream 7 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK;
|
||||
DMA2->HIFCR = STM32_DMA_ISR_MASK << 22;
|
||||
if (dma_isr_redir[15].dma_func)
|
||||
dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief STM32 DMA helper initialization.
|
||||
*
|
||||
* @init
|
||||
*/
|
||||
void dmaInit(void) {
|
||||
int i;
|
||||
|
||||
dma_streams_mask = 0;
|
||||
for (i = 0; i < STM32_DMA_STREAMS; i++) {
|
||||
_stm32_dma_streams[i].stream->CR = 0;
|
||||
dma_isr_redir[i].dma_func = NULL;
|
||||
}
|
||||
DMA1->LIFCR = 0xFFFFFFFF;
|
||||
DMA1->HIFCR = 0xFFFFFFFF;
|
||||
DMA2->LIFCR = 0xFFFFFFFF;
|
||||
DMA2->HIFCR = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Allocates a DMA stream.
|
||||
* @details The stream is allocated and, if required, the DMA clock enabled.
|
||||
* The function also enables the IRQ vector associated to the stream
|
||||
* and initializes its priority.
|
||||
* @pre The stream must not be already in use or an error is returned.
|
||||
* @post The stream is allocated and the default ISR handler redirected
|
||||
* to the specified function.
|
||||
* @post The stream ISR vector is enabled and its priority configured.
|
||||
* @post The stream must be freed using @p dmaStreamRelease() before it can
|
||||
* be reused with another peripheral.
|
||||
* @post The stream is in its post-reset state.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] priority IRQ priority mask for the DMA stream
|
||||
* @param[in] func handling function pointer, can be @p NULL
|
||||
* @param[in] param a parameter to be passed to the handling function
|
||||
* @return The operation status.
|
||||
* @retval FALSE no error, stream taken.
|
||||
* @retval TRUE error, stream already taken.
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
|
||||
uint32_t priority,
|
||||
stm32_dmaisr_t func,
|
||||
void *param) {
|
||||
|
||||
chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
|
||||
|
||||
/* Checks if the stream is already taken.*/
|
||||
if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
|
||||
return TRUE;
|
||||
|
||||
/* Marks the stream as allocated.*/
|
||||
dma_isr_redir[dmastp->selfindex].dma_func = func;
|
||||
dma_isr_redir[dmastp->selfindex].dma_param = param;
|
||||
dma_streams_mask |= (1 << dmastp->selfindex);
|
||||
|
||||
/* Enabling DMA clocks required by the current streams set.*/
|
||||
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
|
||||
rccEnableDMA1(FALSE);
|
||||
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
|
||||
rccEnableDMA2(FALSE);
|
||||
|
||||
/* Putting the stream in a safe state.*/
|
||||
dmaStreamDisable(dmastp);
|
||||
dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE;
|
||||
dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE;
|
||||
|
||||
/* Enables the associated IRQ vector if a callback is defined.*/
|
||||
if (func != NULL)
|
||||
nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Releases a DMA stream.
|
||||
* @details The stream is freed and, if required, the DMA clock disabled.
|
||||
* Trying to release a unallocated stream is an illegal operation
|
||||
* and is trapped if assertions are enabled.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post The stream is again available.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
|
||||
|
||||
chDbgCheck(dmastp != NULL, "dmaStreamRelease");
|
||||
|
||||
/* Check if the streams is not taken.*/
|
||||
chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
|
||||
"dmaStreamRelease(), #1", "not allocated");
|
||||
|
||||
/* Disables the associated IRQ vector.*/
|
||||
nvicDisableVector(dmastp->vector);
|
||||
|
||||
/* Marks the stream as not allocated.*/
|
||||
dma_streams_mask &= ~(1 << dmastp->selfindex);
|
||||
|
||||
/* Shutting down clocks that are no more required, if any.*/
|
||||
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
|
||||
rccDisableDMA1(FALSE);
|
||||
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
|
||||
rccDisableDMA2(FALSE);
|
||||
}
|
||||
|
||||
#endif /* STM32_DMA_REQUIRED */
|
||||
|
||||
/** @} */
|
|
@ -0,0 +1,461 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F4xx/stm32_dma.h
|
||||
* @brief Enhanced-DMA helper driver header.
|
||||
* @note This file requires definitions from the ST STM32F4xx header file
|
||||
* stm32f4xx.h.
|
||||
*
|
||||
* @addtogroup STM32F4xx_DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _STM32_DMA_H_
|
||||
#define _STM32_DMA_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Total number of DMA streams.
|
||||
* @note This is the total number of streams among all the DMA units.
|
||||
*/
|
||||
#define STM32_DMA_STREAMS 16
|
||||
|
||||
/**
|
||||
* @brief Mask of the ISR bits passed to the DMA callback functions.
|
||||
*/
|
||||
#define STM32_DMA_ISR_MASK 0x3D
|
||||
|
||||
/**
|
||||
* @brief Returns the channel associated to the specified stream.
|
||||
*
|
||||
* @param[in] id the unique numeric stream identifier
|
||||
* @param[in] c a stream/channel association word, one channel per
|
||||
* nibble
|
||||
* @return Returns the channel associated to the stream.
|
||||
*/
|
||||
#define STM32_DMA_GETCHANNEL(id, c) (((c) >> (((id) & 7) * 4)) & 7)
|
||||
|
||||
/**
|
||||
* @brief Checks if a DMA priority is within the valid range.
|
||||
* @param[in] prio DMA priority
|
||||
*
|
||||
* @retval The check result.
|
||||
* @retval FALSE invalid DMA priority.
|
||||
* @retval TRUE correct DMA priority.
|
||||
*/
|
||||
#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
|
||||
|
||||
/**
|
||||
* @brief Returns an unique numeric identifier for a DMA stream.
|
||||
*
|
||||
* @param[in] dma the DMA unit number
|
||||
* @param[in] stream the stream number
|
||||
* @return An unique numeric stream identifier.
|
||||
*/
|
||||
#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 8) + (stream))
|
||||
|
||||
/**
|
||||
* @brief Returns a DMA stream identifier mask.
|
||||
*
|
||||
*
|
||||
* @param[in] dma the DMA unit number
|
||||
* @param[in] stream the stream number
|
||||
* @return A DMA stream identifier mask.
|
||||
*/
|
||||
#define STM32_DMA_STREAM_ID_MSK(dma, stream) \
|
||||
(1 << STM32_DMA_STREAM_ID(dma, stream))
|
||||
|
||||
/**
|
||||
* @brief Checks if a DMA stream unique identifier belongs to a mask.
|
||||
* @param[in] id the stream numeric identifier
|
||||
* @param[in] mask the stream numeric identifiers mask
|
||||
*
|
||||
* @retval The check result.
|
||||
* @retval FALSE id does not belong to the mask.
|
||||
* @retval TRUE id belongs to the mask.
|
||||
*/
|
||||
#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
|
||||
|
||||
/**
|
||||
* @name DMA streams identifiers
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Returns a pointer to a stm32_dma_stream_t structure.
|
||||
*
|
||||
* @param[in] id the stream numeric identifier
|
||||
* @return A pointer to the stm32_dma_stream_t constant structure
|
||||
* associated to the DMA stream.
|
||||
*/
|
||||
#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id])
|
||||
|
||||
#define STM32_DMA1_STREAM0 STM32_DMA_STREAM(0)
|
||||
#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(1)
|
||||
#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(2)
|
||||
#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(3)
|
||||
#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(4)
|
||||
#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(5)
|
||||
#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(6)
|
||||
#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(7)
|
||||
#define STM32_DMA2_STREAM0 STM32_DMA_STREAM(8)
|
||||
#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(9)
|
||||
#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(10)
|
||||
#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(11)
|
||||
#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(12)
|
||||
#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(13)
|
||||
#define STM32_DMA2_STREAM6 STM32_DMA_STREAM(14)
|
||||
#define STM32_DMA2_STREAM7 STM32_DMA_STREAM(15)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name CR register constants common to all DMA types
|
||||
* @{
|
||||
*/
|
||||
#define STM32_DMA_CR_EN DMA_SxCR_EN
|
||||
#define STM32_DMA_CR_TEIE DMA_SxCR_TEIE
|
||||
#define STM32_DMA_CR_HTIE DMA_SxCR_HTIE
|
||||
#define STM32_DMA_CR_TCIE DMA_SxCR_TCIE
|
||||
#define STM32_DMA_CR_DIR_MASK DMA_SxCR_DIR
|
||||
#define STM32_DMA_CR_DIR_P2M 0
|
||||
#define STM32_DMA_CR_DIR_M2P DMA_SxCR_DIR_0
|
||||
#define STM32_DMA_CR_DIR_M2M DMA_SxCR_DIR_1
|
||||
#define STM32_DMA_CR_CIRC DMA_SxCR_CIRC
|
||||
#define STM32_DMA_CR_PINC DMA_SxCR_PINC
|
||||
#define STM32_DMA_CR_MINC DMA_SxCR_MINC
|
||||
#define STM32_DMA_CR_PSIZE_MASK DMA_SxCR_PSIZE
|
||||
#define STM32_DMA_CR_PSIZE_BYTE 0
|
||||
#define STM32_DMA_CR_PSIZE_HWORD DMA_SxCR_PSIZE_0
|
||||
#define STM32_DMA_CR_PSIZE_WORD DMA_SxCR_PSIZE_1
|
||||
#define STM32_DMA_CR_MSIZE_MASK DMA_SxCR_MSIZE
|
||||
#define STM32_DMA_CR_MSIZE_BYTE 0
|
||||
#define STM32_DMA_CR_MSIZE_HWORD DMA_SxCR_MSIZE_0
|
||||
#define STM32_DMA_CR_MSIZE_WORD DMA_SxCR_MSIZE_1
|
||||
#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \
|
||||
STM32_DMA_CR_MSIZE_MASK)
|
||||
#define STM32_DMA_CR_PL_MASK DMA_SxCR_PL
|
||||
#define STM32_DMA_CR_PL(n) ((n) << 16)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name CR register constants only found in STM32F2xx/STM32F4xx
|
||||
* @{
|
||||
*/
|
||||
#define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE
|
||||
#define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL
|
||||
#define STM32_DMA_CR_PINCOS DMA_SxCR_PINCOS
|
||||
#define STM32_DMA_CR_DBM DMA_SxCR_DBM
|
||||
#define STM32_DMA_CR_CT DMA_SxCR_CT
|
||||
#define STM32_DMA_CR_PBURST_MASK DMA_SxCR_PBURST
|
||||
#define STM32_DMA_CR_PBURST_SINGLE 0
|
||||
#define STM32_DMA_CR_PBURST_INCR4 DMA_SxCR_PBURST_0
|
||||
#define STM32_DMA_CR_PBURST_INCR8 DMA_SxCR_PBURST_1
|
||||
#define STM32_DMA_CR_PBURST_INCR16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1)
|
||||
#define STM32_DMA_CR_MBURST_MASK DMA_SxCR_MBURST
|
||||
#define STM32_DMA_CR_MBURST_SINGLE 0
|
||||
#define STM32_DMA_CR_MBURST_INCR4 DMA_SxCR_MBURST_0
|
||||
#define STM32_DMA_CR_MBURST_INCR8 DMA_SxCR_MBURST_1
|
||||
#define STM32_DMA_CR_MBURST_INCR16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1)
|
||||
#define STM32_DMA_CR_CHSEL_MASK DMA_SxCR_CHSEL
|
||||
#define STM32_DMA_CR_CHSEL(n) ((n) << 25)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name FCR register constants only found in STM32F2xx/STM32F4xx
|
||||
* @{
|
||||
*/
|
||||
#define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE
|
||||
#define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS
|
||||
#define STM32_DMA_FCR_DMDIS DMA_SxFCR_DMDIS
|
||||
#define STM32_DMA_FCR_FTH_MASK DMA_SxFCR_FTH
|
||||
#define STM32_DMA_FCR_FTH_1Q 0
|
||||
#define STM32_DMA_FCR_FTH_HALF DMA_SxFCR_FTH_0
|
||||
#define STM32_DMA_FCR_FTH_3Q DMA_SxFCR_FTH_1
|
||||
#define STM32_DMA_FCR_FTH_FULL (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Status flags passed to the ISR callbacks
|
||||
*/
|
||||
#define STM32_DMA_ISR_FEIF DMA_LISR_FEIF0
|
||||
#define STM32_DMA_ISR_DMEIF DMA_LISR_DMEIF0
|
||||
#define STM32_DMA_ISR_TEIF DMA_LISR_TEIF0
|
||||
#define STM32_DMA_ISR_HTIF DMA_LISR_HTIF0
|
||||
#define STM32_DMA_ISR_TCIF DMA_LISR_TCIF0
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief STM32 DMA stream descriptor structure.
|
||||
*/
|
||||
typedef struct {
|
||||
DMA_Stream_TypeDef *stream; /**< @brief Associated DMA stream. */
|
||||
volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
|
||||
uint8_t ishift; /**< @brief Bits offset in xIFCR
|
||||
register. */
|
||||
uint8_t selfindex; /**< @brief Index to self in array. */
|
||||
uint8_t vector; /**< @brief Associated IRQ vector. */
|
||||
} stm32_dma_stream_t;
|
||||
|
||||
/**
|
||||
* @brief STM32 DMA ISR function type.
|
||||
*
|
||||
* @param[in] p parameter for the registered function
|
||||
* @param[in] flags pre-shifted content of the xISR register, the bits
|
||||
* are aligned to bit zero
|
||||
*/
|
||||
typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Macro Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Associates a peripheral data register to a DMA stream.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] addr value to be written in the PAR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetPeripheral(dmastp, addr) { \
|
||||
(dmastp)->stream->PAR = (uint32_t)(addr); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Associates a memory destination to a DMA stream.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] addr value to be written in the M0AR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetMemory0(dmastp, addr) { \
|
||||
(dmastp)->stream->M0AR = (uint32_t)(addr); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Associates an alternate memory destination to a DMA stream.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] addr value to be written in the M1AR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetMemory1(dmastp, addr) { \
|
||||
(dmastp)->stream->M1AR = (uint32_t)(addr); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the number of transfers to be performed.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] size value to be written in the CNDTR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetTransactionSize(dmastp, size) { \
|
||||
(dmastp)->stream->NDTR = (uint32_t)(size); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of transfers to be performed.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @return The number of transfers to be performed.
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR))
|
||||
|
||||
/**
|
||||
* @brief Programs the stream mode settings.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] mode value to be written in the CR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetMode(dmastp, mode) { \
|
||||
(dmastp)->stream->CR = (uint32_t)(mode); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Programs the stream FIFO settings.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] mode value to be written in the FCR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetFIFO(dmastp, mode) { \
|
||||
(dmastp)->stream->FCR = (uint32_t)(mode); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA stream enable.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamEnable(dmastp) { \
|
||||
(dmastp)->stream->CR |= STM32_DMA_CR_EN; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA stream disable.
|
||||
* @details The function disables the specified stream, waits for the disable
|
||||
* operation to complete and then clears any pending interrupt.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @note Interrupts enabling flags are set to zero after this call, see
|
||||
* bug 3607518.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamDisable(dmastp) { \
|
||||
(dmastp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
|
||||
STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE | \
|
||||
STM32_DMA_CR_EN); \
|
||||
while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0) \
|
||||
; \
|
||||
dmaStreamClearInterrupt(dmastp); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA stream interrupt sources clear.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamClearInterrupt(dmastp) { \
|
||||
*(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts a memory to memory operation using the specified stream.
|
||||
* @note The default transfer data mode is "byte to byte" but it can be
|
||||
* changed by specifying extra options in the @p mode parameter.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] mode value to be written in the CCR register, this value
|
||||
* is implicitly ORed with:
|
||||
* - @p STM32_DMA_CR_MINC
|
||||
* - @p STM32_DMA_CR_PINC
|
||||
* - @p STM32_DMA_CR_DIR_M2M
|
||||
* - @p STM32_DMA_CR_EN
|
||||
* .
|
||||
* @param[in] src source address
|
||||
* @param[in] dst destination address
|
||||
* @param[in] n number of data units to copy
|
||||
*/
|
||||
#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \
|
||||
dmaStreamSetPeripheral(dmastp, src); \
|
||||
dmaStreamSetMemory0(dmastp, dst); \
|
||||
dmaStreamSetTransactionSize(dmastp, n); \
|
||||
dmaStreamSetMode(dmastp, (mode) | \
|
||||
STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
|
||||
STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Polled wait for DMA transfer end.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*/
|
||||
#define dmaWaitCompletion(dmastp) { \
|
||||
while ((dmastp)->stream->NDTR > 0) \
|
||||
; \
|
||||
dmaStreamDisable(dmastp); \
|
||||
}
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void dmaInit(void);
|
||||
bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
|
||||
uint32_t priority,
|
||||
stm32_dmaisr_t func,
|
||||
void *param);
|
||||
void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _STM32_DMA_H_ */
|
||||
|
||||
/** @} */
|
|
@ -0,0 +1,150 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F4xx/stm32_isr.h
|
||||
* @brief ISR remapper driver header.
|
||||
*
|
||||
* @addtogroup STM32F4xx_ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _STM32_ISR_H_
|
||||
#define _STM32_ISR_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name ISR names and numbers remapping
|
||||
* @{
|
||||
*/
|
||||
/*
|
||||
* CAN units.
|
||||
*/
|
||||
#define STM32_CAN1_TX_HANDLER CAN1_TX_IRQHandler
|
||||
#define STM32_CAN1_RX0_HANDLER CAN1_RX0_IRQHandler
|
||||
#define STM32_CAN1_RX1_HANDLER CAN1_RX1_IRQHandler
|
||||
#define STM32_CAN1_SCE_HANDLER CAN1_SCE_IRQHandler
|
||||
#define STM32_CAN2_TX_HANDLER CAN2_TX_IRQHandler
|
||||
#define STM32_CAN2_RX0_HANDLER CAN2_RX0_IRQHandler
|
||||
#define STM32_CAN2_RX1_HANDLER CAN2_RX1_IRQHandler
|
||||
#define STM32_CAN2_SCE_HANDLER CAN2_SCE_IRQHandler
|
||||
|
||||
#define STM32_CAN1_TX_NUMBER CAN1_TX_IRQn
|
||||
#define STM32_CAN1_RX0_NUMBER CAN1_RX0_IRQn
|
||||
#define STM32_CAN1_RX1_NUMBER CAN1_RX1_IRQn
|
||||
#define STM32_CAN1_SCE_NUMBER CAN1_SCE_IRQn
|
||||
#define STM32_CAN2_TX_NUMBER CAN2_TX_IRQn
|
||||
#define STM32_CAN2_RX0_NUMBER CAN2_RX0_IRQn
|
||||
#define STM32_CAN2_RX1_NUMBER CAN2_RX1_IRQn
|
||||
#define STM32_CAN2_SCE_NUMBER CAN2_SCE_IRQn
|
||||
|
||||
/*
|
||||
* OTG units.
|
||||
*/
|
||||
#define STM32_OTG1_HANDLER Vector14C
|
||||
#define STM32_OTG2_HANDLER Vector174
|
||||
#define STM32_OTG2_EP1OUT_HANDLER Vector168
|
||||
#define STM32_OTG2_EP1IN_HANDLER Vector16C
|
||||
|
||||
#define STM32_OTG1_NUMBER OTG_FS_IRQn
|
||||
#define STM32_OTG2_NUMBER OTG_HS_IRQn
|
||||
#define STM32_OTG2_EP1OUT_NUMBER OTG_HS_EP1_OUT_IRQn
|
||||
#define STM32_OTG2_EP1IN_NUMBER OTG_HS_EP1_IN_IRQn
|
||||
|
||||
/*
|
||||
* SDIO unit.
|
||||
*/
|
||||
#define STM32_SDIO_HANDLER SDIO_IRQHandler
|
||||
|
||||
#define STM32_SDIO_NUMBER SDIO_IRQn
|
||||
|
||||
/*
|
||||
* TIM units.
|
||||
*/
|
||||
#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler
|
||||
#define STM32_TIM1_CC_HANDLER TIM1_CC_IRQHandler
|
||||
#define STM32_TIM2_HANDLER TIM2_IRQHandler
|
||||
#define STM32_TIM3_HANDLER TIM3_IRQHandler
|
||||
#define STM32_TIM4_HANDLER TIM4_IRQHandler
|
||||
#define STM32_TIM5_HANDLER TIM5_IRQHandler
|
||||
#define STM32_TIM6_HANDLER TIM6_IRQHandler
|
||||
#define STM32_TIM7_HANDLER TIM7_IRQHandler
|
||||
#define STM32_TIM8_UP_HANDLER TIM8_UP_IRQHandler
|
||||
#define STM32_TIM8_CC_HANDLER TIM8_CC_IRQHandler
|
||||
#define STM32_TIM9_HANDLER TIM1_BRK_IRQHandler
|
||||
#define STM32_TIM11_HANDLER TIM1_TRG_COM_IRQHandler
|
||||
#define STM32_TIM12_HANDLER TIM8_BRK_IRQHandler
|
||||
#define STM32_TIM14_HANDLER TIM8_TRG_COM_IRQHandler
|
||||
|
||||
#define STM32_TIM1_UP_NUMBER TIM1_UP_TIM10_IRQn
|
||||
#define STM32_TIM1_CC_NUMBER TIM1_CC_IRQn
|
||||
#define STM32_TIM2_NUMBER TIM2_IRQn
|
||||
#define STM32_TIM3_NUMBER TIM3_IRQn
|
||||
#define STM32_TIM4_NUMBER TIM4_IRQn
|
||||
#define STM32_TIM5_NUMBER TIM5_IRQn
|
||||
#define STM32_TIM6_NUMBER TIM6_IRQn
|
||||
#define STM32_TIM7_NUMBER TIM7_IRQn
|
||||
#define STM32_TIM8_UP_NUMBER TIM8_UP_TIM13_IRQn
|
||||
#define STM32_TIM8_CC_NUMBER TIM8_CC_IRQn
|
||||
#define STM32_TIM9_NUMBER TIM1_BRK_TIM9_IRQn
|
||||
#define STM32_TIM11_NUMBER TIM1_TRG_COM_TIM11_IRQn
|
||||
#define STM32_TIM12_NUMBER TIM8_BRK_TIM12_IRQn
|
||||
#define STM32_TIM14_NUMBER TIM8_TRG_COM_TIM14_IRQn
|
||||
|
||||
/*
|
||||
* USART units.
|
||||
*/
|
||||
#define STM32_USART1_HANDLER USART1_IRQHandler
|
||||
#define STM32_USART2_HANDLER USART2_IRQHandler
|
||||
#define STM32_USART3_HANDLER USART3_IRQHandler
|
||||
#define STM32_UART4_HANDLER UART4_IRQHandler
|
||||
#define STM32_UART5_HANDLER UART5_IRQHandler
|
||||
#define STM32_USART6_HANDLER USART6_IRQHandler
|
||||
|
||||
#define STM32_USART1_NUMBER USART1_IRQn
|
||||
#define STM32_USART2_NUMBER USART2_IRQn
|
||||
#define STM32_USART3_NUMBER USART3_IRQn
|
||||
#define STM32_UART4_NUMBER UART4_IRQn
|
||||
#define STM32_UART5_NUMBER UART5_IRQn
|
||||
#define STM32_USART6_NUMBER USART6_IRQn
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _STM32_ISR_H_ */
|
||||
|
||||
/** @} */
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,161 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
||||
2011,2012,2013 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
---
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes ChibiOS/RT, without being obliged to provide
|
||||
the source code for any proprietary components. See the file exception.txt
|
||||
for full details of how and when the exception can be applied.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ST32F405xG memory setup.
|
||||
*/
|
||||
__main_stack_size__ = 0x0400;
|
||||
__process_stack_size__ = 0x0400;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash : org = 0x08000000, len = 1M
|
||||
ram : org = 0x20000000, len = 112k
|
||||
ethram : org = 0x2001C000, len = 16k
|
||||
ccmram : org = 0x10000000, len = 64k
|
||||
}
|
||||
|
||||
__ram_start__ = ORIGIN(ram);
|
||||
__ram_size__ = LENGTH(ram);
|
||||
__ram_end__ = __ram_start__ + __ram_size__;
|
||||
|
||||
ENTRY(ResetHandler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0;
|
||||
_text = .;
|
||||
|
||||
startup : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
KEEP(*(vectors))
|
||||
} > flash
|
||||
|
||||
constructors : ALIGN(4) SUBALIGN(4)
|
||||
{
|
||||
PROVIDE(__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE(__init_array_end = .);
|
||||
} > flash
|
||||
|
||||
destructors : ALIGN(4) SUBALIGN(4)
|
||||
{
|
||||
PROVIDE(__fini_array_start = .);
|
||||
KEEP(*(.fini_array))
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
PROVIDE(__fini_array_end = .);
|
||||
} > flash
|
||||
|
||||
.text : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
*(.text.startup.*)
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.glue_7t)
|
||||
*(.glue_7)
|
||||
*(.gcc*)
|
||||
} > flash
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > flash
|
||||
|
||||
.ARM.exidx : {
|
||||
PROVIDE(__exidx_start = .);
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
PROVIDE(__exidx_end = .);
|
||||
} > flash
|
||||
|
||||
.eh_frame_hdr :
|
||||
{
|
||||
*(.eh_frame_hdr)
|
||||
} > flash
|
||||
|
||||
.eh_frame : ONLY_IF_RO
|
||||
{
|
||||
*(.eh_frame)
|
||||
} > flash
|
||||
|
||||
.textalign : ONLY_IF_RO
|
||||
{
|
||||
. = ALIGN(8);
|
||||
} > flash
|
||||
|
||||
_etext = .;
|
||||
_textdata = _etext;
|
||||
|
||||
.stacks :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__main_stack_base__ = .;
|
||||
. += __main_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__main_stack_end__ = .;
|
||||
__process_stack_base__ = .;
|
||||
__main_thread_stack_base__ = .;
|
||||
. += __process_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__process_stack_end__ = .;
|
||||
__main_thread_stack_end__ = .;
|
||||
} > ram
|
||||
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_data = .);
|
||||
*(.data)
|
||||
. = ALIGN(4);
|
||||
*(.data.*)
|
||||
. = ALIGN(4);
|
||||
*(.ramtext)
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_edata = .);
|
||||
} > ram AT > flash
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_bss_start = .);
|
||||
*(.bss)
|
||||
. = ALIGN(4);
|
||||
*(.bss.*)
|
||||
. = ALIGN(4);
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_bss_end = .);
|
||||
} > ram
|
||||
}
|
||||
|
||||
PROVIDE(end = .);
|
||||
_end = .;
|
||||
|
||||
__heap_base__ = _end;
|
||||
__heap_end__ = __ram_end__;
|
|
@ -0,0 +1,161 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
||||
2011,2012,2013 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
---
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes ChibiOS/RT, without being obliged to provide
|
||||
the source code for any proprietary components. See the file exception.txt
|
||||
for full details of how and when the exception can be applied.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ST32F407xG memory setup.
|
||||
*/
|
||||
__main_stack_size__ = 0x0400;
|
||||
__process_stack_size__ = 0x0400;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash : org = 0x08000000, len = 1M
|
||||
ram : org = 0x20000000, len = 112k
|
||||
ethram : org = 0x2001C000, len = 16k
|
||||
ccmram : org = 0x10000000, len = 64k
|
||||
}
|
||||
|
||||
__ram_start__ = ORIGIN(ram);
|
||||
__ram_size__ = LENGTH(ram);
|
||||
__ram_end__ = __ram_start__ + __ram_size__;
|
||||
|
||||
ENTRY(ResetHandler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0;
|
||||
_text = .;
|
||||
|
||||
startup : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
KEEP(*(vectors))
|
||||
} > flash
|
||||
|
||||
constructors : ALIGN(4) SUBALIGN(4)
|
||||
{
|
||||
PROVIDE(__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE(__init_array_end = .);
|
||||
} > flash
|
||||
|
||||
destructors : ALIGN(4) SUBALIGN(4)
|
||||
{
|
||||
PROVIDE(__fini_array_start = .);
|
||||
KEEP(*(.fini_array))
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
PROVIDE(__fini_array_end = .);
|
||||
} > flash
|
||||
|
||||
.text : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
*(.text.startup.*)
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.glue_7t)
|
||||
*(.glue_7)
|
||||
*(.gcc*)
|
||||
} > flash
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > flash
|
||||
|
||||
.ARM.exidx : {
|
||||
PROVIDE(__exidx_start = .);
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
PROVIDE(__exidx_end = .);
|
||||
} > flash
|
||||
|
||||
.eh_frame_hdr :
|
||||
{
|
||||
*(.eh_frame_hdr)
|
||||
} > flash
|
||||
|
||||
.eh_frame : ONLY_IF_RO
|
||||
{
|
||||
*(.eh_frame)
|
||||
} > flash
|
||||
|
||||
.textalign : ONLY_IF_RO
|
||||
{
|
||||
. = ALIGN(8);
|
||||
} > flash
|
||||
|
||||
_etext = .;
|
||||
_textdata = _etext;
|
||||
|
||||
.stacks :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__main_stack_base__ = .;
|
||||
. += __main_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__main_stack_end__ = .;
|
||||
__process_stack_base__ = .;
|
||||
__main_thread_stack_base__ = .;
|
||||
. += __process_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__process_stack_end__ = .;
|
||||
__main_thread_stack_end__ = .;
|
||||
} > ram
|
||||
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_data = .);
|
||||
*(.data)
|
||||
. = ALIGN(4);
|
||||
*(.data.*)
|
||||
. = ALIGN(4);
|
||||
*(.ramtext)
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_edata = .);
|
||||
} > ram AT > flash
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_bss_start = .);
|
||||
*(.bss)
|
||||
. = ALIGN(4);
|
||||
*(.bss.*)
|
||||
. = ALIGN(4);
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_bss_end = .);
|
||||
} > ram
|
||||
}
|
||||
|
||||
PROVIDE(end = .);
|
||||
_end = .;
|
||||
|
||||
__heap_base__ = _end;
|
||||
__heap_end__ = __ram_end__;
|
|
@ -0,0 +1,182 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
||||
2011,2012,2013 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
---
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes ChibiOS/RT, without being obliged to provide
|
||||
the source code for any proprietary components. See the file exception.txt
|
||||
for full details of how and when the exception can be applied.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ST32F407xG memory setup.
|
||||
*/
|
||||
__main_stack_size__ = 0x0400;
|
||||
__process_stack_size__ = 0x0400;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash : org = 0x08000000, len = 1M
|
||||
ram : org = 0x20000000, len = 112k
|
||||
ethram : org = 0x2001C000, len = 16k
|
||||
ccmram : org = 0x10000000, len = 64k
|
||||
}
|
||||
|
||||
__ram_start__ = ORIGIN(ram);
|
||||
__ram_size__ = LENGTH(ram);
|
||||
__ram_end__ = __ram_start__ + __ram_size__;
|
||||
|
||||
ENTRY(ResetHandler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0;
|
||||
_text = .;
|
||||
|
||||
startup : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
KEEP(*(vectors))
|
||||
} > flash
|
||||
|
||||
constructors : ALIGN(4) SUBALIGN(4)
|
||||
{
|
||||
PROVIDE(__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE(__init_array_end = .);
|
||||
} > flash
|
||||
|
||||
destructors : ALIGN(4) SUBALIGN(4)
|
||||
{
|
||||
PROVIDE(__fini_array_start = .);
|
||||
KEEP(*(.fini_array))
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
PROVIDE(__fini_array_end = .);
|
||||
} > flash
|
||||
|
||||
.text : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
*(.text.startup.*)
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.glue_7t)
|
||||
*(.glue_7)
|
||||
*(.gcc*)
|
||||
} > flash
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > flash
|
||||
|
||||
.ARM.exidx : {
|
||||
PROVIDE(__exidx_start = .);
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
PROVIDE(__exidx_end = .);
|
||||
} > flash
|
||||
|
||||
.eh_frame_hdr :
|
||||
{
|
||||
*(.eh_frame_hdr)
|
||||
} > flash
|
||||
|
||||
.eh_frame : ONLY_IF_RO
|
||||
{
|
||||
*(.eh_frame)
|
||||
} > flash
|
||||
|
||||
.textalign : ONLY_IF_RO
|
||||
{
|
||||
. = ALIGN(8);
|
||||
} > flash
|
||||
|
||||
_etext = .;
|
||||
_textdata = _etext;
|
||||
|
||||
.stacks :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__main_stack_base__ = .;
|
||||
. += __main_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__main_stack_end__ = .;
|
||||
__process_stack_base__ = .;
|
||||
__main_thread_stack_base__ = .;
|
||||
. += __process_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__process_stack_end__ = .;
|
||||
__main_thread_stack_end__ = .;
|
||||
} > ccmram
|
||||
|
||||
.ccm :
|
||||
{
|
||||
PROVIDE(_cmm_start = .);
|
||||
. = ALIGN(4);
|
||||
*(.bss.mainthread.*)
|
||||
. = ALIGN(4);
|
||||
*(.bss._idle_thread_wa)
|
||||
. = ALIGN(4);
|
||||
*(.bss.rlist)
|
||||
. = ALIGN(4);
|
||||
*(.bss.vtlist)
|
||||
. = ALIGN(4);
|
||||
*(.bss.endmem)
|
||||
. = ALIGN(4);
|
||||
*(.bss.nextmem)
|
||||
. = ALIGN(4);
|
||||
*(.bss.default_heap)
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_cmm_end = .);
|
||||
} > ccmram
|
||||
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_data = .);
|
||||
*(.data)
|
||||
. = ALIGN(4);
|
||||
*(.data.*)
|
||||
. = ALIGN(4);
|
||||
*(.ramtext)
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_edata = .);
|
||||
} > ram AT > flash
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_bss_start = .);
|
||||
*(.bss)
|
||||
. = ALIGN(4);
|
||||
*(.bss.*)
|
||||
. = ALIGN(4);
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_bss_end = .);
|
||||
} > ram
|
||||
}
|
||||
|
||||
PROVIDE(end = .);
|
||||
_end = .;
|
||||
|
||||
__heap_base__ = _end;
|
||||
__heap_end__ = __ram_end__;
|
|
@ -5067,7 +5067,9 @@ typedef struct
|
|||
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
|
||||
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
|
||||
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
|
||||
#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
|
||||
/* CHIBIOS FIX */
|
||||
/*#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)*/
|
||||
#define RCC_AHB1RSTR_OTGHSRST ((uint32_t)0x10000000)
|
||||
|
||||
/******************** Bit definition for RCC_AHB2RSTR register **************/
|
||||
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
|
||||
|
|
Loading…
Reference in New Issue