I2C. Waits moved from ISR.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3161 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -48,12 +48,23 @@ static volatile uint16_t dbgSR1 = 0;
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static volatile uint16_t dbgSR2 = 0;
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static volatile uint16_t dbgCR1 = 0;
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static volatile uint16_t dbgCR2 = 0;
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static uint32_t polling_time_worst = 0;
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static uint32_t polling_time_begin = 0;
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static uint32_t polling_time_delta = 0;
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#endif /* CH_DBG_ENABLE_ASSERTS */
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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#if STM32_I2C_USE_POLLING_WAIT
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#else
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VirtualTimer i2c_waiting_vt;
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#endif /* STM32_I2C_USE_POLLING_WAIT */
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/* defines for convenience purpose */
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#define txBuffp (i2cp->txbuff_p)
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#define rxBuffp (i2cp->rxbuff_p)
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@ -113,8 +124,6 @@ void _i2c_ev6_master_rec_mode_selected(I2CDriver *i2cp){
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case I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED: /* only an single byte to receive */
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dp->CR1 &= (uint16_t)~I2C_CR1_ACK; /* Clear ACK */
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dp->CR1 |= I2C_CR1_STOP; /* Program the STOP */
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while(dp->CR1 & I2C_CR1_STOP)
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;
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break;
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case I2C_EV6_1_MASTER_REC_2BTR_MODE_SELECTED: /* only two bytes to receive */
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@ -146,14 +155,14 @@ void _i2c_ev7_master_rec_byte_qued(I2CDriver *i2cp){
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dp->CR1 &= (uint16_t)~I2C_CR1_ACK; /* Clear ACK */
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*rxBuffp = dp->DR; /* Read the DataN-2. This clear the RXE & BFT flags and launch the DataN exception in the shift register (ending the SCL stretch) */
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rxBuffp++;
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chSysLockFromIsr();
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dp->CR1 |= I2C_CR1_STOP; /* Program the STOP */
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*rxBuffp = dp->DR; /* Read the DataN-1 */
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chSysUnlockFromIsr();
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rxBuffp++;
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i2cp->rxbytes -= 2; /* Decrement the number of readed bytes */
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i2cp->flags = 0;
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dp->CR2 |= I2C_CR2_ITBUFEN; /* ready for read DataN. Enable interrupt for next (and last) RxNE event*/
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while(dp->CR1 & I2C_CR1_STOP)
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;
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break;
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case I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS:
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@ -161,15 +170,15 @@ void _i2c_ev7_master_rec_byte_qued(I2CDriver *i2cp){
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* DataN-1 and DataN are received */
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dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN;
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dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
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chSysLockFromIsr();
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dp->CR1 |= I2C_CR1_STOP; /* Program the STOP */
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*rxBuffp = dp->DR; /* Read the DataN-1*/
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rxBuffp++;
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*rxBuffp = dp->DR; /* Read the DataN*/
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chSysUnlockFromIsr();
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i2cp->rxbytes = 0;
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i2cp->flags = 0;
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_i2c_isr_code(i2cp, i2cp->id_slave_config); /* Portable I2C ISR code defined in the high level driver. */
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while(dp->CR1 & I2C_CR1_STOP)
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;
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break;
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case I2C_FLG_MASTER_RECEIVER:
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@ -250,8 +259,6 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
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if (i2cp->rxbytes == 0){ /* if nothing to read then generate stop */
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dp->CR1 |= I2C_CR1_STOP;
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_i2c_isr_code(i2cp, i2cp->id_slave_config); /* Portable I2C ISR code defined in the high level driver. */
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while(dp->CR1 & I2C_CR1_STOP)
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;
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}
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else{ /* start reading operation */
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i2c_lld_master_transceive(i2cp);
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@ -629,6 +636,17 @@ void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr,
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i2cp->flags = 0;
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i2cp->errors = 0;
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#if CH_DBG_ENABLE_ASSERTS
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polling_time_begin = PWMD4.tim->CNT;
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#endif
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while(i2cp->id_i2c->CR1 & I2C_CR1_STOP)
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;
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#if CH_DBG_ENABLE_ASSERTS
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polling_time_delta = PWMD4.tim->CNT - polling_time_begin;
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if (polling_time_delta > polling_time_worst)
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polling_time_worst = polling_time_delta;
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#endif
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i2cp->id_i2c->CR1 &= ~I2C_CR1_POS;
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i2cp->id_i2c->CR1 |= I2C_CR1_START; /* send start bit */
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i2cp->id_i2c->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN); /* enable ERR, EVT & BUF ITs */
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@ -668,6 +686,18 @@ void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr,
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i2cp->flags = I2C_FLG_MASTER_RECEIVER;
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i2cp->errors = 0;
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#if CH_DBG_ENABLE_ASSERTS
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polling_time_begin = PWMD4.tim->CNT;
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#endif
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while(i2cp->id_i2c->CR1 & I2C_CR1_STOP)
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;
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#if CH_DBG_ENABLE_ASSERTS
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polling_time_delta = PWMD4.tim->CNT - polling_time_begin;
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if (polling_time_delta > polling_time_worst)
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polling_time_worst = polling_time_delta;
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#endif
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i2cp->id_i2c->CR1 |= I2C_CR1_ACK; /* acknowledge returned */
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i2cp->id_i2c->CR1 &= ~I2C_CR1_POS;
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@ -19,6 +19,17 @@
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Waiting method switch.
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* @details If set to @p TRUE than waiting of STOP generation will use
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* while() loop polling. Otherwise -- virtual timer will be used.
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* @note The default is @p TRUE.
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* @note Virtual timer resolution is 1/@p CH_FREQUENCY seconds.
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*/
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#if !defined(STM32_I2C_USE_POLLING_WAIT) || defined(__DOXYGEN__)
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#define STM32_I2C_USE_POLLING_WAIT TRUE
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#endif
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/**
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* @brief I2C1 driver enable switch.
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* @details If set to @p TRUE the support for I2C1 is included.
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