diff --git a/demos/STM32/RT-STM32L432KC-NUCLEO32/cfg/mcuconf.h b/demos/STM32/RT-STM32L432KC-NUCLEO32/cfg/mcuconf.h index 58a18c62f..ffd551d1d 100644 --- a/demos/STM32/RT-STM32L432KC-NUCLEO32/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32L432KC-NUCLEO32/cfg/mcuconf.h @@ -102,10 +102,18 @@ #define STM32_IRQ_EXTI19_PRIORITY 6 #define STM32_IRQ_EXTI20_PRIORITY 6 #define STM32_IRQ_EXTI21_22_PRIORITY 15 + #define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7 #define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7 #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 #define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 3 +#define STM32_IRQ_USART2_PRIORITY 3 +#define STM32_IRQ_LPUART1_PRIORITY 3 /* * ADC driver system settings. @@ -146,10 +154,6 @@ #define STM32_GPT_USE_TIM7 FALSE #define STM32_GPT_USE_TIM15 FALSE #define STM32_GPT_USE_TIM16 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 /* * I2C driver system settings. @@ -173,8 +177,7 @@ #define STM32_ICU_USE_TIM1 FALSE #define STM32_ICU_USE_TIM2 FALSE #define STM32_ICU_USE_TIM15 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_USE_TIM16 FALSE /* * PWM driver system settings. @@ -184,8 +187,6 @@ #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM15 FALSE #define STM32_PWM_USE_TIM16 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 /* * RTC driver system settings. @@ -240,10 +241,6 @@ #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") /* diff --git a/demos/STM32/RT-STM32L452RE-NUCLEO64-P/cfg/mcuconf.h b/demos/STM32/RT-STM32L452RE-NUCLEO64-P/cfg/mcuconf.h index dcd4080b1..8cd6c7e00 100644 --- a/demos/STM32/RT-STM32L452RE-NUCLEO64-P/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32L452RE-NUCLEO64-P/cfg/mcuconf.h @@ -79,7 +79,9 @@ #define STM32_UART4SEL STM32_UART4SEL_SYSCLK #define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK #define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK +#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK #define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK +#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 #define STM32_SAI1SEL STM32_SAI1SEL_OFF @@ -103,10 +105,20 @@ #define STM32_IRQ_EXTI19_PRIORITY 6 #define STM32_IRQ_EXTI20_PRIORITY 6 #define STM32_IRQ_EXTI21_22_PRIORITY 15 + #define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7 #define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7 #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 #define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 3 +#define STM32_IRQ_USART2_PRIORITY 3 +#define STM32_IRQ_USART3_PRIORITY 3 +#define STM32_IRQ_UART4_PRIORITY 3 +#define STM32_IRQ_LPUART1_PRIORITY 3 /* * ADC driver system settings. @@ -115,7 +127,9 @@ #define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 /* * CAN driver system settings. @@ -126,15 +140,10 @@ /* * DAC driver system settings. */ -#define STM32_DAC_DUAL_MODE FALSE #define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) /* * GPT driver system settings. @@ -145,11 +154,6 @@ #define STM32_GPT_USE_TIM6 FALSE #define STM32_GPT_USE_TIM15 FALSE #define STM32_GPT_USE_TIM16 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 /* * I2C driver system settings. @@ -165,8 +169,8 @@ #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C1_IRQ_PRIORITY 5 #define STM32_I2C_I2C2_IRQ_PRIORITY 5 #define STM32_I2C_I2C3_IRQ_PRIORITY 5 @@ -184,8 +188,7 @@ #define STM32_ICU_USE_TIM2 FALSE #define STM32_ICU_USE_TIM3 FALSE #define STM32_ICU_USE_TIM15 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_USE_TIM16 FALSE /* * PWM driver system settings. @@ -196,8 +199,6 @@ #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM15 FALSE #define STM32_PWM_USE_TIM16 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 /* * RTC driver system settings. @@ -259,6 +260,11 @@ #define STM32_ST_IRQ_PRIORITY 8 #define STM32_ST_USE_TIMER 2 +/* + * TRNG driver system settings. + */ +#define STM32_TRNG_USE_RNG1 FALSE + /* * UART driver system settings. */ @@ -287,10 +293,9 @@ /* * USB driver system settings. */ -#define STM32_USB_USE_USB1 FALSE -#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE -#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 -#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 /* * WDG driver system settings. diff --git a/demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST/cfg/chconf.h b/demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST/cfg/chconf.h index 53b3224c8..eb3c8a6ee 100644 --- a/demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST/cfg/chconf.h +++ b/demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST/cfg/chconf.h @@ -751,6 +751,8 @@ /* Port-specific settings (override port settings defaulted in chcore.h). */ /*===========================================================================*/ +#define PORT_USE_SYSCALL TRUE + #endif /* CHCONF_H */ /** @} */ diff --git a/demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST/main.c b/demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST/main.c index 91bb52c25..26dfb6945 100644 --- a/demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST/main.c +++ b/demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST/main.c @@ -53,14 +53,14 @@ static THD_FUNCTION(Thread1, arg) { */ static THD_WORKING_AREA(waUnprivileged1, 128); static THD_FUNCTION(Unprivileged1, arg) { - extern uint32_t __flash7_start__, __flash7_end__, - __ram7_start__, __ram7_end__; + extern uint32_t __flash7_base__, __flash7_end__, + __ram7_base__, __ram7_end__; static const sb_config_t sb_config = { .code_region = 0U, .data_region = 1U, .regions = { - {(uint32_t)&__flash7_start__, (uint32_t)&__flash7_end__, false}, - {(uint32_t)&__ram7_start__, (uint32_t)&__ram7_end__, true} + {(uint32_t)&__flash7_base__, (uint32_t)&__flash7_end__, false}, + {(uint32_t)&__ram7_base__, (uint32_t)&__ram7_end__, true} }, .stdin_stream = (SandboxStream *)&SD2, .stdout_stream = (SandboxStream *)&SD2, diff --git a/demos/STM32/RT-STM32L496ZG-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32L496ZG-NUCLEO144/cfg/mcuconf.h index 5d8a4fcba..f94abb79e 100644 --- a/demos/STM32/RT-STM32L496ZG-NUCLEO144/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32L496ZG-NUCLEO144/cfg/mcuconf.h @@ -112,10 +112,26 @@ #define STM32_IRQ_EXTI19_PRIORITY 6 #define STM32_IRQ_EXTI20_PRIORITY 6 #define STM32_IRQ_EXTI21_22_PRIORITY 6 + #define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7 #define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7 #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 #define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 +#define STM32_IRQ_TIM8_UP_PRIORITY 7 +#define STM32_IRQ_TIM8_CC_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 3 +#define STM32_IRQ_USART2_PRIORITY 3 +#define STM32_IRQ_USART3_PRIORITY 3 +#define STM32_IRQ_UART4_PRIORITY 3 +#define STM32_IRQ_UART5_PRIORITY 3 +#define STM32_IRQ_LPUART1_PRIORITY 3 /* * ADC driver system settings. @@ -172,14 +188,6 @@ #define STM32_GPT_USE_TIM15 FALSE #define STM32_GPT_USE_TIM16 FALSE #define STM32_GPT_USE_TIM17 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 /* * I2C driver system settings. @@ -187,6 +195,7 @@ #define STM32_I2C_USE_I2C1 FALSE #define STM32_I2C_USE_I2C2 FALSE #define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE #define STM32_I2C_BUSY_TIMEOUT 50 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) @@ -194,12 +203,16 @@ #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_I2C_I2C1_IRQ_PRIORITY 5 #define STM32_I2C_I2C2_IRQ_PRIORITY 5 #define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 #define STM32_I2C_I2C1_DMA_PRIORITY 3 #define STM32_I2C_I2C2_DMA_PRIORITY 3 #define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* @@ -212,12 +225,8 @@ #define STM32_ICU_USE_TIM5 FALSE #define STM32_ICU_USE_TIM8 FALSE #define STM32_ICU_USE_TIM15 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_USE_TIM16 FALSE +#define STM32_ICU_USE_TIM17 FALSE /* * PWM driver system settings. @@ -232,12 +241,6 @@ #define STM32_PWM_USE_TIM15 FALSE #define STM32_PWM_USE_TIM16 FALSE #define STM32_PWM_USE_TIM17 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 /* * RTC driver system settings. diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h index 23aa90268..46bdfdb99 100644 --- a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h @@ -332,20 +332,6 @@ #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE -/* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 TRUE -#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)|\ - STM32_DMA_STREAM_ID_MSK(2, 4)) -#define STM32_DAC1_CH1_DMA_CHN 0x00003600 - -#define STM32_HAS_DAC1_CH2 TRUE -#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)|\ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_DAC1_CH2_DMA_CHN 0x00035000 - -#define STM32_HAS_DAC2_CH1 FALSE -#define STM32_HAS_DAC2_CH2 FALSE - /* DMA attributes.*/ #define STM32_ADVANCED_DMA TRUE #define STM32_DMA_SUPPORTS_DMAMUX FALSE diff --git a/tools/ftl/processors/conf/mcuconf_stm32l453xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32l452xx/mcuconf.h.ftl similarity index 80% rename from tools/ftl/processors/conf/mcuconf_stm32l453xx/mcuconf.h.ftl rename to tools/ftl/processors/conf/mcuconf_stm32l452xx/mcuconf.h.ftl index 9ce2519f0..89507e862 100644 --- a/tools/ftl/processors/conf/mcuconf_stm32l453xx/mcuconf.h.ftl +++ b/tools/ftl/processors/conf/mcuconf_stm32l452xx/mcuconf.h.ftl @@ -43,8 +43,7 @@ #define MCUCONF_H #define STM32L4xx_MCUCONF -#define STM32L476_MCUCONF -#define STM32L486_MCUCONF +#define STM32L452_MCUCONF /* * HAL driver system settings. @@ -54,6 +53,7 @@ #define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"} #define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"} #define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"FALSE"} +#define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"FALSE"} #define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"} #define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"FALSE"} #define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"} @@ -64,6 +64,7 @@ #define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_MSI"} #define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"1"} #define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"80"} +#define STM32_PLLPDIV_VALUE ${doc.STM32_PLLPDIV_VALUE!"0"} #define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"7"} #define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"6"} #define STM32_PLLR_VALUE ${doc.STM32_PLLR_VALUE!"4"} @@ -75,12 +76,10 @@ #define STM32_MCOPRE ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"} #define STM32_LSCOSEL ${doc.STM32_LSCOSEL!"STM32_LSCOSEL_NOCLOCK"} #define STM32_PLLSAI1N_VALUE ${doc.STM32_PLLSAI1N_VALUE!"72"} +#define STM32_PLLSAI1PDIV_VALUE ${doc.STM32_PLLSAI1PDIV_VALUE!"6"} #define STM32_PLLSAI1P_VALUE ${doc.STM32_PLLSAI1P_VALUE!"7"} #define STM32_PLLSAI1Q_VALUE ${doc.STM32_PLLSAI1Q_VALUE!"6"} #define STM32_PLLSAI1R_VALUE ${doc.STM32_PLLSAI1R_VALUE!"6"} -#define STM32_PLLSAI2N_VALUE ${doc.STM32_PLLSAI2N_VALUE!"72"} -#define STM32_PLLSAI2P_VALUE ${doc.STM32_PLLSAI2P_VALUE!"7"} -#define STM32_PLLSAI2R_VALUE ${doc.STM32_PLLSAI2R_VALUE!"6"} /* * Peripherals clock sources. @@ -89,19 +88,17 @@ #define STM32_USART2SEL ${doc.STM32_USART2SEL!"STM32_USART2SEL_SYSCLK"} #define STM32_USART3SEL ${doc.STM32_USART3SEL!"STM32_USART3SEL_SYSCLK"} #define STM32_UART4SEL ${doc.STM32_UART4SEL!"STM32_UART4SEL_SYSCLK"} -#define STM32_UART5SEL ${doc.STM32_UART5SEL!"STM32_UART5SEL_SYSCLK"} #define STM32_LPUART1SEL ${doc.STM32_LPUART1SEL!"STM32_LPUART1SEL_SYSCLK"} #define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_SYSCLK"} #define STM32_I2C2SEL ${doc.STM32_I2C2SEL!"STM32_I2C2SEL_SYSCLK"} #define STM32_I2C3SEL ${doc.STM32_I2C3SEL!"STM32_I2C3SEL_SYSCLK"} +#define STM32_I2C4SEL ${doc.STM32_I2C4SEL!"STM32_I2C4SEL_SYSCLK"} #define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"} #define STM32_LPTIM2SEL ${doc.STM32_LPTIM2SEL!"STM32_LPTIM2SEL_PCLK1"} #define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"} -#define STM32_SAI2SEL ${doc.STM32_SAI2SEL!"STM32_SAI2SEL_OFF"} #define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_PLL"} #define STM32_ADCSEL ${doc.STM32_ADCSEL!"STM32_ADCSEL_SYSCLK"} #define STM32_SWPMI1SEL ${doc.STM32_SWPMI1SEL!"STM32_SWPMI1SEL_PCLK1"} -#define STM32_DFSDMSEL ${doc.STM32_DFSDMSEL!"STM32_DFSDMSEL_PCLK2"} #define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"} /* @@ -126,39 +123,23 @@ #define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"} #define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"7"} #define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"7"} -#define STM32_IRQ_TIM4_PRIORITY ${doc.STM32_IRQ_TIM4_PRIORITY!"7"} -#define STM32_IRQ_TIM5_PRIORITY ${doc.STM32_IRQ_TIM5_PRIORITY!"7"} #define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"7"} -#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"7"} -#define STM32_IRQ_TIM8_UP_PRIORITY ${doc.STM32_IRQ_TIM8_UP_PRIORITY!"7"} -#define STM32_IRQ_TIM8_CC_PRIORITY ${doc.STM32_IRQ_TIM8_CC_PRIORITY!"7"} #define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"3"} #define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"3"} #define STM32_IRQ_USART3_PRIORITY ${doc.STM32_IRQ_USART3_PRIORITY!"3"} #define STM32_IRQ_UART4_PRIORITY ${doc.STM32_IRQ_UART4_PRIORITY!"3"} -#define STM32_IRQ_UART5_PRIORITY ${doc.STM32_IRQ_UART5_PRIORITY!"3"} #define STM32_IRQ_LPUART1_PRIORITY ${doc.STM32_IRQ_LPUART1_PRIORITY!"3"} /* * ADC driver system settings. */ -#define STM32_ADC_DUAL_MODE ${doc.STM32_ADC_DUAL_MODE!"FALSE"} #define STM32_ADC_COMPACT_SAMPLES ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"} #define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"} -#define STM32_ADC_USE_ADC2 ${doc.STM32_ADC_USE_ADC2!"FALSE"} -#define STM32_ADC_USE_ADC3 ${doc.STM32_ADC_USE_ADC3!"FALSE"} #define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"} -#define STM32_ADC_ADC2_DMA_STREAM ${doc.STM32_ADC_ADC2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"} -#define STM32_ADC_ADC3_DMA_STREAM ${doc.STM32_ADC_ADC3_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"} #define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"} -#define STM32_ADC_ADC2_DMA_PRIORITY ${doc.STM32_ADC_ADC2_DMA_PRIORITY!"2"} -#define STM32_ADC_ADC3_DMA_PRIORITY ${doc.STM32_ADC_ADC3_DMA_PRIORITY!"2"} #define STM32_ADC_ADC12_IRQ_PRIORITY ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"} -#define STM32_ADC_ADC3_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_IRQ_PRIORITY!"5"} #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"5"} -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC2_DMA_IRQ_PRIORITY!"5"} -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_DMA_IRQ_PRIORITY!"5"} #define STM32_ADC_ADC123_CLOCK_MODE ${doc.STM32_ADC_ADC123_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV1"} /* @@ -170,15 +151,10 @@ /* * DAC driver system settings. */ -#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"} #define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"} -#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"} #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"} -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"} #define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"} -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"} #define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"} -#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"} /* * GPT driver system settings. @@ -186,14 +162,9 @@ #define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"} #define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"} #define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"} -#define STM32_GPT_USE_TIM4 ${doc.STM32_GPT_USE_TIM4!"FALSE"} -#define STM32_GPT_USE_TIM5 ${doc.STM32_GPT_USE_TIM5!"FALSE"} #define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"} -#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"} -#define STM32_GPT_USE_TIM8 ${doc.STM32_GPT_USE_TIM8!"FALSE"} #define STM32_GPT_USE_TIM15 ${doc.STM32_GPT_USE_TIM15!"FALSE"} #define STM32_GPT_USE_TIM16 ${doc.STM32_GPT_USE_TIM16!"FALSE"} -#define STM32_GPT_USE_TIM17 ${doc.STM32_GPT_USE_TIM17!"FALSE"} /* * I2C driver system settings. @@ -201,6 +172,7 @@ #define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"} #define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"} #define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"} +#define STM32_I2C_USE_I2C4 ${doc.STM32_I2C_USE_I2C4!"FALSE"} #define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"} #define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"} #define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"} @@ -208,12 +180,16 @@ #define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"} #define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"} #define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"} +#define STM32_I2C_I2C4_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"} +#define STM32_I2C_I2C4_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"} #define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"} #define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"} #define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"} +#define STM32_I2C_I2C4_IRQ_PRIORITY ${doc.STM32_I2C_I2C4_IRQ_PRIORITY!"5"} #define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"} #define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"} #define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"} +#define STM32_I2C_I2C4_DMA_PRIORITY ${doc.STM32_I2C_I2C4_DMA_PRIORITY!"3"} #define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"} /* @@ -222,12 +198,8 @@ #define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"} #define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"} #define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"} -#define STM32_ICU_USE_TIM4 ${doc.STM32_ICU_USE_TIM4!"FALSE"} -#define STM32_ICU_USE_TIM5 ${doc.STM32_ICU_USE_TIM5!"FALSE"} -#define STM32_ICU_USE_TIM8 ${doc.STM32_ICU_USE_TIM8!"FALSE"} #define STM32_ICU_USE_TIM15 ${doc.STM32_ICU_USE_TIM15!"FALSE"} #define STM32_ICU_USE_TIM16 ${doc.STM32_ICU_USE_TIM16!"FALSE"} -#define STM32_ICU_USE_TIM17 ${doc.STM32_ICU_USE_TIM17!"FALSE"} /* * PWM driver system settings. @@ -236,12 +208,8 @@ #define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"} #define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"} #define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"} -#define STM32_PWM_USE_TIM4 ${doc.STM32_PWM_USE_TIM4!"FALSE"} -#define STM32_PWM_USE_TIM5 ${doc.STM32_PWM_USE_TIM5!"FALSE"} -#define STM32_PWM_USE_TIM8 ${doc.STM32_PWM_USE_TIM8!"FALSE"} #define STM32_PWM_USE_TIM15 ${doc.STM32_PWM_USE_TIM15!"FALSE"} #define STM32_PWM_USE_TIM16 ${doc.STM32_PWM_USE_TIM16!"FALSE"} -#define STM32_PWM_USE_TIM17 ${doc.STM32_PWM_USE_TIM17!"FALSE"} /* * RTC driver system settings. @@ -270,13 +238,11 @@ #define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"} #define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"FALSE"} #define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"} -#define STM32_SERIAL_USE_UART5 ${doc.STM32_SERIAL_USE_UART5!"FALSE"} #define STM32_SERIAL_USE_LPUART1 ${doc.STM32_SERIAL_USE_LPUART1!"FALSE"} #define STM32_SERIAL_USART1_PRIORITY ${doc.STM32_SERIAL_USART1_PRIORITY!"12"} #define STM32_SERIAL_USART2_PRIORITY ${doc.STM32_SERIAL_USART2_PRIORITY!"12"} #define STM32_SERIAL_USART3_PRIORITY ${doc.STM32_SERIAL_USART3_PRIORITY!"12"} #define STM32_SERIAL_UART4_PRIORITY ${doc.STM32_SERIAL_UART4_PRIORITY!"12"} -#define STM32_SERIAL_UART5_PRIORITY ${doc.STM32_SERIAL_UART5_PRIORITY!"12"} #define STM32_SERIAL_LPUART1_PRIORITY ${doc.STM32_SERIAL_LPUART1_PRIORITY!"12"} /* @@ -317,7 +283,6 @@ #define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"} #define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"} #define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"} -#define STM32_UART_USE_UART5 ${doc.STM32_UART_USE_UART5!"FALSE"} #define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"} #define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"} #define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"} @@ -326,18 +291,14 @@ #define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"} #define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"} #define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"} -#define STM32_UART_UART5_RX_DMA_STREAM ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"} -#define STM32_UART_UART5_TX_DMA_STREAM ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"} #define STM32_UART_USART1_IRQ_PRIORITY ${doc.STM32_UART_USART1_IRQ_PRIORITY!"12"} #define STM32_UART_USART2_IRQ_PRIORITY ${doc.STM32_UART_USART2_IRQ_PRIORITY!"12"} #define STM32_UART_USART3_IRQ_PRIORITY ${doc.STM32_UART_USART3_IRQ_PRIORITY!"12"} #define STM32_UART_UART4_IRQ_PRIORITY ${doc.STM32_UART_UART4_IRQ_PRIORITY!"12"} -#define STM32_UART_UART5_IRQ_PRIORITY ${doc.STM32_UART_UART5_IRQ_PRIORITY!"12"} #define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"} #define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"} #define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"} #define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"} -#define STM32_UART_UART5_DMA_PRIORITY ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"} #define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"} /* diff --git a/tools/updater/update_mcuconf_stm32l452xx.sh b/tools/updater/update_mcuconf_stm32l452xx.sh new file mode 100644 index 000000000..354babdd5 --- /dev/null +++ b/tools/updater/update_mcuconf_stm32l452xx.sh @@ -0,0 +1,29 @@ +#!/bin/bash +if [ $# -eq 2 ] + then + if [ $1 = "rootpath" ] + then + find $2 -name "mcuconf.h" -exec bash update_mcuconf_stm32l452xx.sh "{}" \; + else + echo "Usage: update_mcuconf_stm32l452xx.sh [rootpath ]" + fi +elif [ $# -eq 1 ] +then + declare conffile=$(<$1) + if egrep -q "STM32L452_MCUCONF" <<< "$conffile" + then + echo Processing: $1 + egrep -e "\#define\s+[a-zA-Z0-9_()]*\s+[a-zA-Z0-9_]" <<< "$conffile" | sed -r 's/\#define\s+([a-zA-Z0-9_]*)(\([^)]*\))?\s+/\1=/g' > ./values.txt + if ! fmpp -q -C conf.fmpp -S ../ftl/processors/conf/mcuconf_stm32l452xx + then + echo + echo "aborted" + exit 1 + fi + cp ./mcuconf.h $1 + rm ./mcuconf.h ./values.txt + fi +else + echo "Usage: update_mcuconf_stm32l452xx.sh [rootpath ]" + echo " update_mcuconf_stm32l452xx.sh ]" +fi