git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5841 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
8dfb201307
commit
e4b51ee2fa
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@ -51,12 +51,12 @@ PROJECT = ch
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# Imported source files
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CHIBIOS = ../..
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#include $(CHIBIOS)/boards/ST_EVB_SPC560D/board.mk
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#include $(CHIBIOS)/os/hal/platforms/SPC560Dxx/platform.mk
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#include $(CHIBIOS)/os/hal/hal.mk
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include $(CHIBIOS)/boards/ST_EVB_SPC560D/board.mk
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include $(CHIBIOS)/os/hal/platforms/SPC560Dxx/platform.mk
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include $(CHIBIOS)/os/hal/hal.mk
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include $(CHIBIOS)/os/ports/GCC/PPC/SPC560Dxx/port.mk
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include $(CHIBIOS)/os/kernel/kernel.mk
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#include $(CHIBIOS)/test/test.mk
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include $(CHIBIOS)/test/test.mk
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# Define linker script file here
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LDSCRIPT= $(PORTLD)/SPC560D40.ld
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@ -68,10 +68,10 @@ CSRC = $(PORTSRC) \
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$(HALSRC) \
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$(PLATFORMSRC) \
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$(BOARDSRC) \
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$(CHIBIOS)/os/various/evtimer.c \
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$(CHIBIOS)/os/various/shell.c \
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$(CHIBIOS)/os/various/chprintf.c \
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main.c
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# $(CHIBIOS)/os/various/evtimer.c \
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# $(CHIBIOS)/os/various/shell.c \
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# $(CHIBIOS)/os/various/chprintf.c \
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# C++ sources here.
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CPPSRC =
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@ -86,6 +86,7 @@ static const ShellConfig shell_cfg1 = {
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(BaseSequentialStream *)&SD1,
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commands
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};
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#endif
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/*
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* LEDs blinker thread, times are in milliseconds.
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@ -156,7 +157,6 @@ static msg_t Thread1(void *arg) {
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}
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return 0;
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}
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#endif
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/*
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* Application entry point.
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@ -171,18 +171,18 @@ int main(void) {
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* - Kernel initialization, the main() function becomes a thread and the
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* RTOS is active.
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*/
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// halInit();
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halInit();
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chSysInit();
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/*
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* Activates the serial driver 1 using the driver default configuration.
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*/
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// sdStart(&SD1, NULL);
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sdStart(&SD1, NULL);
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/*
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* Creates the blinker thread.
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*/
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// chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
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chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
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/*
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* Normal main() thread activity.
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@ -15,8 +15,8 @@
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*/
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/**
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* @file SPC560BCxx/hal_lld.c
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* @brief SPC560B/Cxx HAL subsystem low level driver source.
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* @file SPC560Dxx/hal_lld.c
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* @brief SPC560Dxx HAL subsystem low level driver source.
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*
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* @addtogroup HAL
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* @{
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@ -15,8 +15,8 @@
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*/
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/**
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* @file SPC560BCxx/hal_lld.h
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* @brief SPC560B/Cxx HAL subsystem low level driver header.
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* @file SPC560Dxx/hal_lld.h
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* @brief SPC560Dxx HAL subsystem low level driver header.
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* @pre This module requires the following macros to be defined in the
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* @p board.h file:
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* - SPC5_XOSC_CLK.
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@ -30,8 +30,8 @@
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "xpc560bc.h"
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#include "spc560bc_registry.h"
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#include "xpc560d.h"
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#include "spc560d_registry.h"
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/*===========================================================================*/
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/* Driver constants. */
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@ -46,7 +46,7 @@
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* @name Platform identification
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* @{
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*/
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#define PLATFORM_NAME "SPC560B/Cxx Car Body and Convenience"
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#define PLATFORM_NAME "SPC560Dxx Car Body and Convenience"
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/** @} */
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/**
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@ -63,16 +63,6 @@
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*/
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#define SPC5_XOSC_CLK_MIN 4000000
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/**
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* @brief Maximum SXOSC clock frequency.
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*/
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#define SPC5_SXOSC_CLK_MAX 40000
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/**
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* @brief Minimum SXOSC clock frequency.
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*/
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#define SPC5_SXOSC_CLK_MIN 32000
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/**
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* @brief Maximum FMPLLs input clock frequency.
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*/
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@ -81,7 +71,7 @@
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/**
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* @brief Maximum FMPLLs input clock frequency.
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*/
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#define SPC5_FMPLLIN_MAX 64000000
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#define SPC5_FMPLLIN_MAX 48000000
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/**
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* @brief Maximum FMPLLs VCO clock frequency.
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@ -96,7 +86,7 @@
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/**
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* @brief Maximum FMPLL0 output clock frequency.
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*/
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#define SPC5_FMPLL0_CLK_MAX 64000000
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#define SPC5_FMPLL0_CLK_MAX 48000000
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/** @} */
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/**
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@ -247,7 +237,7 @@
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/**
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* @brief FMPLL0 IDF divider value.
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* @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
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* @note The default value is calculated for XOSC=8MHz and PHI=48MHz.
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*/
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#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
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#define SPC5_FMPLL0_IDF_VALUE 1
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@ -255,18 +245,18 @@
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/**
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* @brief FMPLL0 NDIV divider value.
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* @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
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* @note The default value is calculated for XOSC=8MHz and PHI=48MHz.
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*/
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#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
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#define SPC5_FMPLL0_NDIV_VALUE 32
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#define SPC5_FMPLL0_NDIV_VALUE 48
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#endif
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/**
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* @brief FMPLL0 ODF divider value.
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* @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
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* @note The default value is calculated for XOSC=8MHz and PHI=48MHz.
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*/
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#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
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#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
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#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV8
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#endif
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/**
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@ -639,7 +629,7 @@
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* Configuration-related checks.
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*/
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#if !defined(SPC560BCxx_MCUCONF)
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#error "Using a wrong mcuconf.h file, SPC560BCxx_MCUCONF not defined"
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#error "Using a wrong mcuconf.h file, SPC560Dxx_MCUCONF not defined"
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#endif
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/* Check on the XOSC frequency.*/
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@ -1,11 +1,11 @@
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# List of all the SPC560B/Cxx platform files.
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PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560BCxx/hal_lld.c \
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# List of all the SPC560Dxx platform files.
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PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Dxx/hal_lld.c \
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${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \
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${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \
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${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c
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# Required include directories
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PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560BCxx \
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PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560Dxx \
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${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \
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${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \
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${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1
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@ -15,26 +15,56 @@
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*/
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/**
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* @file SPC560BCxx/spc560bc_registry.h
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* @brief SPC560B/Cxx capabilities registry.
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* @file SPC560Dxx/spc560d_registry.h
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* @brief SPC560Dxx capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _SPC560BC_REGISTRY_H_
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#define _SPC560BC_REGISTRY_H_
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#ifndef _SPC560D_REGISTRY_H_
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#define _SPC560D_REGISTRY_H_
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name SPC560B/Cxx capabilities
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* @name SPC560Dxx capabilities
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* @{
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*/
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/* DSPI attribures.*/
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#define SPC5_HAS_DSPI0 TRUE
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#define SPC5_HAS_DSPI1 TRUE
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#define SPC5_HAS_DSPI2 FALSE
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#define SPC5_HAS_DSPI3 FALSE
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#define SPC5_HAS_DSPI4 FALSE
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#define SPC5_DSPI_FIFO_DEPTH 4
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#define SPC5_DSPI0_PCTL 4
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#define SPC5_DSPI1_PCTL 5
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#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
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#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
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#define SPC5_DSPI0_RX_DMA_DEV_ID 2
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#define SPC5_DSPI1_TX1_DMA_DEV_ID 3
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#define SPC5_DSPI1_TX2_DMA_DEV_ID 0
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#define SPC5_DSPI1_RX_DMA_DEV_ID 4
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#define SPC5_DSPI0_TFFF_HANDLER vector76
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#define SPC5_DSPI0_TFFF_NUMBER 76
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#define SPC5_DSPI1_TFFF_HANDLER vector96
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#define SPC5_DSPI1_TFFF_NUMBER 96
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#define SPC5_DSPI0_ENABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL)
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#define SPC5_DSPI0_DISABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL)
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#define SPC5_DSPI1_ENABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL)
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#define SPC5_DSPI1_DISABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL)
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/* eDMA attributes.*/
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#define SPC5_HAS_EDMA FALSE
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#define SPC5_HAS_EDMA TRUE
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#define SPC5_EDMA_NCHANNELS 16
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#define SPC5_EDMA_HAS_MUX TRUE
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/* LINFlex attributes.*/
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#define SPC5_HAS_LINFLEX0 TRUE
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@ -70,16 +100,7 @@
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#define SPC5_LINFLEX2_CLK (halSPCGetSystemClock() / \
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SPC5_PERIPHERAL1_CLK_DIV_VALUE)
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#define SPC5_HAS_LINFLEX3 TRUE
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#define SPC5_LINFLEX3_PCTL 51
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#define SPC5_LINFLEX3_RXI_HANDLER vector122
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#define SPC5_LINFLEX3_TXI_HANDLER vector123
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#define SPC5_LINFLEX3_ERR_HANDLER vector124
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#define SPC5_LINFLEX3_RXI_NUMBER 122
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#define SPC5_LINFLEX3_TXI_NUMBER 123
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#define SPC5_LINFLEX3_ERR_NUMBER 124
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#define SPC5_LINFLEX3_CLK (halSPCGetSystemClock() / \
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SPC5_PERIPHERAL1_CLK_DIV_VALUE)
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#define SPC5_HAS_LINFLEX3 FALSE
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/* SIUL attributes.*/
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#define SPC5_HAS_SIUL TRUE
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@ -88,213 +109,8 @@
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#define SPC5_SIUL_NUM_PCRS 123
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#define SPC5_SIUL_NUM_PADSELS 32
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#define SPC5_SIUL_SYSTEM_PINS 32,33,121,122
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/* eMIOS attributes.*/
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#define SPC5_HAS_EMIOS0 TRUE
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#define SPC5_EMIOS0_PCTL 72
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#define SPC5_EMIOS0_GFR_F0F1_HANDLER vector141
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#define SPC5_EMIOS0_GFR_F2F3_HANDLER vector142
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#define SPC5_EMIOS0_GFR_F4F5_HANDLER vector143
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#define SPC5_EMIOS0_GFR_F6F7_HANDLER vector144
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#define SPC5_EMIOS0_GFR_F8F9_HANDLER vector145
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#define SPC5_EMIOS0_GFR_F10F11_HANDLER vector146
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#define SPC5_EMIOS0_GFR_F12F13_HANDLER vector147
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#define SPC5_EMIOS0_GFR_F14F15_HANDLER vector148
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#define SPC5_EMIOS0_GFR_F16F17_HANDLER vector149
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#define SPC5_EMIOS0_GFR_F18F19_HANDLER vector150
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#define SPC5_EMIOS0_GFR_F20F21_HANDLER vector151
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#define SPC5_EMIOS0_GFR_F22F23_HANDLER vector152
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#define SPC5_EMIOS0_GFR_F24F25_HANDLER vector153
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#define SPC5_EMIOS0_GFR_F26F27_HANDLER vector154
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#define SPC5_EMIOS0_GFR_F0F1_NUMBER 141
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#define SPC5_EMIOS0_GFR_F2F3_NUMBER 142
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#define SPC5_EMIOS0_GFR_F4F5_NUMBER 143
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#define SPC5_EMIOS0_GFR_F6F7_NUMBER 144
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#define SPC5_EMIOS0_GFR_F8F9_NUMBER 145
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#define SPC5_EMIOS0_GFR_F10F11_NUMBER 146
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#define SPC5_EMIOS0_GFR_F12F13_NUMBER 147
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#define SPC5_EMIOS0_GFR_F14F15_NUMBER 148
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#define SPC5_EMIOS0_GFR_F16F17_NUMBER 149
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#define SPC5_EMIOS0_GFR_F18F19_NUMBER 150
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#define SPC5_EMIOS0_GFR_F20F21_NUMBER 151
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#define SPC5_EMIOS0_GFR_F22F23_NUMBER 152
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#define SPC5_EMIOS0_GFR_F24F25_NUMBER 153
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#define SPC5_EMIOS0_GFR_F26F27_NUMBER 154
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#define SPC5_EMIOS0_CLK (halSPCGetSystemClock() / \
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SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
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SPC5_EMIOS0_GLOBAL_PRESCALER)
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#define SPC5_HAS_EMIOS1 TRUE
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#define SPC5_EMIOS1_PCTL 73
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#define SPC5_EMIOS1_GFR_F0F1_HANDLER vector157
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#define SPC5_EMIOS1_GFR_F2F3_HANDLER vector158
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#define SPC5_EMIOS1_GFR_F4F5_HANDLER vector159
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#define SPC5_EMIOS1_GFR_F6F7_HANDLER vector160
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#define SPC5_EMIOS1_GFR_F8F9_HANDLER vector161
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#define SPC5_EMIOS1_GFR_F10F11_HANDLER vector162
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#define SPC5_EMIOS1_GFR_F12F13_HANDLER vector163
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#define SPC5_EMIOS1_GFR_F14F15_HANDLER vector164
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#define SPC5_EMIOS1_GFR_F16F17_HANDLER vector165
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#define SPC5_EMIOS1_GFR_F18F19_HANDLER vector166
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#define SPC5_EMIOS1_GFR_F20F21_HANDLER vector167
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#define SPC5_EMIOS1_GFR_F22F23_HANDLER vector168
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#define SPC5_EMIOS1_GFR_F24F25_HANDLER vector169
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#define SPC5_EMIOS1_GFR_F26F27_HANDLER vector170
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#define SPC5_EMIOS1_GFR_F0F1_NUMBER 157
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#define SPC5_EMIOS1_GFR_F2F3_NUMBER 158
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#define SPC5_EMIOS1_GFR_F4F5_NUMBER 159
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#define SPC5_EMIOS1_GFR_F6F7_NUMBER 160
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#define SPC5_EMIOS1_GFR_F8F9_NUMBER 161
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#define SPC5_EMIOS1_GFR_F10F11_NUMBER 162
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#define SPC5_EMIOS1_GFR_F12F13_NUMBER 163
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#define SPC5_EMIOS1_GFR_F14F15_NUMBER 164
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#define SPC5_EMIOS1_GFR_F16F17_NUMBER 165
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#define SPC5_EMIOS1_GFR_F18F19_NUMBER 166
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#define SPC5_EMIOS1_GFR_F20F21_NUMBER 167
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#define SPC5_EMIOS1_GFR_F22F23_NUMBER 168
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#define SPC5_EMIOS1_GFR_F24F25_NUMBER 169
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#define SPC5_EMIOS1_GFR_F26F27_NUMBER 170
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#define SPC5_EMIOS1_CLK (halSPCGetSystemClock() / \
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SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
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SPC5_EMIOS1_GLOBAL_PRESCALER)
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/* FlexCAN attributes.*/
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#define SPC5_HAS_FLEXCAN0 TRUE
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#define SPC5_FLEXCAN0_PCTL 16
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#define SPC5_FLEXCAN0_MB 64
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#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
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#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER vector73
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72
|
||||
#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER 73
|
||||
#define SPC5_FLEXCAN0_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL);
|
||||
#define SPC5_FLEXCAN0_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL);
|
||||
|
||||
#define SPC5_HAS_FLEXCAN1 TRUE
|
||||
#define SPC5_FLEXCAN1_PCTL 17
|
||||
#define SPC5_FLEXCAN1_MB 64
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector85
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector86
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER vector88
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER vector89
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER vector90
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER vector91
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER vector92
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER vector93
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER 85
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER 86
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER 88
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER 89
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER 90
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER 91
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER 92
|
||||
#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_NUMBER 93
|
||||
#define SPC5_FLEXCAN1_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_START_PCTL);
|
||||
#define SPC5_FLEXCAN1_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_STOP_PCTL);
|
||||
|
||||
#define SPC5_HAS_FLEXCAN2 TRUE
|
||||
#define SPC5_FLEXCAN2_PCTL 18
|
||||
#define SPC5_FLEXCAN2_MB 64
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER vector105
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER vector106
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER vector108
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER vector109
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER vector110
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER vector111
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER vector112
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER vector113
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER 105
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER 106
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER 108
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER 109
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER 110
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER 111
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER 112
|
||||
#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_NUMBER 113
|
||||
#define SPC5_FLEXCAN2_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
|
||||
#define SPC5_FLEXCAN2_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
|
||||
|
||||
#define SPC5_HAS_FLEXCAN3 TRUE
|
||||
#define SPC5_FLEXCAN3_PCTL 19
|
||||
#define SPC5_FLEXCAN3_MB 64
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER vector173
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER vector174
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER vector176
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_HANDLER vector177
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_HANDLER vector178
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_HANDLER vector179
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER vector180
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER vector181
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER 173
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER 174
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_NUMBER 176
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_NUMBER 177
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_NUMBER 178
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER 179
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER 180
|
||||
#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_NUMBER 181
|
||||
#define SPC5_FLEXCAN3_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_START_PCTL);
|
||||
#define SPC5_FLEXCAN3_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_STOP_PCTL);
|
||||
|
||||
#define SPC5_HAS_FLEXCAN4 TRUE
|
||||
#define SPC5_FLEXCAN4_PCTL 20
|
||||
#define SPC5_FLEXCAN4_MB 64
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER vector190
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER vector191
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER vector193
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_HANDLER vector194
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_HANDLER vector195
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_HANDLER vector196
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER vector197
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER vector198
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER 190
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER 191
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_NUMBER 193
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_NUMBER 194
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_NUMBER 195
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER 196
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER 197
|
||||
#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_NUMBER 198
|
||||
#define SPC5_FLEXCAN4_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_START_PCTL);
|
||||
#define SPC5_FLEXCAN4_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_STOP_PCTL);
|
||||
|
||||
#define SPC5_HAS_FLEXCAN5 TRUE
|
||||
#define SPC5_FLEXCAN5_PCTL 21
|
||||
#define SPC5_FLEXCAN5_MB 64
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER vector202
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER vector203
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER vector205
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_HANDLER vector206
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_HANDLER vector207
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_HANDLER vector208
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER vector209
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER vector210
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER 202
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER 203
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_NUMBER 205
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_NUMBER 206
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_NUMBER 207
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER 208
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER 209
|
||||
#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_NUMBER 210
|
||||
#define SPC5_FLEXCAN5_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_START_PCTL);
|
||||
#define SPC5_FLEXCAN5_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_STOP_PCTL);
|
||||
/** @} */
|
||||
|
||||
#endif /* _SPC560BC_REGISTRY_H_ */
|
||||
#endif /* _SPC560D_REGISTRY_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @file SPC560BCxx/typedefs.h
|
||||
* @file SPC560Dxx/typedefs.h
|
||||
* @brief Dummy typedefs file.
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -186,7 +186,11 @@
|
|||
/* SIUL attributes.*/
|
||||
#define SPC5_HAS_SIUL TRUE
|
||||
#define SPC5_SIUL_NUM_PORTS 8
|
||||
#if defined(_SPC560PXX_SMALL_)
|
||||
#define SPC5_SIUL_NUM_PCRS 72
|
||||
#else
|
||||
#define SPC5_SIUL_NUM_PCRS 108
|
||||
#endif
|
||||
#define SPC5_SIUL_NUM_PADSELS 36
|
||||
|
||||
/* FlexPWM attributes.*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue