Added check to verify that the matrix H64H32 clock ratio is compatible with master clock frequency.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10451 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
isiora 2017-08-18 21:06:02 +00:00
parent 3f4b4d7fb7
commit e50bc32840
1 changed files with 15 additions and 12 deletions

View File

@ -406,18 +406,6 @@
#error "PLLADIV2 must be always enabled when Main Clock Divider is 3"
#endif
/**
* @brief Matrix H64H32 clock ratio.
*/
#if ((SAMA_H64MX_H32MX_RATIO == 2) || defined(__DOXYGEN__))
#define SAMA_H64MX_H32MX_DIV PMC_MCKR_H32MXDIV_H32MXDIV2
#elif (SAMA_H64MX_H32MX_RATIO == 1)
#define SAMA_H64MX_H32MX_DIV PMC_MCKR_H32MXDIV_H32MXDIV1
#else
#error "H64MX H32MX clock ratio out of range."
#endif
/**
* @brief Processor Clock frequency.
*/
@ -451,6 +439,21 @@
#if (SAMA_MCK > SAMA_MCK_MAX) || (SAMA_MCK < SAMA_MCK_MIN)
#error "Master clock frequency out of range."
#endif
/**
* @brief Matrix H64H32 clock ratio.
*/
#if ((SAMA_H64MX_H32MX_RATIO == 2) || defined(__DOXYGEN__))
#define SAMA_H64MX_H32MX_DIV PMC_MCKR_H32MXDIV_H32MXDIV2
#elif (SAMA_H64MX_H32MX_RATIO == 1)
#define SAMA_H64MX_H32MX_DIV PMC_MCKR_H32MXDIV_H32MXDIV1
#if (SAMA_MCK > 83000000)
#error "Invalid H32MXCLK. MCK > 83MHz wants SAMA_H64MX_H32MX_RATIO == 2"
#endif
#else
#error "H64MX H32MX clock ratio out of range."
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/