diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_bd.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_bd.inc
index b48e4c968..f328607de 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_bd.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_bd.inc
@@ -45,7 +45,7 @@
 /**
  * @brief   Initializes the backup domain.
  */
-static inline void bd_init(void) {
+__STATIC_INLINE void bd_init(void) {
   uint32_t bdcr;
 
   /* Current settings.*/
@@ -71,7 +71,7 @@ static inline void bd_init(void) {
  * @note    WARNING! Changing RTC clock source impossible without reset
  *          of the whole BKP domain.
  */
-static inline void bd_reset(void) {
+__STATIC_INLINE void bd_reset(void) {
 
   /* Reset BKP domain if different clock source selected.*/
   if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_hse.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_hse.inc
index 301151fa1..6027732dc 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_hse.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_hse.inc
@@ -89,18 +89,28 @@
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
+__STATIC_INLINE void hse_enable(void) {
 
-static inline void hse_init(void) {
+#if defined(STM32_HSE_BYPASS)
+  /* HSE Bypass case.*/
+  RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#else
+  RCC->CR |= RCC_CR_HSEON;
+#endif
+  while ((RCC->CR & RCC_CR_HSERDY) == 0U) {
+    /* Waiting for HSE activation.*/
+  }
+}
+
+__STATIC_INLINE void hse_disable(void) {
+
+  RCC->CR &= ~RCC_CR_HSEON;
+}
+
+__STATIC_INLINE void hse_init(void) {
 
 #if STM32_HSE_ENABLED
-#if defined(STM32_HSE_BYPASS)
-  /* HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
-#endif
-  /* HSE activation.*/
-  RCC->CR |= RCC_CR_HSEON;
-  while ((RCC->CR & RCC_CR_HSERDY) == 0U) {
-  }
+  hse_enable();
 #endif
 }
 
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_hse32.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_hse32.inc
index 686f32905..bfec46e1a 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_hse32.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_hse32.inc
@@ -85,7 +85,7 @@
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
-static inline void hse32_init(void) {
+__STATIC_INLINE void hse32_init(void) {
 
 #if STM32_HSE32_ENABLED
 
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi16.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi16.inc
index 9f1bec281..872034d81 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi16.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi16.inc
@@ -57,13 +57,24 @@
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
-static inline void hsi16_init(void) {
+__STATIC_INLINE void hsi16_enable(void) {
+
+  RCC->CR |= RCC_CR_HSION;
+  while ((RCC->CR & RCC_CR_HSIRDY) == 0U) {
+    /* Waiting for HSI16 activation.*/
+  }
+}
+
+__STATIC_INLINE void hsi16_disable(void) {
+
+  RCC->CR &= ~RCC_CR_HSION;
+}
+
+__STATIC_INLINE void hsi16_init(void) {
 
 #if STM32_HSI16_ENABLED
   /* HSI activation.*/
-  RCC->CR |= RCC_CR_HSION;
-  while ((RCC->CR & RCC_CR_HSIRDY) == 0U) {
-  }
+  hsi16_enable();
 #endif
 }
 
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi48.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi48.inc
index ec4dbb2dc..a1e5fabf3 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi48.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi48.inc
@@ -61,7 +61,7 @@
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
-static inline void hsi48_init(void) {
+__STATIC_INLINE void hsi48_init(void) {
 
 #if STM32_HSI48_ENABLED
   /* HSI activation.*/
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_lse.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_lse.inc
index 48ba08e6d..ee30dd87b 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_lse.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_lse.inc
@@ -87,7 +87,7 @@
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
-static inline void lse_init(void) {
+__STATIC_INLINE void lse_init(void) {
 
 #if STM32_LSE_ENABLED
   /* LSE activation.*/
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc
index 4741ac6ce..0352f8f84 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc
@@ -92,7 +92,7 @@
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
-static inline void lsi_init(void) {
+__STATIC_INLINE void lsi_init(void) {
 
 #if STM32_LSI_ENABLED
   /* LSI activation.*/
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc
index 572290dd8..c96f043d4 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc
@@ -165,7 +165,7 @@
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
-static inline void msi_reset(void) {
+__STATIC_INLINE void msi_reset(void) {
 
   /* Resetting to the MSI clock in case we come here after an initialization,
      because a debugger for example.*/
@@ -181,7 +181,7 @@ static inline void msi_reset(void) {
   }
 }
 
-static inline void msi_init(void) {
+__STATIC_INLINE void msi_init(void) {
   uint32_t cr, csr;
 
   /* Initial clocks setup and wait for MSI stabilization, the MSI clock is
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc
index 5494f7bfa..e2448f45e 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc
@@ -319,7 +319,14 @@
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
-static inline void pll_init(void) {
+__STATIC_INLINE void pll_wait_lock(void) {
+
+  while ((RCC->CR & RCC_CR_PLLRDY) == 0U) {
+    /* Waiting for PLL lock.*/
+  }
+}
+
+__STATIC_INLINE void pll_init(void) {
 
 #if STM32_ACTIVATE_PLL
   /* PLL activation.*/
@@ -330,13 +337,11 @@ static inline void pll_init(void) {
                  STM32_PLLM    | STM32_PLLSRC;
   RCC->CR |= RCC_CR_PLLON;
 
-  /* Waiting for PLL lock.*/
-  while ((RCC->CR & RCC_CR_PLLRDY) == 0U)
-    ;
+  pll_wait_lock();
 #endif
 }
 
-static inline void pll_deinit(void) {
+__STATIC_INLINE void pll_deinit(void) {
 
 #if STM32_ACTIVATE_PLL
   /* PLL de-activation.*/
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll_v2.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll_v2.inc
index 32e942ea7..9ef86591e 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll_v2.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll_v2.inc
@@ -321,7 +321,7 @@
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
-static inline void pll_init(void) {
+__STATIC_INLINE void pll_init(void) {
 
 #if STM32_ACTIVATE_PLL
   /* PLLM and PLLSRC are common to all PLLs.*/
@@ -340,7 +340,7 @@ static inline void pll_init(void) {
 #endif
 }
 
-static inline void pll_deinit(void) {
+__STATIC_INLINE void pll_deinit(void) {
 
   /* PLL de-activation.*/
   RCC->PLLCFGR &= ~RCC_CR_PLLON;
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1.inc
index 31d4ef202..dcc8de480 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1.inc
@@ -323,7 +323,7 @@
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
-static inline void pllsai1_init(void) {
+__STATIC_INLINE void pllsai1_init(void) {
 
 #if STM32_ACTIVATE_PLLSAI1
   /* PLLSAI1 activation.*/
@@ -340,7 +340,7 @@ static inline void pllsai1_init(void) {
 #endif
 }
 
-static inline void pllsai1_deinit(void) {
+__STATIC_INLINE void pllsai1_deinit(void) {
 
 #if STM32_ACTIVATE_PLLSAI1
   /* PLLSAI1 de-activation.*/
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai2.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai2.inc
index b1e102d1d..5e02e75dc 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai2.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai2.inc
@@ -323,7 +323,7 @@
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
-static inline void pllsai2_init(void) {
+__STATIC_INLINE void pllsai2_init(void) {
 
 #if STM32_ACTIVATE_PLLSAI2
   /* PLLSAI2 activation.*/
@@ -340,7 +340,7 @@ static inline void pllsai2_init(void) {
 #endif
 }
 
-static inline void pllsai2_deinit(void) {
+__STATIC_INLINE void pllsai2_deinit(void) {
 
 #if STM32_ACTIVATE_PLLSAI2
   /* PLLSAI2 de-activation.*/
diff --git a/os/hal/ports/STM32/STM32G4xx/hal_lld.c b/os/hal/ports/STM32/STM32G4xx/hal_lld.c
index bfa583317..da2bbc760 100644
--- a/os/hal/ports/STM32/STM32G4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32G4xx/hal_lld.c
@@ -216,7 +216,7 @@ __STATIC_INLINE void bd_init(void) {
  *
  * @notapi
  */
-bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
+static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
   static const uint32_t hprediv[16] = {1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U,
                                        2U, 4U, 8U, 16U, 64U, 128U, 256U, 512U};
   static const uint32_t pprediv[16] = {1U, 1U, 1U, 1U, 2U, 4U, 8U, 16U};
@@ -443,10 +443,7 @@ bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) {
   }
 
   /* Making sure HSI16 is activated.*/
-  RCC->CR |= RCC_CR_HSION;
-  while ((RCC->CR & RCC_CR_HSIRDY) == 0U) {
-    /* Waiting for HSI16 activation.*/
-  }
+  hsi16_enable();
 
   /* Disabling boost mode.*/
   PWR->CR5 = PWR_CR5_R1MODE;
@@ -460,15 +457,9 @@ bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) {
   /* Resetting flash ACR settings to the default value.*/
   FLASH->ACR = 0x00040601U;
 
-  /* HSE setup.*/
-  if ((ccp->rcc_cr & RCC_CR_HSEON) == 0U) {
-    RCC->CR &= ~RCC_CR_HSEON;
-  }
-  else {
-    RCC->CR |= RCC_CR_HSEON;
-    while ((RCC->CR & RCC_CR_HSERDY) == 0U) {
-      /* Waiting for HSE activation.*/
-    }
+  /* HSE setup, if required, before starting the PLL.*/
+  if ((ccp->rcc_cr & RCC_CR_HSEON) != 0U) {
+    hse_enable();
   }
 
   /* PLL setup.*/
@@ -479,9 +470,7 @@ bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) {
 
   /* PLL activation polling if required.*/
   if ((ccp->rcc_cr & RCC_CR_PLLON) != 0U) {
-    while ((RCC->CR & RCC_CR_PLLRDY) == 0U) {
-      /* Waiting for PLL lock.*/
-    }
+    pll_wait_lock();
   }
 
   /* MCO and bus dividers first.*/