diff --git a/os/hal/ports/STM32/STM32G0xx/hal_lld.h b/os/hal/ports/STM32/STM32G0xx/hal_lld.h index 09e196400..fdca7ab25 100644 --- a/os/hal/ports/STM32/STM32G0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32G0xx/hal_lld.h @@ -210,7 +210,7 @@ #define STM32_USART2SEL_LSE (3U << 2U) /**< USART2 source is LSE. */ #define STM32_CECSEL_MASK (1U << 6U) /**< CEC mask. */ -#define STM32_CECSEL_HSI16 (0U << 6U) /**< CEC source is HSI16. */ +#define STM32_CECSEL_HSI16DIV (0U << 6U) /**< CEC source is HSI16/448. */ #define STM32_CECSEL_LSE (1U << 6U) /**< CEC source is LSE. */ #define STM32_LPUART1SEL_MASK (3U << 10U) /**< LPUART1 mask. */ @@ -225,8 +225,8 @@ #define STM32_I2C1SEL_HSI16 (2U << 12U) /**< I2C1 source is HSI16. */ #define STM32_I2S1SEL_MASK (3U << 14U) /**< I2S1SEL mask. */ -#define STM32_I2S1SEL_PCLK (0U << 14U) /**< I2S1 source is PCLK. */ -#define STM32_I2S1SEL_SYSCLK (1U << 14U) /**< I2S1 source is SYSCLK. */ +#define STM32_I2S1SEL_SYSCLK (0U << 14U) /**< I2S1 source is SYSCLK. */ +#define STM32_I2S1SEL_PLLPCLK (1U << 14U) /**< I2S1 source is PLLPCLK. */ #define STM32_I2S1SEL_HSI16 (2U << 14U) /**< I2S1 source is HSI16. */ #define STM32_I2S1SEL_CKIN (3U << 14U) /**< I2S1 source is CKIN. */ @@ -319,6 +319,14 @@ STM32_PVDE_DISABLED) #endif +/** + * @brief HSI16 divider value. + * @note The allowed values are 1, 2, 4, 8, 16, 32, 64, 128. + */ +#if !defined(STM32_HSIDIV_VALUE) || defined(__DOXYGEN__) +#define STM32_HSIDIV_VALUE 1 +#endif + /** * @brief Enables or disables the HSI16 clock source. */ @@ -390,24 +398,24 @@ #endif /** - * @brief PLLP divider value or zero if disabled. - * @note The allowed values are 0, 2..32. + * @brief PLLP divider value. + * @note The allowed values are 2..32. */ #if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) #define STM32_PLLP_VALUE 4 #endif /** - * @brief PLLQ divider value or zero if disabled. - * @note The allowed values are 0, 2..8. + * @brief PLLQ divider value. + * @note The allowed values are 2..8. */ #if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) #define STM32_PLLQ_VALUE 4 #endif /** - * @brief PLLR divider value or zero if disabled. - * @note The allowed values are 0, 2..8. + * @brief PLLR divider value. + * @note The allowed values are 2..8. * @note The default value is calculated for a 64MHz system clock from * the internal 16MHz HSI clock. */ @@ -477,7 +485,7 @@ * @brief CEC clock source. */ #if !defined(STM32_CECSEL) || defined(__DOXYGEN__) -#define STM32_CECSEL STM32_CECSEL_HSI16 +#define STM32_CECSEL STM32_CECSEL_HSI16DIV #endif /** @@ -523,11 +531,32 @@ #endif /** - * @brief ADCSEL value (ADCs clock source). + * @brief RNG clock source. + */ +#if !defined(STM32_RNGSEL) || defined(__DOXYGEN__) +#define STM32_RNGSEL STM32_RNGSEL_HSI16 +#endif + +/** + * @brief RNG divider value. + */ +#if !defined(STM32_RNGDIV_VALUE) || defined(__DOXYGEN__) +#define STM32_RNGDIV_VALUE 1 +#endif + +/** + * @brief ADC clock source. */ #if !defined(STM32_ADCSEL) || defined(__DOXYGEN__) #define STM32_ADCSEL STM32_ADCSEL_PLLPCLK #endif + +/** + * @brief RTC clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK +#endif /** @} */ /*===========================================================================*/ @@ -574,14 +603,9 @@ * @{ */ /** - * @brief Maximum SYSCLK clock frequency in boost mode. + * @brief Maximum SYSCLK clock frequency. */ -#define STM32_SYSCLK_MAX 120000000 - -/** - * @brief Maximum SYSCLK clock frequency in normal mode. - */ -#define STM32_SYSCLK_NOBOOST_MAX 80000000 +#define STM32_SYSCLK_MAX 64000000 /** * @brief Maximum HSE clock frequency at current voltage setting. @@ -596,7 +620,7 @@ /** * @brief Minimum HSE clock frequency. */ -#define STM32_HSECLK_MIN 8000000 +#define STM32_HSECLK_MIN 4000000 /** * @brief Minimum HSE clock frequency using an external source. @@ -641,72 +665,66 @@ /** * @brief Minimum VCO clock frequency at current voltage setting. */ -#define STM32_PLLVCO_MIN 64000000 +#define STM32_PLLVCO_MIN 96000000 /** * @brief Maximum PLL-P output clock frequency. */ -#define STM32_PLLP_MAX 120000000 +#define STM32_PLLP_MAX 122000000 /** * @brief Minimum PLL-P output clock frequency. */ -#define STM32_PLLP_MIN 2064500 +#define STM32_PLLP_MIN 3090000 /** * @brief Maximum PLL-Q output clock frequency. */ -#define STM32_PLLQ_MAX 120000000 +#define STM32_PLLQ_MAX 128000000 /** * @brief Minimum PLL-Q output clock frequency. */ -#define STM32_PLLQ_MIN 8000000 +#define STM32_PLLQ_MIN 12000000 /** * @brief Maximum PLL-R output clock frequency. */ -#define STM32_PLLR_MAX 120000000 +#define STM32_PLLR_MAX 64000000 /** * @brief Minimum PLL-R output clock frequency. */ -#define STM32_PLLR_MIN 8000000 +#define STM32_PLLR_MIN 12000000 /** - * @brief Maximum APB1 clock frequency. + * @brief Maximum APB clock frequency. */ -#define STM32_PCLK1_MAX 120000000 - -/** - * @brief Maximum APB2 clock frequency. - */ -#define STM32_PCLK2_MAX 120000000 +#define STM32_PCLK_MAX 64000000 /** * @brief Maximum ADC clock frequency. */ -#define STM32_ADCCLK_MAX 80000000 +#define STM32_ADCCLK_MAX 350000000 /** @} */ /** * @name Flash Wait states * @{ */ -#define STM32_0WS_THRESHOLD 20000000 -#define STM32_1WS_THRESHOLD 40000000 -#define STM32_2WS_THRESHOLD 60000000 -#define STM32_3WS_THRESHOLD 80000000 -#define STM32_4WS_THRESHOLD 100000000 -#define STM32_5WS_THRESHOLD 120000000 +#define STM32_0WS_THRESHOLD 24000000 +#define STM32_1WS_THRESHOLD 48000000 +#define STM32_2WS_THRESHOLD 64000000 +#define STM32_3WS_THRESHOLD 0 +#define STM32_4WS_THRESHOLD 0 +#define STM32_5WS_THRESHOLD 0 /** @} */ #elif STM32_VOS == STM32_VOS_RANGE2 -#define STM32_SYSCLK_MAX 26000000 -#define STM32_SYSCLK_NOBOOST_MAX 26000000 +#define STM32_SYSCLK_MAX 16000000 #define STM32_HSECLK_MAX 26000000 #define STM32_HSECLK_BYP_MAX 26000000 -#define STM32_HSECLK_MIN 8000000 +#define STM32_HSECLK_MIN 4000000 #define STM32_HSECLK_BYP_MIN 8000000 #define STM32_LSECLK_MAX 32768 #define STM32_LSECLK_BYP_MAX 1000000 @@ -715,20 +733,19 @@ #define STM32_PLLIN_MAX 16000000 #define STM32_PLLIN_MIN 2660000 #define STM32_PLLVCO_MAX 128000000 -#define STM32_PLLVCO_MIN 64000000 -#define STM32_PLLP_MAX 26000000 -#define STM32_PLLP_MIN 2064500 -#define STM32_PLLQ_MAX 26000000 -#define STM32_PLLQ_MIN 8000000 -#define STM32_PLLR_MAX 26000000 -#define STM32_PLLR_MIN 8000000 -#define STM32_PCLK1_MAX 26000000 -#define STM32_PCLK2_MAX 26000000 -#define STM32_ADCCLK_MAX 26000000 +#define STM32_PLLVCO_MIN 96000000 +#define STM32_PLLP_MAX 40000000 +#define STM32_PLLP_MIN 3090000 +#define STM32_PLLQ_MAX 33000000 +#define STM32_PLLQ_MIN 12000000 +#define STM32_PLLR_MAX 16000000 +#define STM32_PLLR_MIN 12000000 +#define STM32_PCLK_MAX 16000000 +#define STM32_ADCCLK_MAX 16000000 #define STM32_0WS_THRESHOLD 8000000 #define STM32_1WS_THRESHOLD 16000000 -#define STM32_2WS_THRESHOLD 26000000 +#define STM32_2WS_THRESHOLD 0 #define STM32_3WS_THRESHOLD 0 #define STM32_4WS_THRESHOLD 0 #define STM32_5WS_THRESHOLD 0 @@ -737,52 +754,6 @@ #error "invalid STM32_VOS value specified" #endif -/** - * @brief MSI frequency. - */ -#if STM32_MSIRANGE == STM32_MSIRANGE_100K -#define STM32_MSICLK 100000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_200K -#define STM32_MSICLK 200000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_400K -#define STM32_MSICLK 400000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_800K -#define STM32_MSICLK 800000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_1M -#define STM32_MSICLK 1000000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_2M -#define STM32_MSICLK 2000000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_4M -#define STM32_MSICLK 4000000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_8M -#define STM32_MSICLK 8000000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_16M -#define STM32_MSICLK 16000000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_24M -#define STM32_MSICLK 24000000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_32M -#define STM32_MSICLK 32000000 -#elif STM32_MSIRANGE == STM32_MSIRANGE_48M -#define STM32_MSICLK 48000000 -#else -#error "invalid STM32_MSIRANGE value specified" -#endif - -/** - * @brief MSIS frequency. - */ -#if STM32_MSISRANGE == STM32_MSISRANGE_1M -#define STM32_MSISCLK 1000000 -#elif STM32_MSISRANGE == STM32_MSISRANGE_2M -#define STM32_MSISCLK 2000000 -#elif STM32_MSISRANGE == STM32_MSISRANGE_4M -#define STM32_MSISCLK 4000000 -#elif STM32_MSISRANGE == STM32_MSISRANGE_8M -#define STM32_MSISCLK 8000000 -#else -#error "invalid STM32_MSISRANGE value specified" -#endif - /* * HSI16 related checks. */ @@ -806,72 +777,44 @@ #error "HSI16 not enabled, required by STM32_MCOSEL" #endif -#if ((STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \ - (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2)) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSI16) -#error "HSI16 not enabled, required by STM32_SAI1SEL" -#endif - -#if ((STM32_SAI2SEL == STM32_SAI1SEL_PLLSAI1) || \ - (STM32_SAI2SEL == STM32_SAI1SEL_PLLSAI2)) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSI16) -#error "HSI16 not enabled, required by STM32_SAI2SEL" -#endif - #if (STM32_USART1SEL == STM32_USART1SEL_HSI16) #error "HSI16 not enabled, required by STM32_USART1SEL" #endif #if (STM32_USART2SEL == STM32_USART2SEL_HSI16) #error "HSI16 not enabled, required by STM32_USART2SEL" #endif -#if (STM32_USART3SEL == STM32_USART3SEL_HSI16) -#error "HSI16 not enabled, required by STM32_USART3SEL" -#endif -#if (STM32_UART4SEL == STM32_UART4SEL_HSI16) -#error "HSI16 not enabled, required by STM32_UART4SEL" -#endif -#if (STM32_UART5SEL == STM32_UART5SEL_HSI16) -#error "HSI16 not enabled, required by STM32_UART5SEL" -#endif #if (STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16) #error "HSI16 not enabled, required by STM32_LPUART1SEL" #endif +#if (STM32_CECSEL == STM32_CECSEL_HSI16DIV) +#error "HSI16 not enabled, required by STM32_CECSEL" +#endif + #if (STM32_I2C1SEL == STM32_I2C1SEL_HSI16) -#error "HSI16 not enabled, required by I2C1SEL" +#error "HSI16 not enabled, required by STM32_I2C1SEL" #endif -#if (STM32_I2C2SEL == STM32_I2C2SEL_HSI16) -#error "HSI16 not enabled, required by I2C2SEL" -#endif -#if (STM32_I2C3SEL == STM32_I2C3SEL_HSI16) -#error "HSI16 not enabled, required by I2C3SEL" +#if (STM32_I2S1SEL == STM32_I2S1SEL_HSI16) +#error "HSI16 not enabled, required by STM32_I2S1SEL" #endif #if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16) -#error "HSI16 not enabled, required by LPTIM1SEL" +#error "HSI16 not enabled, required by STM32_LPTIM1SEL" #endif #if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16) -#error "HSI16 not enabled, required by LPTIM2SEL" +#error "HSI16 not enabled, required by STM32_LPTIM2SEL" #endif -#if (STM32_STOPWUCK == STM32_STOPWUCK_HSI16) -#error "HSI16 not enabled, required by STM32_STOPWUCK" +#if (STM32_RNGSEL == STM32_RNGSEL_HSI16) +#error "HSI16 not enabled, required by STM32_RNGSEL" +#endif + +#if (STM32_ADCSEL == STM32_ADCSEL_HSI16) +#error "HSI16 not enabled, required by STM32_ADCSEL" #endif #endif /* !STM32_HSI16_ENABLED */ -#if STM32_HSI48_ENABLED -#else /* !STM32_HSI48_ENABLED */ - -#if STM32_MCOSEL == STM32_MCOSEL_HSI48 -#error "HSI48 not enabled, required by STM32_MCOSEL" -#endif - -#if STM32_CLK48SEL == STM32_CLK48SEL_HSI48 -#error "HSI48 not enabled, required by STM32_CLK48SEL" -#endif -#endif /* !STM32_HSI48_ENABLED */ - /* * HSE related checks. */ @@ -907,18 +850,6 @@ #error "HSE not enabled, required by STM32_MCOSEL" #endif - #if ((STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) | \ - (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2)) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSE) - #error "HSE not enabled, required by STM32_SAI1SEL" - #endif - - #if ((STM32_SAI2SEL == STM32_SAI1SEL_PLLSAI1) | \ - (STM32_SAI2SEL == STM32_SAI1SEL_PLLSAI2)) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSE) - #error "HSE not enabled, required by STM32_SAI2SEL" - #endif - #if STM32_RTCSEL == STM32_RTCSEL_HSEDIV #error "HSE not enabled, required by STM32_RTCSEL" #endif @@ -972,23 +903,35 @@ #error "LSE not enabled, required by STM32_LSCOSEL" #endif - #if STM32_MSIPLL_ENABLED == TRUE - #error "LSE not enabled, required by STM32_MSIPLL_ENABLED" - #endif - #endif /* !STM32_LSE_ENABLED */ -/* - * MSI related checks. +/** + * @brief STM32_HSIDIV field. */ -#if (STM32_MSIRANGE == STM32_MSIRANGE_48M) && !STM32_MSIPLL_ENABLED -#warning "STM32_MSIRANGE_48M should be used with STM32_MSIPLL_ENABLED" +#if (STM32_HSIDIV_VALUE == 1) || defined(__DOXYGEN__) +#define STM32_HSIDIV (0U << 11U) +#elif STM32_HSIDIV_VALUE == 2 +#define STM32_HSIDIV (1U << 11U) +#elif STM32_HSIDIV_VALUE == 4 +#define STM32_HSIDIV (2U << 11U) +#elif STM32_HSIDIV_VALUE == 8 +#define STM32_HSIDIV (3U << 11U) +#elif STM32_HSIDIV_VALUE == 16 +#define STM32_HSIDIV (4U << 11U) +#elif STM32_HSIDIV_VALUE == 32 +#define STM32_HSIDIV (5U << 11U) +#elif STM32_HSIDIV_VALUE == 64 +#define STM32_HSIDIV (6U << 11U) +#elif STM32_HSIDIV_VALUE == 128 +#define STM32_HSIDIV (7U << 11U) +#else +#error "invalid STM32_HSIDIV_VALUE value specified" #endif /** * @brief STM32_PLLM field. */ -#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 16)) || \ +#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 8)) || \ defined(__DOXYGEN__) #define STM32_PLLM ((STM32_PLLM_VALUE - 1) << 4) #else @@ -1001,9 +944,6 @@ #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) #define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE) -#elif STM32_PLLSRC == STM32_PLLSRC_MSI -#define STM32_PLLCLKIN (STM32_MSICLK / STM32_PLLM_VALUE) - #elif STM32_PLLSRC == STM32_PLLSRC_HSI16 #define STM32_PLLCLKIN (STM32_HSI16CLK / STM32_PLLM_VALUE) @@ -1025,11 +965,13 @@ /* * PLL enable check. */ -#if (STM32_HSI48_ENABLED && (STM32_CLK48SEL == STM32_CLK48SEL_PLL)) || \ - (STM32_SW == STM32_SW_PLL) || \ +#if (STM32_SW == STM32_SW_PLL) || \ (STM32_MCOSEL == STM32_MCOSEL_PLL) || \ - (STM32_SAI1SEL == STM32_SAI1SEL_PLL) || \ - (STM32_SAI2SEL == STM32_SAI2SEL_PLL) || \ + (STM32_TIM1SEL == STM32_TIM1SEL_PLLQCLK) || \ + (STM32_TIM15SEL == STM32_TIM15SEL_PLLQCLK) || \ + (STM32_RNGSEL == STM32_RNGSEL_PLLQCLK) || \ + (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \ + (STM32_I2S1SEL == STM32_I2S1SEL_PLLPCLK) || \ defined(__DOXYGEN__) #if STM32_PLLCLKIN == 0 @@ -1047,93 +989,41 @@ /** * @brief STM32_PLLN field. */ -#if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 127)) || \ +#if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 86)) || \ defined(__DOXYGEN__) #define STM32_PLLN (STM32_PLLN_VALUE << 8) #else #error "invalid STM32_PLLN_VALUE value specified" #endif -/** - * @brief STM32_PLLP field. - */ -#if (STM32_PLLP_VALUE == 7) || defined(__DOXYGEN__) -#define STM32_PLLP (0 << 17) - -#elif STM32_PLLP_VALUE == 17 -#define STM32_PLLP (1 << 17) - -#else -#error "invalid STM32_PLLP_VALUE value specified" -#endif - -/** - * @brief STM32_PLLQ field. - */ -#if (STM32_PLLQ_VALUE == 2) || defined(__DOXYGEN__) -#define STM32_PLLQ (0 << 21) - -#elif STM32_PLLQ_VALUE == 4 -#define STM32_PLLQ (1 << 21) - -#elif STM32_PLLQ_VALUE == 6 -#define STM32_PLLQ (2 << 21) - -#elif STM32_PLLQ_VALUE == 8 -#define STM32_PLLQ (3 << 21) - -#else -#error "invalid STM32_PLLQ_VALUE value specified" -#endif - /** * @brief STM32_PLLR field. */ -#if (STM32_PLLR_VALUE == 2) || defined(__DOXYGEN__) -#define STM32_PLLR (0 << 25) - -#elif STM32_PLLR_VALUE == 4 -#define STM32_PLLR (1 << 25) - -#elif STM32_PLLR_VALUE == 6 -#define STM32_PLLR (2 << 25) - -#elif STM32_PLLR_VALUE == 8 -#define STM32_PLLR (3 << 25) - +#if ((STM32_PLLR_VALUE >= 2) && (STM32_PLLR_VALUE <= 8)) || \ + defined(__DOXYGEN__) +#define STM32_PLLR ((STM32_PLLR_VALUE - 1) << 29) #else #error "invalid STM32_PLLR_VALUE value specified" #endif /** - * @brief STM32_PLLPDIV field. + * @brief STM32_PLLQ field. */ -#if (STM32_PLLPDIV_VALUE == 0) || \ - ((STM32_PLLPDIV_VALUE != 1) && (STM32_PLLPDIV_VALUE <= 31)) || \ +#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 8)) || \ defined(__DOXYGEN__) -#define STM32_PLLPDIV (STM32_PLLPDIV_VALUE << 27) +#define STM32_PLLQ ((STM32_PLLQ_VALUE - 1) << 25) #else -#error "invalid STM32_PLLPDIV_VALUE value specified" +#error "invalid STM32_PLLQ_VALUE value specified" #endif /** - * @brief STM32_PLLPEN field. + * @brief STM32_PLLP field. */ -#if (STM32_SAI1SEL == STM32_SAI1SEL_PLL) || \ - (STM32_SAI2SEL == STM32_SAI2SEL_PLL) || \ +#if ((STM32_PLLP_VALUE >= 2) && (STM32_PLLP_VALUE <= 32)) || \ defined(__DOXYGEN__) -#define STM32_PLLPEN (1 << 16) +#define STM32_PLLP ((STM32_PLLP_VALUE - 1) << 17) #else -#define STM32_PLLPEN (0 << 16) -#endif - -/** - * @brief STM32_PLLQEN field. - */ -#if (STM32_CLK48SEL == STM32_CLK48SEL_PLL) || defined(__DOXYGEN__) -#define STM32_PLLQEN (1 << 20) -#else -#define STM32_PLLQEN (0 << 20) +#error "invalid STM32_PLLP_VALUE value specified" #endif /** @@ -1142,9 +1032,32 @@ #if (STM32_SW == STM32_SW_PLL) || \ (STM32_MCOSEL == STM32_MCOSEL_PLL) || \ defined(__DOXYGEN__) -#define STM32_PLLREN (1 << 24) +#define STM32_PLLREN (1 << 28) #else -#define STM32_PLLREN (0 << 24) +#define STM32_PLLREN (0 << 28) +#endif + +/** + * @brief STM32_PLLQEN field. + */ +#if (STM32_TIM1SEL == STM32_TIM1SEL_PLLQCLK) || \ + (STM32_TIM15SEL == STM32_TIM15SEL_PLLQCLK) || \ + (STM32_RNGSEL == STM32_RNGSEL_PLLQCLK) || \ + defined(__DOXYGEN__) +#define STM32_PLLQEN (1 << 24) +#else +#define STM32_PLLQEN (0 << 24) +#endif + +/** + * @brief STM32_PLLPEN field. + */ +#if (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \ + (STM32_I2S1SEL == STM32_I2S1SEL_PLLPCLK) || \ + defined(__DOXYGEN__) +#define STM32_PLLPEN (1 << 16) +#else +#define STM32_PLLPEN (0 << 16) #endif /** @@ -1160,6 +1073,16 @@ #error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" #endif +/** + * @brief PLL R output clock frequency. + */ +#define STM32_PLL_R_CLKOUT (STM32_PLLVCO / STM32_PLLR_VALUE) + +/** + * @brief PLL Q output clock frequency. + */ +#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE) + /** * @brief PLL P output clock frequency. */ @@ -1169,22 +1092,12 @@ #define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLPDIV_VALUE) #endif -/** - * @brief PLL Q output clock frequency. - */ -#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE) - -/** - * @brief PLL R output clock frequency. - */ -#define STM32_PLL_R_CLKOUT (STM32_PLLVCO / STM32_PLLR_VALUE) - /* - * PLL-P output frequency range check. + * PLL-R output frequency range check. */ #if STM32_ACTIVATE_PLL && \ - ((STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX)) -#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)" + ((STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX)) +#error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)" #endif /* @@ -1196,31 +1109,39 @@ #endif /* - * PLL-R output frequency range check. + * PLL-P output frequency range check. */ #if STM32_ACTIVATE_PLL && \ - ((STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX)) -#error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)" + ((STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX)) +#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)" #endif +/** + * @brief HSISYS clock frequency. + */ +#define STM32_HSISYSCLK (STM32_HSI16CLK / STM32_HSIDIV_VALUE) + /** * @brief System clock source. */ #if STM32_NO_INIT || defined(__DOXYGEN__) -#define STM32_SYSCLK STM32_MSICLK +#define STM32_SYSCLK STM32_HSISYSCLK -#elif (STM32_SW == STM32_SW_MSI) -#define STM32_SYSCLK STM32_MSICLK - -#elif (STM32_SW == STM32_SW_HSI16) -#define STM32_SYSCLK STM32_HSI16CLK +#elif (STM32_SW == STM32_SW_HSISYS) +#define STM32_SYSCLK STM32_HSISYSCLK #elif (STM32_SW == STM32_SW_HSE) #define STM32_SYSCLK STM32_HSECLK -#elif (STM32_SW == STM32_SW_PLL) +#elif (STM32_SW == STM32_SW_PLLRCLK) #define STM32_SYSCLK STM32_PLL_R_CLKOUT +#elif (STM32_SW == STM32_SW_LSI) +#define STM32_SYSCLK STM32_LSICLK + +#elif (STM32_SW == STM32_SW_LSE) +#define STM32_SYSCLK STM32_LSECLK + #else #error "invalid STM32_SW value specified" #endif @@ -1272,447 +1193,32 @@ #endif /** - * @brief APB1 frequency. + * @brief APB frequency. */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK1 (STM32_HCLK / 1) +#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK (STM32_HCLK / 1) -#elif STM32_PPRE1 == STM32_PPRE1_DIV2 -#define STM32_PCLK1 (STM32_HCLK / 2) +#elif STM32_PPRE == STM32_PPRE_DIV2 +#define STM32_PCLK (STM32_HCLK / 2) -#elif STM32_PPRE1 == STM32_PPRE1_DIV4 -#define STM32_PCLK1 (STM32_HCLK / 4) +#elif STM32_PPRE == STM32_PPRE_DIV4 +#define STM32_PCLK (STM32_HCLK / 4) -#elif STM32_PPRE1 == STM32_PPRE1_DIV8 -#define STM32_PCLK1 (STM32_HCLK / 8) +#elif STM32_PPRE == STM32_PPRE_DIV8 +#define STM32_PCLK (STM32_HCLK / 8) -#elif STM32_PPRE1 == STM32_PPRE1_DIV16 -#define STM32_PCLK1 (STM32_HCLK / 16) +#elif STM32_PPRE == STM32_PPRE_DIV16 +#define STM32_PCLK (STM32_HCLK / 16) #else -#error "invalid STM32_PPRE1 value specified" +#error "invalid STM32_PPRE value specified" #endif /* - * APB1 frequency check. + * APB frequency check. */ -#if STM32_PCLK1 > STM32_PCLK1_MAX -#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" -#endif - -/** - * @brief APB2 frequency. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK2 (STM32_HCLK / 1) - -#elif STM32_PPRE2 == STM32_PPRE2_DIV2 -#define STM32_PCLK2 (STM32_HCLK / 2) - -#elif STM32_PPRE2 == STM32_PPRE2_DIV4 -#define STM32_PCLK2 (STM32_HCLK / 4) - -#elif STM32_PPRE2 == STM32_PPRE2_DIV8 -#define STM32_PCLK2 (STM32_HCLK / 8) - -#elif STM32_PPRE2 == STM32_PPRE2_DIV16 -#define STM32_PCLK2 (STM32_HCLK / 16) - -#else -#error "invalid STM32_PPRE2 value specified" -#endif - -/* - * APB2 frequency check. - */ -#if STM32_PCLK2 > STM32_PCLK2_MAX -#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" -#endif - -/** - * @brief STM32_PLLSAI1M field. - */ -#if ((STM32_PLLSAI1M_VALUE >= 1) && (STM32_PLLSAI1M_VALUE <= 16)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAI1M ((STM32_PLLSAI1M_VALUE - 1) << 4) -#else -#error "invalid STM32_PLLSAI1M_VALUE value specified" -#endif - -/** - * @brief PLLSAI1 input clock frequency. - */ -#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) -#define STM32_PLLSAI1CLKIN (STM32_HSECLK / STM32_PLLSAI1M_VALUE) - -#elif STM32_PLLSRC == STM32_PLLSRC_MSI -#define STM32_PLLSAI1CLKIN (STM32_MSICLK / STM32_PLLSAI1M_VALUE) - -#elif STM32_PLLSRC == STM32_PLLSRC_HSI16 -#define STM32_PLLSAI1CLKIN (STM32_HSI16CLK / STM32_PLLSAI1M_VALUE) - -#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK -#define STM32_PLLSAI1CLKIN 0 - -#else -#error "invalid STM32_PLLSRC value specified" -#endif - -/* - * PLLSAI1 input frequency range check. - */ -#if (STM32_PLLSAI1CLKIN != 0) && \ - ((STM32_PLLSAI1CLKIN < STM32_PLLIN_MIN) || \ - (STM32_PLLSAI1CLKIN > STM32_PLLIN_MAX)) -#error "STM32_PLLSAI1CLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" -#endif - -/* - * PLLSAI1 enable check. - */ -#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \ - (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || \ - (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || \ - (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || \ - defined(__DOXYGEN__) - -#if STM32_PLLSAI1CLKIN == 0 -#error "PLLSAI1 activation required but no PLL clock selected" -#endif - -/** - * @brief PLLSAI1 activation flag. - */ -#define STM32_ACTIVATE_PLLSAI1 TRUE -#else -#define STM32_ACTIVATE_PLLSAI1 FALSE -#endif - -/** - * @brief STM32_PLLSAI1N field. - */ -#if ((STM32_PLLSAI1N_VALUE >= 8) && (STM32_PLLSAI1N_VALUE <= 127)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAI1N (STM32_PLLSAI1N_VALUE << 8) -#else -#error "invalid STM32_PLLSAI1N_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAI1P field. - */ -#if (STM32_PLLSAI1P_VALUE == 7) || defined(__DOXYGEN__) -#define STM32_PLLSAI1P (0 << 17) - -#elif STM32_PLLSAI1P_VALUE == 17 -#define STM32_PLLSAI1P (1 << 17) - -#else -#error "invalid STM32_PLLSAI1P_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAI1Q field. - */ -#if (STM32_PLLSAI1Q_VALUE == 2) || defined(__DOXYGEN__) -#define STM32_PLLSAI1Q (0 << 21) - -#elif STM32_PLLSAI1Q_VALUE == 4 -#define STM32_PLLSAI1Q (1 << 21) - -#elif STM32_PLLSAI1Q_VALUE == 6 -#define STM32_PLLSAI1Q (2 << 21) - -#elif STM32_PLLSAI1Q_VALUE == 8 -#define STM32_PLLSAI1Q (3 << 21) - -#else -#error "invalid STM32_PLLSAI1Q_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAI1R field. - */ -#if (STM32_PLLSAI1R_VALUE == 2) || defined(__DOXYGEN__) -#define STM32_PLLSAI1R (0 << 25) - -#elif STM32_PLLSAI1R_VALUE == 4 -#define STM32_PLLSAI1R (1 << 25) - -#elif STM32_PLLSAI1R_VALUE == 6 -#define STM32_PLLSAI1R (2 << 25) - -#elif STM32_PLLSAI1R_VALUE == 8 -#define STM32_PLLSAI1R (3 << 25) - -#else -#error "invalid STM32_PLLSAI1R_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAI1PDIV field. - */ -#if ((STM32_PLLSAI1PDIV_VALUE != 1) && (STM32_PLLSAI1PDIV_VALUE <= 31)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAI1PDIV (STM32_PLLSAI1PDIV_VALUE << 27) -#else -#error "invalid STM32_PLLSAI1PDIV_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAI1PEN field. - */ -#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \ - (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAI1PEN (1 << 16) -#else -#define STM32_PLLSAI1PEN (0 << 16) -#endif - -/** - * @brief STM32_PLLSAI1QEN field. - */ -#if (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || defined(__DOXYGEN__) -#define STM32_PLLSAI1QEN (1 << 20) -#else -#define STM32_PLLSAI1QEN (0 << 20) -#endif - -/** - * @brief STM32_PLLSAI1REN field. - */ -#if (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || defined(__DOXYGEN__) -#define STM32_PLLSAI1REN (1 << 24) -#else -#define STM32_PLLSAI1REN (0 << 24) -#endif - -/** - * @brief PLLSAI1 VCO frequency. - */ -#define STM32_PLLSAI1VCO (STM32_PLLSAI1CLKIN * STM32_PLLSAI1N_VALUE) - -/* - * PLLSAI1 VCO frequency range check. - */ -#if STM32_ACTIVATE_PLLSAI1 && \ - ((STM32_PLLSAI1VCO < STM32_PLLVCO_MIN) || (STM32_PLLSAI1VCO > STM32_PLLVCO_MAX)) -#error "STM32_PLLSAI1VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" -#endif - -/** - * @brief PLLSAI1-P output clock frequency. - */ -#if (STM32_PLLSAI1PDIV_VALUE == 0) || defined(__DOXYGEN__) -#define STM32_PLLSAI1_P_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1P_VALUE) -#else -#define STM32_PLLSAI1_P_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1PDIV_VALUE) -#endif - -/** - * @brief PLLSAI1-Q output clock frequency. - */ -#define STM32_PLLSAI1_Q_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE) - -/** - * @brief PLLSAI1-R output clock frequency. - */ -#define STM32_PLLSAI1_R_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1R_VALUE) - -/* - * PLLSAI1-P output frequency range check. - */ -#if STM32_ACTIVATE_PLLSAI1 && \ - ((STM32_PLLSAI1_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLLSAI1_P_CLKOUT > STM32_PLLP_MAX)) -#error "STM32_PLLSAI1_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)" -#endif - -/* - * PLLSAI1-Q output frequency range check. - */ -#if STM32_ACTIVATE_PLLSAI1 && \ - ((STM32_PLLSAI1_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLLSAI1_Q_CLKOUT > STM32_PLLQ_MAX)) -#error "STM32_PLLSAI1_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)" -#endif - -/* - * PLLSAI1-R output frequency range check. - */ -#if STM32_ACTIVATE_PLLSAI1 && \ - ((STM32_PLLSAI1_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLLSAI1_R_CLKOUT > STM32_PLLR_MAX)) -#error "STM32_PLLSAI1_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)" -#endif - -/** - * @brief STM32_PLLSAI2M field. - */ -#if ((STM32_PLLSAI2M_VALUE >= 1) && (STM32_PLLSAI2M_VALUE <= 16)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAI2M ((STM32_PLLSAI2M_VALUE - 1) << 4) -#else -#error "invalid STM32_PLLSAI2M_VALUE value specified" -#endif - -/** - * @brief PLLSAI2 input clock frequency. - */ -#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) -#define STM32_PLLSAI2CLKIN (STM32_HSECLK / STM32_PLLSAI2M_VALUE) - -#elif STM32_PLLSRC == STM32_PLLSRC_MSI -#define STM32_PLLSAI2CLKIN (STM32_MSICLK / STM32_PLLSAI2M_VALUE) - -#elif STM32_PLLSRC == STM32_PLLSRC_HSI16 -#define STM32_PLLSAI2CLKIN (STM32_HSI16CLK / STM32_PLLSAI2M_VALUE) - -#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK -#define STM32_PLLSAI2CLKIN 0 - -#else -#error "invalid STM32_PLLSRC value specified" -#endif - -/* - * PLLSAI2 input frequency range check. - */ -#if (STM32_PLLSAI2CLKIN != 0) && \ - ((STM32_PLLSAI2CLKIN < STM32_PLLIN_MIN) || \ - (STM32_PLLSAI2CLKIN > STM32_PLLIN_MAX)) -#error "STM32_PLLSAI2CLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" -#endif - -/* - * PLLSAI2 enable check. - */ -#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2) || \ - (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) || \ - (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || \ - defined(__DOXYGEN__) - -#if STM32_PLLSAI2CLKIN == 0 -#error "PLLSAI2 activation required but no PLL clock selected" -#endif - -/** - * @brief PLLSAI2 activation flag. - */ -#define STM32_ACTIVATE_PLLSAI2 TRUE -#else -#define STM32_ACTIVATE_PLLSAI2 FALSE -#endif - -/** - * @brief STM32_PLLSAI2N field. - */ -#if ((STM32_PLLSAI2N_VALUE >= 8) && (STM32_PLLSAI2N_VALUE <= 127)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAI2N (STM32_PLLSAI2N_VALUE << 8) -#else -#error "invalid STM32_PLLSAI2N_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAI2P field. - */ -#if (STM32_PLLSAI2P_VALUE == 7) || defined(__DOXYGEN__) -#define STM32_PLLSAI2P (0 << 17) - -#elif STM32_PLLSAI2P_VALUE == 17 -#define STM32_PLLSAI2P (1 << 17) - -#else -#error "invalid STM32_PLLSAI2P_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAI2R field. - */ -#if (STM32_PLLSAI2R_VALUE == 2) || defined(__DOXYGEN__) -#define STM32_PLLSAI2R (0 << 25) - -#elif STM32_PLLSAI2R_VALUE == 4 -#define STM32_PLLSAI2R (1 << 25) - -#elif STM32_PLLSAI2R_VALUE == 6 -#define STM32_PLLSAI2R (2 << 25) - -#elif STM32_PLLSAI2R_VALUE == 8 -#define STM32_PLLSAI2R (3 << 25) - -#else -#error "invalid STM32_PLLSAI2R_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAI2PDIV field. - */ -#if ((STM32_PLLSAI2PDIV_VALUE != 1) && (STM32_PLLSAI2PDIV_VALUE <= 31)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAI2PDIV (STM32_PLLSAI2PDIV_VALUE << 27) -#else -#error "invalid STM32_PLLSAI2PDIV_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAI2PEN field. - */ -#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2) || \ - (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAI2PEN (1 << 16) -#else -#define STM32_PLLSAI2PEN (0 << 16) -#endif - -/** - * @brief STM32_PLLSAI2REN field. - * @note Always enabled. - * @todo It should depend on some condition. - */ -#define STM32_PLLSAI2REN (1 << 24) - -/** - * @brief PLLSAI2 VCO frequency. - */ -#define STM32_PLLSAI2VCO (STM32_PLLSAI2CLKIN * STM32_PLLSAI2N_VALUE) - -/* - * PLLSAI2 VCO frequency range check. - */ -#if STM32_ACTIVATE_PLLSAI2 && \ - ((STM32_PLLSAI2VCO < STM32_PLLVCO_MIN) || (STM32_PLLSAI2VCO > STM32_PLLVCO_MAX)) -#error "STM32_PLLSAI2VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" -#endif - -/** - * @brief PLLSAI2-P output clock frequency. - */ -#if (STM32_PLLSAI2PDIV_VALUE == 0) || defined(__DOXYGEN__) -#define STM32_PLLSAI2_P_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2P_VALUE) -#else -#define STM32_PLLSAI2_P_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2PDIV_VALUE) -#endif - -/** - * @brief PLLSAI2-R output clock frequency. - */ -#define STM32_PLLSAI2_R_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2R_VALUE) - -/* - * PLLSAI2-P output frequency range check. - */ -#if STM32_ACTIVATE_PLLSAI2 && \ - ((STM32_PLLSAI2_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLLSAI2_P_CLKOUT > STM32_PLLP_MAX)) -#error "STM32_PLLSAI2_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)" -#endif - -/* - * PLLSAI2-R output frequency range check. - */ -#if STM32_ACTIVATE_PLLSAI2 && \ - ((STM32_PLLSAI2_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLLSAI2_R_CLKOUT > STM32_PLLR_MAX)) -#error "STM32_PLLSAI2_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)" +#if STM32_PCLK > STM32_PCLK_MAX +#error "STM32_PCLK exceeding maximum frequency (STM32_PCLK_MAX)" #endif /** @@ -1724,17 +1230,14 @@ #elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK #define STM32_MCODIVCLK STM32_SYSCLK -#elif STM32_MCOSEL == STM32_MCOSEL_MSI -#define STM32_MCODIVCLK STM32_MSICLK - #elif STM32_MCOSEL == STM32_MCOSEL_HSI16 #define STM32_MCODIVCLK STM32_HSI16CLK #elif STM32_MCOSEL == STM32_MCOSEL_HSE #define STM32_MCODIVCLK STM32_HSECLK -#elif STM32_MCOSEL == STM32_MCOSEL_PLL -#define STM32_MCODIVCLK STM32_PLL_P_CLKOUT +#elif STM32_MCOSEL == STM32_MCOSEL_PLLRCLK +#define STM32_MCODIVCLK STM32_PLL_R_CLKOUT #elif STM32_MCOSEL == STM32_MCOSEL_LSI #define STM32_MCODIVCLK STM32_LSICLK @@ -1742,9 +1245,6 @@ #elif STM32_MCOSEL == STM32_MCOSEL_LSE #define STM32_MCODIVCLK STM32_LSECLK -#elif STM32_MCOSEL == STM32_MCOSEL_HSI48 -#define STM32_MCODIVCLK STM32_HSI48CLK - #else #error "invalid STM32_MCOSEL value specified" #endif @@ -1767,6 +1267,15 @@ #elif STM32_MCOPRE == STM32_MCOPRE_DIV16 #define STM32_MCOCLK (STM32_MCODIVCLK / 16) +#elif STM32_MCOPRE == STM32_MCOPRE_DIV32 +#define STM32_MCOCLK (STM32_MCODIVCLK / 32) + +#elif STM32_MCOPRE == STM32_MCOPRE_DIV64 +#define STM32_MCOCLK (STM32_MCODIVCLK / 64) + +#elif STM32_MCOPRE == STM32_MCOPRE_DIV128 +#define STM32_MCOCLK (STM32_MCODIVCLK / 128) + #else #error "invalid STM32_MCOPRE value specified" #endif @@ -1794,7 +1303,7 @@ * @brief USART1 clock frequency. */ #if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__) -#define STM32_USART1CLK STM32_PCLK2 +#define STM32_USART1CLK STM32_PCLK #elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK #define STM32_USART1CLK STM32_SYSCLK #elif STM32_USART1SEL == STM32_USART1SEL_HSI16 @@ -1809,7 +1318,7 @@ * @brief USART2 clock frequency. */ #if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_USART2CLK STM32_PCLK1 +#define STM32_USART2CLK STM32_PCLK #elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK #define STM32_USART2CLK STM32_SYSCLK #elif STM32_USART2SEL == STM32_USART2SEL_HSI16 @@ -1820,56 +1329,11 @@ #error "invalid source selected for USART2 clock" #endif -/** - * @brief USART3 clock frequency. - */ -#if (STM32_USART3SEL == STM32_USART3SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_USART3CLK STM32_PCLK1 -#elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK -#define STM32_USART3CLK STM32_SYSCLK -#elif STM32_USART3SEL == STM32_USART3SEL_HSI16 -#define STM32_USART3CLK STM32_HSI16CLK -#elif STM32_USART3SEL == STM32_USART3SEL_LSE -#define STM32_USART3CLK STM32_LSECLK -#else -#error "invalid source selected for USART3 clock" -#endif - -/** - * @brief UART4 clock frequency. - */ -#if (STM32_UART4SEL == STM32_UART4SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_UART4CLK STM32_PCLK1 -#elif STM32_UART4SEL == STM32_UART4SEL_SYSCLK -#define STM32_UART4CLK STM32_SYSCLK -#elif STM32_UART4SEL == STM32_UART4SEL_HSI16 -#define STM32_UART4CLK STM32_HSI16CLK -#elif STM32_UART4SEL == STM32_UART4SEL_LSE -#define STM32_UART4CLK STM32_LSECLK -#else -#error "invalid source selected for UART4 clock" -#endif - -/** - * @brief UART5 clock frequency. - */ -#if (STM32_UART5SEL == STM32_UART5SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_UART5CLK STM32_PCLK1 -#elif STM32_UART5SEL == STM32_UART5SEL_SYSCLK -#define STM32_UART5CLK STM32_SYSCLK -#elif STM32_UART5SEL == STM32_UART5SEL_HSI16 -#define STM32_UART5CLK STM32_HSI16CLK -#elif STM32_UART5SEL == STM32_UART5SEL_LSE -#define STM32_UART5CLK STM32_LSECLK -#else -#error "invalid source selected for UART5 clock" -#endif - /** * @brief LPUART1 clock frequency. */ #if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_LPUART1CLK STM32_PCLK1 +#define STM32_LPUART1CLK STM32_PCLK #elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK #define STM32_LPUART1CLK STM32_SYSCLK #elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16 @@ -1880,11 +1344,22 @@ #error "invalid source selected for LPUART1 clock" #endif +/** + * @brief CEC clock frequency. + */ +#if (STM32_CECSEL == STM32_CECSEL_HSI16DIV) || defined(__DOXYGEN__) +#define STM32_CECCLK (STM32_HSI16CLK / 448) +#elif STM32_CECSEL == STM32_CECSEL_LSE +#define STM32_CECCLK STM32_LSECLK +#else +#error "invalid source selected for CEC clock" +#endif + /** * @brief I2C1 clock frequency. */ #if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_I2C1CLK STM32_PCLK1 +#define STM32_I2C1CLK STM32_PCLK #elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK #define STM32_I2C1CLK STM32_SYSCLK #elif STM32_I2C1SEL == STM32_I2C1SEL_HSI16 @@ -1894,36 +1369,25 @@ #endif /** - * @brief I2C2 clock frequency. + * @brief I2S1 clock frequency. */ -#if (STM32_I2C2SEL == STM32_I2C2SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_I2C2CLK STM32_PCLK1 -#elif STM32_I2C2SEL == STM32_I2C2SEL_SYSCLK -#define STM32_I2C2CLK STM32_SYSCLK -#elif STM32_I2C2SEL == STM32_I2C2SEL_HSI16 -#define STM32_I2C2CLK STM32_HSI16CLK +#if (STM32_I2S1SEL == STM32_I2S1SEL_SYSCLK) || defined(__DOXYGEN__) +#define STM32_I2S1CLK STM32_SYSCLK +#elif STM32_I2S1SEL == STM32_I2S1SEL_PLLPCLK +#define STM32_I2S1CLK STM32_PLL_P_CLKOUT +#elif STM32_I2S1SEL == STM32_I2S1SEL_HSI16 +#define STM32_I2S1CLK STM32_HSI16CLK +#elif STM32_I2S1SEL == STM32_I2S1SEL_CKIN +#define STM32_I2S1CLK 0 /* Unknown, would require a board value */ #else -#error "invalid source selected for I2C2 clock" -#endif - -/** - * @brief I2C3 clock frequency. - */ -#if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_I2C3CLK STM32_PCLK1 -#elif STM32_I2C3SEL == STM32_I2C3SEL_SYSCLK -#define STM32_I2C3CLK STM32_SYSCLK -#elif STM32_I2C3SEL == STM32_I2C3SEL_HSI16 -#define STM32_I2C3CLK STM32_HSI16CLK -#else -#error "invalid source selected for I2C3 clock" +#error "invalid source selected for I2S1 clock" #endif /** * @brief LPTIM1 clock frequency. */ #if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_LPTIM1CLK STM32_PCLK1 +#define STM32_LPTIM1CLK STM32_PCLK #elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI #define STM32_LPTIM1CLK STM32_LSICLK #elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16 @@ -1938,7 +1402,7 @@ * @brief LPTIM2 clock frequency. */ #if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_LPTIM2CLK STM32_PCLK1 +#define STM32_LPTIM2CLK STM32_PCLK #elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSI #define STM32_LPTIM2CLK STM32_LSICLK #elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16 @@ -1950,85 +1414,88 @@ #endif /** - * @brief 48MHz clock frequency. + * @brief RNGDIV field. */ -#if (STM32_CLK48SEL == STM32_CLK48SEL_HSI48) || defined(__DOXYGEN__) -#define STM32_48CLK STM32_HSI48CLK -#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1 -#define STM32_48CLK (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE) -#elif STM32_CLK48SEL == STM32_CLK48SEL_PLL -#define STM32_48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE) -#elif STM32_CLK48SEL == STM32_CLK48SEL_MSI -#define STM32_48CLK STM32_MSICLK +#if (STM32_RNGDIV_VALUE == 1) || defined(__DOXYGEN__) +#define STM32_RNGDIV (0U << 28U) +#elif STM32_RNGDIV_VALUE == 2 +#define STM32_RNGDIV (1U << 28U) +#elif STM32_RNGDIV_VALUE == 4 +#define STM32_RNGDIV (2U << 28U) +#elif STM32_RNGDIV_VALUE == 8 +#define STM32_RNGDIV (3U << 28U) #else -#error "invalid source selected for 48CLK clock" +#error "invalid STM32_RNGDIV_VALUE value specified" #endif /** - * @brief USB clock point. + * @brief RNG clock frequency. */ -#define STM32_USBCLK STM32_48CLK - -/** - * @brief RNG clock point. - */ -#define STM32_RNGCLK STM32_48CLK +#if (STM32_RNGSEL == STM32_RNGSEL_NOCLOCK) || defined(__DOXYGEN__) +#define STM32_RNGCLK 0 +#elif STM32_RNGSEL == STM32_RNGSEL_HSI16 +#define STM32_RNGCLK (STM32_HSI16CLK / STM32_RNGDIV_VALUE) +#elif STM32_RNGSEL == STM32_RNGSEL_SYSCLK +#define STM32_RNGCLK (STM32_SYSCLK / STM32_RNGDIV_VALUE) +#elif STM32_RNGSEL == STM32_RNGSEL_PLLQCLK +#define STM32_RNGCLK (STM32_PLL_Q_CLKOUT / STM32_RNGDIV_VALUE) +#else +#error "invalid source selected for RNG clock" +#endif /** * @brief ADC clock frequency. */ #if (STM32_ADCSEL == STM32_ADCSEL_NOCLK) || defined(__DOXYGEN__) #define STM32_ADCCLK 0 -#elif STM32_ADCSEL == STM32_ADCSEL_PLLSAI1 -#define STM32_ADCCLK STM32_PLLSAI1_R_CLKOUT -#elif STM32_ADCSEL == STM32_ADCSEL_SYSCLK -#define STM32_ADCCLK STM32_SYSCLK +#elif STM32_ADCSEL == STM32_ADCSEL_PLLPCLK +#define STM32_ADCCLK STM32_PLL_P_CLKOUT +#elif STM32_ADCSEL == STM32_ADCSEL_HSI16 +#define STM32_ADCCLK STM32_HSI16CLK #else #error "invalid source selected for ADC clock" #endif /** - * @brief DFSDM clock frequency. + * @brief TIMPCLK clock frequency. */ -#if (STM32_DFSDMSEL == STM32_DFSDMSEL_PCLK2) || defined(__DOXYGEN__) -#define STM32_DFSDMCLK STM32_PCLK2 -#elif STM32_DFSDMSEL == STM32_DFSDMSEL_SYSCLK -#define STM32_DFSDMCLK STM32_SYSCLK +#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMPCLK (STM32_PCLK * 1) #else -#error "invalid source selected for DFSDM clock" +#define STM32_TIMPCLK (STM32_PCLK * 2) #endif /** - * @brief SDMMC frequency. + * @brief TIM1 clock frequency. */ -#define STM32_SDMMC1CLK STM32_48CLK +#if (STM32_TIM1SEL == STM32_TIM1SEL_TIMPCLK) || defined(__DOXYGEN__) +#define STM32_TIM1CLK STM32_TIMPCLK +#elif STM32_TIM1SEL == STM32_TIM1SEL_PLLQCLK +#define STM32_TIM1CLK STM32_PLL_Q_CLKOUT +#else +#error "invalid source selected for TIM1 clock" +#endif /** - * @brief Clock of timers connected to APB1 + * @brief TIM15 clock frequency. */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#if (STM32_TIM15SEL == STM32_TIM15SEL_TIMPCLK) || defined(__DOXYGEN__) +#define STM32_TIM15CLK STM32_TIMPCLK +#elif STM32_TIM15SEL == STM32_TIM15SEL_PLLQCLK +#define STM32_TIM15CLK STM32_PLL_Q_CLKOUT #else -#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#error "invalid source selected for TIM15 clock" #endif +/** + * @brief Clock of timers connected to APB1. + */ +#define STM32_TIMCLK1 STM32_TIMPCLK + /** * @brief Clock of timers connected to APB2. */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK2 (STM32_PCLK2 * 1) -#else -#define STM32_TIMCLK2 (STM32_PCLK2 * 2) -#endif - -/** - * @brief Voltage boost settings. - */ -#if (STM32_SYSCLK <= STM32_SYSCLK_NOBOOST_MAX) || defined(__DOXYGEN__) -#define STM32_R1MODE PWR_CR5_R1MODE -#else -#define STM32_R1MODE 0 -#endif +#define STM32_TIMCLK2 STM32_TIMPCLK /** * @brief Flash settings. @@ -2042,30 +1509,8 @@ #elif STM32_HCLK <= STM32_2WS_THRESHOLD #define STM32_FLASHBITS FLASH_ACR_LATENCY_2WS -#elif STM32_HCLK <= STM32_3WS_THRESHOLD +#else #define STM32_FLASHBITS FLASH_ACR_LATENCY_3WS - -#else -#define STM32_FLASHBITS FLASH_ACR_LATENCY_4WS -#endif - -/** - * @brief Flash settings for MSI. - */ -#if (STM32_MSICLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__) -#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_0WS - -#elif STM32_MSICLK <= STM32_1WS_THRESHOLD -#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_1WS - -#elif STM32_MSICLK <= STM32_2WS_THRESHOLD -#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_2WS - -#elif STM32_MSICLK <= STM32_3WS_THRESHOLD -#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_3WS - -#else -#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_4WS #endif /*===========================================================================*/ @@ -2082,11 +1527,9 @@ /* Various helpers.*/ #include "nvic.h" -#include "cache.h" -#include "mpu_v7m.h" #include "stm32_isr.h" -#include "stm32_dma.h" -#include "stm32_exti.h" +//#include "stm32_dma.h" +//#include "stm32_exti.h" #include "stm32_rcc.h" #ifdef __cplusplus