git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6564 35acf78f-673a-0410-8e92-d51de3d6d3f4
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gdisirio
parent
db6fea6a28
commit
e8ce87c327
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@ -36,96 +36,90 @@
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/*
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* CAN units.
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*/
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#define STM32_CAN1_TX_HANDLER CAN1_TX_IRQHandler
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#define STM32_CAN1_RX0_HANDLER CAN1_RX0_IRQHandler
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#define STM32_CAN1_RX1_HANDLER CAN1_RX1_IRQHandler
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#define STM32_CAN1_SCE_HANDLER CAN1_SCE_IRQHandler
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#define STM32_CAN2_TX_HANDLER CAN2_TX_IRQHandler
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#define STM32_CAN2_RX0_HANDLER CAN2_RX0_IRQHandler
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#define STM32_CAN2_RX1_HANDLER CAN2_RX1_IRQHandler
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#define STM32_CAN2_SCE_HANDLER CAN2_SCE_IRQHandler
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#define STM32_CAN1_TX_HANDLER Vector8C
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#define STM32_CAN1_RX0_HANDLER Vector90
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#define STM32_CAN1_RX1_HANDLER Vector94
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#define STM32_CAN1_SCE_HANDLER Vector98
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#define STM32_CAN2_TX_HANDLER Vector13C
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#define STM32_CAN2_RX0_HANDLER Vector140
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#define STM32_CAN2_RX1_HANDLER Vector144
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#define STM32_CAN2_SCE_HANDLER Vector148
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#ifdef STM32F10X_CL
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#define STM32_CAN1_TX_NUMBER CAN1_TX_IRQn
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#define STM32_CAN1_RX0_NUMBER CAN1_RX0_IRQn
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#else
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#define STM32_CAN1_TX_NUMBER USB_HP_CAN1_TX_IRQn
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#define STM32_CAN1_RX0_NUMBER USB_LP_CAN1_RX0_IRQn
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#endif
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#define STM32_CAN1_RX1_NUMBER CAN1_RX1_IRQn
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#define STM32_CAN1_SCE_NUMBER CAN1_SCE_IRQn
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#define STM32_CAN2_TX_NUMBER CAN2_TX_IRQn
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#define STM32_CAN2_RX0_NUMBER CAN2_RX0_IRQn
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#define STM32_CAN2_RX1_NUMBER CAN2_RX1_IRQn
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#define STM32_CAN2_SCE_NUMBER CAN2_SCE_IRQn
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#define STM32_CAN1_TX_NUMBER 19
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#define STM32_CAN1_RX0_NUMBER 20
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#define STM32_CAN1_RX1_NUMBER 21
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#define STM32_CAN1_SCE_NUMBER 22
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#define STM32_CAN2_TX_NUMBER 63
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#define STM32_CAN2_RX0_NUMBER 64
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#define STM32_CAN2_RX1_NUMBER 65
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#define STM32_CAN2_SCE_NUMBER 66
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/*
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* I2C units.
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*/
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#define STM32_I2C1_EVENT_HANDLER VectorBC
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#define STM32_I2C1_ERROR_HANDLER VectorC0
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#define STM32_I2C1_EVENT_NUMBER 31
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#define STM32_I2C1_ERROR_NUMBER 32
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#define STM32_I2C2_EVENT_HANDLER VectorC4
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#define STM32_I2C2_ERROR_HANDLER VectorC8
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#define STM32_I2C2_EVENT_NUMBER 33
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#define STM32_I2C2_ERROR_NUMBER 34
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/*
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* OTG units.
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*/
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#define STM32_OTG1_HANDLER OTG_FS_IRQHandler
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#define STM32_OTG1_HANDLER Vector14C
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#define STM32_OTG1_NUMBER OTG_FS_IRQn
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#define STM32_OTG1_NUMBER 67
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/*
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* SDIO unit.
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*/
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#define STM32_SDIO_HANDLER SDIO_IRQHandler
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#define STM32_SDIO_HANDLER Vector104
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#define STM32_SDIO_NUMBER SDIO_IRQn
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#define STM32_SDIO_NUMBER 49
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/*
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* TIM units.
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*/
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#if defined(STM32F10X_XL)
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#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler
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#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
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defined(STM32F10X_HD_VL)
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#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler
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#else
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#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler
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#endif
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#define STM32_TIM1_CC_HANDLER TIM1_CC_IRQHandler
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#define STM32_TIM2_HANDLER TIM2_IRQHandler
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#define STM32_TIM3_HANDLER TIM3_IRQHandler
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#define STM32_TIM4_HANDLER TIM4_IRQHandler
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#define STM32_TIM5_HANDLER TIM5_IRQHandler
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#define STM32_TIM8_UP_HANDLER TIM8_UP_IRQHandler
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#define STM32_TIM8_CC_HANDLER TIM8_CC_IRQHandler
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#define STM32_TIM1_UP_HANDLER VectorA4
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#define STM32_TIM1_CC_HANDLER VectorAC
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#define STM32_TIM2_HANDLER VectorB0
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#define STM32_TIM3_HANDLER VectorB4
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#define STM32_TIM4_HANDLER VectorB8
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#define STM32_TIM5_HANDLER Vector108
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#define STM32_TIM6_HANDLER Vector118
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#define STM32_TIM7_HANDLER Vector11C
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#define STM32_TIM8_UP_HANDLER VectorF0
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#define STM32_TIM8_CC_HANDLER VectorF8
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#if defined(STM32F10X_XL)
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#define STM32_TIM1_UP_NUMBER TIM1_UP_TIM10_IRQn
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#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
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defined(STM32F10X_HD_VL)
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#define STM32_TIM1_UP_NUMBER TIM1_UP_TIM16_IRQn
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#else
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#define STM32_TIM1_UP_NUMBER TIM1_UP_IRQn
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#endif
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#define STM32_TIM1_CC_NUMBER TIM1_CC_IRQn
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#define STM32_TIM2_NUMBER TIM2_IRQn
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#define STM32_TIM3_NUMBER TIM3_IRQn
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#define STM32_TIM4_NUMBER TIM4_IRQn
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#define STM32_TIM5_NUMBER TIM5_IRQn
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#ifdef STM32F10X_XL
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#define STM32_TIM8_UP_NUMBER TIM8_UP_TIM13_IRQn
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#else
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#define STM32_TIM8_UP_NUMBER TIM8_UP_IRQn
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#endif
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#define STM32_TIM8_CC_NUMBER TIM8_CC_IRQn
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#define STM32_TIM1_UP_NUMBER 25
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#define STM32_TIM1_CC_NUMBER 27
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#define STM32_TIM2_NUMBER 28
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#define STM32_TIM3_NUMBER 29
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#define STM32_TIM4_NUMBER 30
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#define STM32_TIM5_NUMBER 50
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#define STM32_TIM6_NUMBER 54
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#define STM32_TIM7_NUMBER 55
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#define STM32_TIM8_UP_NUMBER 44
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#define STM32_TIM8_CC_NUMBER 46
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/*
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* USART units.
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*/
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#define STM32_USART1_HANDLER USART1_IRQHandler
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#define STM32_USART2_HANDLER USART2_IRQHandler
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#define STM32_USART3_HANDLER USART3_IRQHandler
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#define STM32_UART4_HANDLER UART4_IRQHandler
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#define STM32_UART5_HANDLER UART5_IRQHandler
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#define STM32_USART1_HANDLER VectorD4
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#define STM32_USART2_HANDLER VectorD8
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#define STM32_USART3_HANDLER VectorDC
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#define STM32_UART4_HANDLER Vector110
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#define STM32_UART5_HANDLER Vector114
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#define STM32_USART1_NUMBER USART1_IRQn
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#define STM32_USART2_NUMBER USART2_IRQn
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#define STM32_USART3_NUMBER USART3_IRQn
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#define STM32_UART4_NUMBER UART4_IRQn
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#define STM32_UART5_NUMBER UART5_IRQn
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#define STM32_USART1_NUMBER 37
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#define STM32_USART2_NUMBER 38
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#define STM32_USART3_NUMBER 39
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#define STM32_UART4_NUMBER 52
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#define STM32_UART5_NUMBER 53
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/*
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* USB units.
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@ -133,8 +127,8 @@
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#define STM32_USB1_HP_HANDLER Vector8C
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#define STM32_USB1_LP_HANDLER Vector90
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#define STM32_USB1_HP_NUMBER USB_HP_CAN1_TX_IRQn
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#define STM32_USB1_LP_NUMBER USB_LP_CAN1_RX0_IRQn
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#define STM32_USB1_HP_NUMBER 19
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#define STM32_USB1_LP_NUMBER 20
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/** @} */
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/*===========================================================================*/
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@ -745,6 +745,56 @@
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*/
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#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST)
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/**
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* @brief Enables the TIM6 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
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/**
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* @brief Disables the TIM6 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
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/**
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* @brief Resets the TIM6 peripheral.
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*
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* @api
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*/
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#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
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/**
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* @brief Enables the TIM7 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
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/**
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* @brief Disables the TIM7 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
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/**
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* @brief Resets the TIM7 peripheral.
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*
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* @api
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*/
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#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
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/**
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* @brief Enables the TIM8 peripheral clock.
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* @note The @p lp parameter is ignored in this family.
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