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Fixed bug #835. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10209 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2017-05-28 13:11:05 +00:00
parent 5b9c975a2d
commit e9c2b92359
16 changed files with 243 additions and 98 deletions
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8
demos/STM32/NIL-STM32F746G-DISCOVERY/mcuconf.h
View File

@ -18,7 +18,7 @@
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* STM32F7xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
@ -60,7 +60,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
@ -69,9 +69,11 @@
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1

6
demos/STM32/RT-STM32F746G-DISCOVERY-LWIP-FATFS-USB/mcuconf.h
View File

@ -60,7 +60,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
@ -69,9 +69,11 @@
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1

104
demos/STM32/RT-STM32F746G-DISCOVERY/debug/RT-STM32F746G-DISCOVERY (OpenOCD, Flash and Run).launch
View File

@ -1,52 +1,52 @@
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6
demos/STM32/RT-STM32F746G-DISCOVERY/mcuconf.h
View File

@ -60,7 +60,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
@ -69,9 +69,11 @@
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1

8
demos/STM32/RT-STM32F746ZG-NUCLEO144/mcuconf.h
View File

@ -18,7 +18,7 @@
#define MCUCONF_H
/*
* STM32Fxx drivers configuration.
* STM32F7xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
@ -60,7 +60,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
@ -69,9 +69,11 @@
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1

8
demos/STM32/RT-STM32F767ZI-NUCLEO144/mcuconf.h
View File

@ -60,7 +60,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
@ -69,9 +69,11 @@
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1
@ -113,8 +115,10 @@
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE
#define STM32_CAN_USE_CAN3 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
#define STM32_CAN_CAN3_IRQ_PRIORITY 11
/*
* DAC driver system settings.

8
demos/STM32/RT-STM32F769I-DISCOVERY/mcuconf.h
View File

@ -60,7 +60,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
@ -69,9 +69,11 @@
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1
@ -113,8 +115,10 @@
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE
#define STM32_CAN_USE_CAN3 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
#define STM32_CAN_CAN3_IRQ_PRIORITY 11
/*
* DAC driver system settings.

5
os/hal/ports/STM32/STM32F7xx/hal_lld.c
View File

@ -262,15 +262,12 @@ void stm32_clock_init(void) {
/* DCKCFGR1 register initialization, note, must take care of the _OFF
pseudo settings.*/
{
uint32_t dckcfgr1 = 0;
uint32_t dckcfgr1 = STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ | STM32_PLLSAIDIVR;
#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
dckcfgr1 |= STM32_SAI2SEL;
#endif
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
dckcfgr1 |= STM32_SAI1SEL;
#endif
#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
dckcfgr1 |= STM32_PLLSAIDIVR;
#endif
RCC->DCKCFGR1 = dckcfgr1;
}

130
os/hal/ports/STM32/STM32F7xx/hal_lld.h
View File

@ -263,6 +263,7 @@
#define STM32_I2SSRC_MASK (1 << 23) /**< I2CSRC mask. */
#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */
#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */
#define STM32_I2SSRC_OFF (1 << 23) /**< ISS clock not required. */
#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */
#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */
@ -301,7 +302,6 @@
#define STM32_PLLSAIDIVR_DIV4 (1 << 16) /**< LCD_CLK is R divided by 4. */
#define STM32_PLLSAIDIVR_DIV8 (2 << 16) /**< LCD_CLK is R divided by 8. */
#define STM32_PLLSAIDIVR_DIV16 (3 << 16) /**< LCD_CLK is R divided by 16.*/
#define STM32_PLLSAIDIVR_OFF 0xFFFFFFFFU /**< LCD CLK is not required. */
#define STM32_SAI1SEL_MASK (3 << 20) /**< SAI1SEL mask. */
#define STM32_SAI1SEL_SAIPLL (0 << 20) /**< SAI1 source is SAIPLL. */
@ -658,6 +658,13 @@
#define STM32_PLLI2SQ_VALUE 4
#endif
/**
* @brief PLLI2SDIVQ divider value (SAI clock divider).
*/
#if !defined(STM32_PLLI2SDIVQ_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLI2SDIVQ_VALUE 2
#endif
/**
* @brief PLLI2SR divider value.
* @note The allowed values are 2..7.
@ -698,11 +705,18 @@
#define STM32_PLLSAIR_VALUE 4
#endif
/**
* @brief PLLSAIDIVQ divider value (SAI clock divider).
*/
#if !defined(STM32_PLLSAIDIVQ_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAIDIVQ_VALUE 2
#endif
/**
* @brief PLLSAIDIVR divider value (LCD clock divider).
*/
#if !defined(STM32_PLLSAIDIVR) || defined(__DOXYGEN__)
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#if !defined(STM32_PLLSAIDIVR_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAIDIVR_VALUE 2
#endif
/**
@ -719,6 +733,13 @@
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#endif
/**
* @brief LCD-TFT clock enable switch.
*/
#if !defined(STM32_LCDTFT_REQUIRED) || defined(__DOXYGEN__)
#define STM32_LCDTFT_REQUIRED FALSE
#endif
/**
* @brief USART1 clock source.
*/
@ -945,9 +966,9 @@
#error "HSI not enabled, required by STM32_SAI2SEL"
#endif
#if (STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF) && \
#if STM32_LCDTFT_REQUIRED && \
(STM32_PLLSRC == STM32_PLLSRC_HSI)
#error "HSI not enabled, required by STM32_PLLSAIDIVR"
#error "HSI not enabled, required by STM32_LCDTFT_REQUIRED"
#endif
#endif /* !STM32_HSI_ENABLED */
@ -1009,9 +1030,9 @@
#error "HSE not enabled, required by STM32_SAI2SEL"
#endif
#if (STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF) && \
#if STM32_LCDTFT_REQUIRED && \
(STM32_PLLSRC == STM32_PLLSRC_HSE)
#error "HSE not enabled, required by STM32_PLLSAIDIVR"
#error "HSE not enabled, required by STM32_LCDTFT_REQUIRED"
#endif
#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
@ -1404,11 +1425,24 @@
*/
#define STM32_PLLI2S_R_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE)
/**
* @brief STM32_PLLI2SDIVQ field.
*/
#if (STM32_PLLI2SDIVQ_VALUE < 1) || (STM32_PLLI2SDIVQ_VALUE > 32)
#error "STM32_PLLI2SDIVQ_VALUE out of acceptable range"
#endif
#define STM32_PLLI2SDIVQ (STM32_PLLI2SDIVQ_VALUE << 0)
/**
* @brief PLLI2S Q output clock frequency after divisor.
*/
#define STM32_PLLI2SDIVQ_CLKOUT (STM32_PLLI2S_Q_CLKOUT / STM32_PLLI2SDIVQ_VALUE)
/*
* PLLSAI enable check.
*/
#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI)) | \
(STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF) || \
STM32_LCDTFT_REQUIRED || \
(STM32_SAI1SEL == STM32_SAI1SEL_SAIPLL) || \
(STM32_SAI2SEL == STM32_SAI2SEL_SAIPLL) || \
defined(__DOXYGEN__)
@ -1497,6 +1531,43 @@
*/
#define STM32_PLLSAI_R_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIR_VALUE)
/**
* @brief STM32_PLLSAIDIVQ field.
*/
#if (STM32_PLLSAIDIVQ_VALUE < 1) || (STM32_PLLSAIDIVQ_VALUE > 32)
#error "STM32_PLLSAIDIVQ_VALUE out of acceptable range"
#endif
#define STM32_PLLSAIDIVQ (STM32_PLLSAIDIVQ_VALUE << 8)
/**
* @brief PLLSAI Q output clock frequency after divisor.
*/
#define STM32_PLLSAIDIVQ_CLKOUT (STM32_PLLSAI_Q_CLKOUT / STM32_PLLSAIDIVQ_VALUE)
/*
* STM32_PLLSAIDIVR field.
*/
#if (STM32_PLLSAIDIVR_VALUE == 2) || defined(__DOXYGEN__)
#define STM32_PLLSAIDIVR (0 << 16)
#elif STM32_PLLSAIDIVR_VALUE == 4
#define STM32_PLLSAIDIVR (1 << 16)
#elif STM32_PLLSAIDIVR_VALUE == 8
#define STM32_PLLSAIDIVR (2 << 16)
#elif STM32_PLLSAIDIVR_VALUE == 16
#define STM32_PLLSAIDIVR (3 << 16)
#else
#error "invalid STM32_PLLSAIDIVR_VALUE value specified"
#endif
/**
* @brief PLLSAI R output clock frequency after divisor.
*/
#define STM32_PLLSAIDIVR_CLKOUT (STM32_PLLSAI_R_CLKOUT / STM32_PLLSAIDIVR_VALUE)
/**
* @brief MCO1 divider clock.
*/
@ -1820,6 +1891,49 @@
#define STM32_PLL48CLK 0
#endif /* !STM32_CLOCK48_REQUIRED */
/**
* @brief I2S frequency.
*/
#if (STM32_I2SSRC == STM32_I2SSRC_OFF) || defined(__DOXYGEN__)
#define STM32_I2SCLK 0
#elif STM32_I2SSRC == STM32_I2SSRC_CKIN
#define STM32_I2SCLK 0 /* Unknown, would require a board value */
#elif STM32_I2SSRC == STM32_I2SSRC_PLLI2S
#define STM32_I2SCLK STM32_PLLI2S_R_CLKOUT
#else
#error "invalid source selected for I2S clock"
#endif
/**
* @brief SAI1 frequency.
*/
#if (STM32_SAI1SEL == STM32_SAI1SEL_OFF) || defined(__DOXYGEN__)
#define STM32_SAI1CLK 0
#elif STM32_SAI1SEL == STM32_SAI1SEL_SAIPLL
#define STM32_SAI1SEL STM32_PLLSAIDIVQ_CLKOUT
#elif STM32_SAI1SEL == STM32_SAI1SEL_I2SPLL
#define STM32_SAI1SEL STM32_PLLI2SDIVQ_CLKOUT
#elif STM32_SAI1SEL == STM32_SAI1SEL_CKIN
#define STM32_SAI1SEL 0 /* Unknown, would require a board value */
#else
#error "invalid source selected for SAI1 clock"
#endif
/**
* @brief SAI2 frequency.
*/
#if (STM32_SAI2SEL == STM32_SAI2SEL_OFF) || defined(__DOXYGEN__)
#define STM32_SAI2CLK 0
#elif STM32_SAI2SEL == STM32_SAI2SEL_SAIPLL
#define STM32_SAI2SEL STM32_PLLSAIDIVQ_CLKOUT
#elif STM32_SAI2SEL == STM32_SAI2SEL_I2SPLL
#define STM32_SAI2SEL STM32_PLLI2SDIVQ_CLKOUT
#elif STM32_SAI2SEL == STM32_SAI2SEL_CKIN
#define STM32_SAI2SEL 0 /* Unknown, would require a board value */
#else
#error "invalid source selected for SAI2 clock"
#endif
/**
* @brief SDMMC frequency.
*/

1
readme.txt
View File

@ -167,6 +167,7 @@
to 16.1.9).
- HAL: Fixed issue with not supported LIN on STM32F070xB (bug #837)(backported
to 16.1.9).
- HAL: fixed missing DCKFG1 fields (bug #835).
- HAL: Fixed STM32 OTGv1 number of endpoints (bug #833)(backported to 16.1.8).
- HAL: Fixed transaction end problem with STM32 OTGv1 driver (bug #832)
(backported to 16.1.8).

8
testhal/STM32/STM32F7xx/GPT-ADC/mcuconf.h
View File

@ -18,7 +18,7 @@
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* STM32F7xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
@ -60,7 +60,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
@ -69,9 +69,11 @@
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1

13
testhal/STM32/STM32F7xx/IRQ_STORM/mcuconf.h
View File

@ -18,7 +18,7 @@
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* STM32F7xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
@ -60,7 +60,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
@ -69,9 +69,11 @@
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1
@ -183,6 +185,7 @@
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_USE_I2C4 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
@ -190,12 +193,16 @@
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C4_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_I2C4_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*

12
testhal/STM32/STM32F7xx/PWM-ICU/mcuconf.h
View File

@ -18,7 +18,7 @@
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* STM32F7xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
@ -60,7 +60,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
@ -69,9 +69,11 @@
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1
@ -94,7 +96,7 @@
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
@ -155,7 +157,7 @@
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 TRUE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE

8
testhal/STM32/STM32F7xx/SPI/mcuconf.h
View File

@ -18,7 +18,7 @@
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* STM32F7xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
@ -60,7 +60,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
@ -69,9 +69,11 @@
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1

8
testhal/STM32/STM32F7xx/USB_CDC/mcuconf.h
View File

@ -18,7 +18,7 @@
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* STM32F7xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
@ -60,7 +60,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
@ -69,9 +69,11 @@
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1

8
testhal/STM32/STM32F7xx/USB_RAW/mcuconf.h
View File

@ -18,7 +18,7 @@
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* STM32F7xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
@ -60,7 +60,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
@ -69,9 +69,11 @@
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1