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Merge pull request #39 from dron0gus/artery-dev-backport 

Artery: MFS support for AT32F43X, hal test
This commit is contained in:
rusefillc 2023-11-03 07:20:58 -04:00 committed by GitHub
parent 12889f8530 421ff88eb4
commit e9d08d00d1
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GPG Key ID: 4AEE18F83AFDEB23
15 changed files with 2328 additions and 698 deletions
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232
os/common/ext/Artery/AT32F4xx/at32f435xx.h
View File

@ -526,13 +526,12 @@ typedef struct
typedef struct
{
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
__IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
__IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
__IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
__IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
__IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
__IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
__IO uint32_t PSR; /*!< FLASH performance select register, Address offset: 0x00 */
__IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
__IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
__IO uint32_t STS; /*!< FLASH status register, Address offset: 0x0C */
__IO uint32_t CTRL; /*!< FLASH control register, Address offset: 0x10 */
__IO uint32_t ADDR; /*!< FLASH address registe, Address offset: 0x14 */
} FLASH_TypeDef;
/**
@ -1082,7 +1081,7 @@ typedef struct
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE 0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region */
#define FLASH_BASE 0x08000000U /*!< FLASH(up to 4 MB) base address in the alias region */
#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
@ -1191,6 +1190,7 @@ typedef struct
#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
#define FLASH2_R_BASE (FLASH_R_BASE + 0x40U)
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6400U)
#define DMA1_Channel1_BASE (DMA1_BASE + 0x008U)
#define DMA1_Channel2_BASE (DMA1_BASE + 0x01CU)
@ -1326,7 +1326,8 @@ typedef struct
#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define FLASH1 ((FLASH_TypeDef *) FLASH_R_BASE)
#define FLASH2 ((FLASH_TypeDef *) FLASH2_R_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
@ -7105,186 +7106,41 @@ typedef struct
/* FLASH */
/* */
/******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS 0x00000000U
#define FLASH_ACR_LATENCY_1WS 0x00000001U
#define FLASH_ACR_LATENCY_2WS 0x00000002U
#define FLASH_ACR_LATENCY_3WS 0x00000003U
#define FLASH_ACR_LATENCY_4WS 0x00000004U
#define FLASH_ACR_LATENCY_5WS 0x00000005U
#define FLASH_ACR_LATENCY_6WS 0x00000006U
#define FLASH_ACR_LATENCY_7WS 0x00000007U
/******************* Bits definition for FLASH_STS register *****************/
#define FLASH_STS_OBF_Pos (0U)
#define FLASH_STS_OBF_Msk (0x1U << FLASH_STS_OBF_Pos) /*!< 0x00000001 */
#define FLASH_STS_OBF FLASH_STS_OBF_Msk
#define FLASH_STS_PRGMERR_Pos (2U)
#define FLASH_STS_PRGMERR_Msk (0x1U << FLASH_STS_PRGMERR_Pos) /*!< 0x00000004 */
#define FLASH_STS_PRGMERR FLASH_STS_PRGMERR_Msk
#define FLASH_STS_EPPERR_Pos (4U)
#define FLASH_STS_EPPERR_Msk (0x1U << FLASH_STS_EPPERR_Pos) /*!< 0x00000010 */
#define FLASH_STS_EPPERR FLASH_STS_EPPERR_Msk
#define FLASH_STS_ODF_Pos (5U)
#define FLASH_STS_ODF_Msk (0x1U << FLASH_STS_ODF_Pos) /*!< 0x00000020 */
#define FLASH_STS_ODF FLASH_STS_ODF_Msk
#define FLASH_ACR_LATENCY_8WS 0x00000008U
#define FLASH_ACR_LATENCY_9WS 0x00000009U
#define FLASH_ACR_LATENCY_10WS 0x0000000AU
#define FLASH_ACR_LATENCY_11WS 0x0000000BU
#define FLASH_ACR_LATENCY_12WS 0x0000000CU
#define FLASH_ACR_LATENCY_13WS 0x0000000DU
#define FLASH_ACR_LATENCY_14WS 0x0000000EU
#define FLASH_ACR_LATENCY_15WS 0x0000000FU
#define FLASH_ACR_PRFTEN_Pos (8U)
#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
#define FLASH_ACR_ICEN_Pos (9U)
#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
#define FLASH_ACR_DCEN_Pos (10U)
#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
#define FLASH_ACR_ICRST_Pos (11U)
#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
#define FLASH_ACR_DCRST_Pos (12U)
#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
/******************* Bits definition for FLASH_SR register ******************/
#define FLASH_SR_EOP_Pos (0U)
#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
#define FLASH_SR_EOP FLASH_SR_EOP_Msk
#define FLASH_SR_SOP_Pos (1U)
#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
#define FLASH_SR_SOP FLASH_SR_SOP_Msk
#define FLASH_SR_WRPERR_Pos (4U)
#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
#define FLASH_SR_PGAERR_Pos (5U)
#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
#define FLASH_SR_PGPERR_Pos (6U)
#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
#define FLASH_SR_PGSERR_Pos (7U)
#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
#define FLASH_SR_RDERR_Pos (8U)
#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
#define FLASH_SR_BSY_Pos (16U)
#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
#define FLASH_SR_BSY FLASH_SR_BSY_Msk
/******************* Bits definition for FLASH_CR register ******************/
#define FLASH_CR_PG_Pos (0U)
#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
#define FLASH_CR_PG FLASH_CR_PG_Msk
#define FLASH_CR_SER_Pos (1U)
#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
#define FLASH_CR_SER FLASH_CR_SER_Msk
#define FLASH_CR_MER_Pos (2U)
#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER FLASH_CR_MER_Msk
#define FLASH_CR_MER1 FLASH_CR_MER
#define FLASH_CR_SNB_Pos (3U)
#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
#define FLASH_CR_SNB FLASH_CR_SNB_Msk
#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
#define FLASH_CR_PSIZE_Pos (8U)
#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
#define FLASH_CR_MER2_Pos (15U)
#define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
#define FLASH_CR_STRT FLASH_CR_STRT_Msk
#define FLASH_CR_EOPIE_Pos (24U)
#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
#define FLASH_CR_LOCK_Pos (31U)
#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
/******************* Bits definition for FLASH_OPTCR register ***************/
#define FLASH_OPTCR_OPTLOCK_Pos (0U)
#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
#define FLASH_OPTCR_OPTSTRT_Pos (1U)
#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
#define FLASH_OPTCR_BOR_LEV_Pos (2U)
#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
#define FLASH_OPTCR_BFB2_Pos (4U)
#define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
#define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
#define FLASH_OPTCR_WDG_SW_Pos (5U)
#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
#define FLASH_OPTCR_nRST_STOP_Pos (6U)
#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
#define FLASH_OPTCR_RDP_Pos (8U)
#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
#define FLASH_OPTCR_nWRP_Pos (16U)
#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
#define FLASH_OPTCR_nWRP_0 0x00010000U
#define FLASH_OPTCR_nWRP_1 0x00020000U
#define FLASH_OPTCR_nWRP_2 0x00040000U
#define FLASH_OPTCR_nWRP_3 0x00080000U
#define FLASH_OPTCR_nWRP_4 0x00100000U
#define FLASH_OPTCR_nWRP_5 0x00200000U
#define FLASH_OPTCR_nWRP_6 0x00400000U
#define FLASH_OPTCR_nWRP_7 0x00800000U
#define FLASH_OPTCR_nWRP_8 0x01000000U
#define FLASH_OPTCR_nWRP_9 0x02000000U
#define FLASH_OPTCR_nWRP_10 0x04000000U
#define FLASH_OPTCR_nWRP_11 0x08000000U
#define FLASH_OPTCR_DB1M_Pos (30U)
#define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
#define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
#define FLASH_OPTCR_SPRMOD_Pos (31U)
#define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
#define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
/****************** Bits definition for FLASH_OPTCR1 register ***************/
#define FLASH_OPTCR1_nWRP_Pos (16U)
#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
/******************* Bits definition for FLASH_CTRL register ****************/
#define FLASH_CTRL_PRGM_Pos (0U)
#define FLASH_CTRL_PRGM_Msk (0x1U << FLASH_CTRL_PRGM_Pos) /*!< 0x00000001 */
#define FLASH_CTRL_PRGM FLASH_CTRL_PRGM_Msk
#define FLASH_CTRL_SECERS_Pos (1U)
#define FLASH_CTRL_SECERS_Msk (0x1U << FLASH_CTRL_SECERS_Pos) /*!< 0x00000002 */
#define FLASH_CTRL_SECERS FLASH_CTRL_SECERS_Msk
#define FLASH_CTRL_BANKERS_Pos (2U)
#define FLASH_CTRL_BANKERS_Msk (0x1U << FLASH_CTRL_BANKERS_Pos) /*!< 0x00000004 */
#define FLASH_CTRL_BANKERS FLASH_CTRL_BANKERS_Msk
#define FLASH_CTRL_BLKERS_Pos (3U)
#define FLASH_CTRL_BLKERS_Msk (0x1U << FLASH_CTRL_BLKERS_Pos) /*!< 0x000000F8 */
#define FLASH_CTRL_BLKERS FLASH_CTRL_BLKERS_Msk
/* USER area erase and program */
#define FLASH_CTRL_ERSTR_Pos (6U)
#define FLASH_CTRL_ERSTR_Msk (0x1U << FLASH_CTRL_ERSTR_Pos) /*!< 0x80000080 */
#define FLASH_CTRL_ERSTR FLASH_CTRL_ERSTR_Msk
#define FLASH_CTRL_LOCK_Pos (7U)
#define FLASH_CTRL_LOCK_Msk (0x1U << FLASH_CTRL_LOCK_Pos) /*!< 0x80000080 */
#define FLASH_CTRL_LOCK FLASH_CTRL_LOCK_Msk
/******************************************************************************/
/* */

3
os/hal/boards/AT_START_F435/board.h
View File

@ -324,8 +324,11 @@
*/
#define LINE_LED1 PAL_LINE(GPIOD, 13U)
#define LINE_LED_RED LINE_LED1
#define LINE_LED2 PAL_LINE(GPIOD, 14U)
#define LINE_LED_YELLOW LINE_LED2
#define LINE_LED3 PAL_LINE(GPIOD, 15U)
#define LINE_LED_GREEN LINE_LED3
#define LINE_BUTTON PAL_LINE(GPIOA, 0U)

612
os/hal/ports/AT32/AT32F4xx/hal_efl_lld.c
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
ChibiOS - Copyright (C) 2023 Andrey Gusakov
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -16,7 +16,7 @@
/**
* @file hal_efl_lld.c
* @brief STM32F4xx Embedded Flash subsystem low level driver source.
* @brief AT32F43X Embedded Flash subsystem low level driver source.
*
* @addtogroup HAL_EFL
* @{
@ -32,8 +32,9 @@
/* Driver local definitions. */
/*===========================================================================*/
#define STM32_FLASH_LINE_SIZE (1 << STM32_FLASH_PSIZE)
#define STM32_FLASH_LINE_MASK (STM32_FLASH_LINE_SIZE - 1U)
/* The Flash memory can be programmed with 32 bits, 16 bits or 8 bits at a time. */
#define AT32_FLASH_LINE_SIZE (4)
#define AT32_FLASH_LINE_MASK (AT32_FLASH_LINE_SIZE - 1U)
#define FLASH_PDKEY1 0x04152637U
#define FLASH_PDKEY2 0xFAFBFCFDU
@ -44,12 +45,8 @@
#define FLASH_OPTKEY1 0x08192A3BU
#define FLASH_OPTKEY2 0x4C5D6E7FU
#if !defined(FLASH_SR_OPERR)
#define FLASH_SR_OPERR FLASH_SR_SOP
#endif
#if !defined(STM32_FLASH_DUAL_BANK_PERMANENT)
#define STM32_FLASH_DUAL_BANK_PERMANENT FALSE
#if !defined(FLASH_STS_OPERR)
#define FLASH_STS_OPERR FLASH_STS_SOP
#endif
/*===========================================================================*/
@ -57,333 +54,118 @@
/*===========================================================================*/
/**
* @brief EFL1 driver identifier.
* @brief EFL1 driver identifier - first bank.
*/
EFlashDriver EFLD1;
/**
* @brief EFL2 driver identifier - second bank.
*/
EFlashDriver EFLD2;
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
#if defined(STM32F413xx) || defined(STM32F412xx) || \
defined(STM32F40_41xxx) || defined(__DOXYGEN__)
/* Sector table for 1.5M device. */
static const flash_sector_descriptor_t efl_lld_sect1[STM32_FLASH1_SECTORS_TOTAL] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
{ 4 * 16384 + 65536, 131072}, /* Sector 5. */
{ 4 * 16384 + 65536 + 1 * 131072, 131072}, /* Sector 6. */
{ 4 * 16384 + 65536 + 2 * 131072, 131072}, /* Sector 7. */
{ 4 * 16384 + 65536 + 3 * 131072, 131072}, /* Sector 8. */
{ 4 * 16384 + 65536 + 4 * 131072, 131072}, /* Sector 9. */
{ 4 * 16384 + 65536 + 5 * 131072, 131072}, /* Sector 10. */
{ 4 * 16384 + 65536 + 6 * 131072, 131072}, /* Sector 11. */
{ 4 * 16384 + 65536 + 7 * 131072, 131072}, /* Sector 12. */
{ 4 * 16384 + 65536 + 8 * 131072, 131072}, /* Sector 13. */
{ 4 * 16384 + 65536 + 9 * 131072, 131072}, /* Sector 14. */
{ 4 * 16384 + 65536 + 10 * 131072, 131072} /* Sector 15. */
};
/* Sector table for 1M device. */
static const flash_sector_descriptor_t efl_lld_sect2[STM32_FLASH2_SECTORS_TOTAL] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
{ 4 * 16384 + 65536, 131072}, /* Sector 5. */
{ 4 * 16384 + 65536 + 1 * 131072, 131072}, /* Sector 6. */
{ 4 * 16384 + 65536 + 2 * 131072, 131072}, /* Sector 7. */
{ 4 * 16384 + 65536 + 3 * 131072, 131072}, /* Sector 8. */
{ 4 * 16384 + 65536 + 4 * 131072, 131072}, /* Sector 9. */
{ 4 * 16384 + 65536 + 5 * 131072, 131072}, /* Sector 10. */
{ 4 * 16384 + 65536 + 6 * 131072, 131072} /* Sector 11. */
};
/* The descriptors for 1.5M device. */
static const flash_descriptor_t efl_lld_size1[STM32_FLASH_NUMBER_OF_BANKS] = {
{ /* Single bank organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH1_SECTORS_TOTAL,
.sectors = efl_lld_sect1,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH1_SIZE * STM32_FLASH_SIZE_SCALE
}
};
/* The descriptors for 1M device. */
static const flash_descriptor_t efl_lld_size2[STM32_FLASH_NUMBER_OF_BANKS] = {
{ /* Single bank organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH2_SECTORS_TOTAL,
.sectors = efl_lld_sect2,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH2_SIZE * STM32_FLASH_SIZE_SCALE
}
};
/* Table describing possible flash sizes and descriptors for this device. */
static const efl_lld_size_t efl_lld_flash_sizes[] = {
{
.desc = efl_lld_size1
},
{
.desc = efl_lld_size2
}
};
#elif defined(STM32F401xx) || defined(STM32F411xx) || \
/* TODO: add and use Artery defines */
#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
defined(__DOXYGEN__)
/* Sector table for 128k device. */
static const flash_sector_descriptor_t efl_lld_sect1[STM32_FLASH1_SECTORS_TOTAL] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
};
/* Sector table for 256k device. */
static const flash_sector_descriptor_t efl_lld_sect2[STM32_FLASH2_SECTORS_TOTAL] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
{ 4 * 16384 + 65536, 131072}, /* Sector 5. */
};
/* Sector table for 384k device. */
static const flash_sector_descriptor_t efl_lld_sect3[STM32_FLASH3_SECTORS_TOTAL] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
{ 4 * 16384 + 65536, 131072}, /* Sector 5. */
{ 4 * 16384 + 65536 + 1 * 131072, 131072}, /* Sector 6. */
};
/* Sector table for 512k device. */
static const flash_sector_descriptor_t efl_lld_sect4[STM32_FLASH4_SECTORS_TOTAL] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
{ 4 * 16384 + 65536, 131072}, /* Sector 5. */
{ 4 * 16384 + 65536 + 1 * 131072, 131072}, /* Sector 6. */
{ 4 * 16384 + 65536 + 2 * 131072, 131072}, /* Sector 7. */
};
/* The descriptors for 128k device. */
static const flash_descriptor_t efl_lld_size1[STM32_FLASH_NUMBER_OF_BANKS] = {
{ /* Single bank organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH1_SECTORS_TOTAL,
.sectors = efl_lld_sect1,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH1_SIZE * STM32_FLASH_SIZE_SCALE
}
};
/* The descriptors for 256k device. */
static const flash_descriptor_t efl_lld_size2[STM32_FLASH_NUMBER_OF_BANKS] = {
{ /* Single bank organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH2_SECTORS_TOTAL,
.sectors = efl_lld_sect2,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH2_SIZE * STM32_FLASH_SIZE_SCALE
}
};
/* The descriptors for 384k device. */
static const flash_descriptor_t efl_lld_size3[STM32_FLASH_NUMBER_OF_BANKS] = {
{ /* Single bank organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH3_SECTORS_TOTAL,
.sectors = efl_lld_sect3,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH3_SIZE * STM32_FLASH_SIZE_SCALE
}
};
/* The descriptors for 512k device. */
static const flash_descriptor_t efl_lld_size4[STM32_FLASH_NUMBER_OF_BANKS] = {
{ /* Single bank organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH4_SECTORS_TOTAL,
.sectors = efl_lld_sect4,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH4_SIZE * STM32_FLASH_SIZE_SCALE
}
};
/* Table describing possible flash sizes and descriptors for this device. */
static const efl_lld_size_t efl_lld_flash_sizes[] = {
{
.desc = efl_lld_size1
},
{
.desc = efl_lld_size2
},
{
.desc = efl_lld_size3
},
{
.desc = efl_lld_size4
}
};
#elif defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
defined(__DOXYGEN__)
/* Sector table for 1M device in SBM. */
static const flash_sector_descriptor_t efl_lld_sect_1m_sbm[STM32_FLASH_SECTORS_TOTAL_1M_SBM] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
{ 4 * 16384 + 1 * 65536, 131072}, /* Sector 5. */
{ 4 * 16384 + 1 * 65536 + 1 * 131072, 131072}, /* Sector 6. */
{ 4 * 16384 + 1 * 65536 + 2 * 131072, 131072}, /* Sector 7. */
{ 4 * 16384 + 1 * 65536 + 3 * 131072, 131072}, /* Sector 8. */
{ 4 * 16384 + 1 * 65536 + 4 * 131072, 131072}, /* Sector 9. */
{ 4 * 16384 + 1 * 65536 + 5 * 131072, 131072}, /* Sector 10. */
{ 4 * 16384 + 1 * 65536 + 6 * 131072, 131072} /* Sector 11. */
};
/* Sector table for 1M device in DBM. */
static const flash_sector_descriptor_t efl_lld_sect_1m_dbm[STM32_FLASH_SECTORS_TOTAL_1M_DBM] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
{ 4 * 16384 + 1 * 65536, 131072}, /* Sector 5. */
{ 4 * 16384 + 1 * 65536 + 1 * 131072, 131072}, /* Sector 6. */
{ 4 * 16384 + 1 * 65536 + 2 * 131072, 131072}, /* Sector 7. */
{ 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */
{ 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */
{ 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */
{ 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */
{ 4 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 12. */
{ 5 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 13. */
{ 6 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 14. */
{ 7 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 15. */
{ 8 * 16384 + 1 * 65536 + 3 * 131072, 65536}, /* Sector 16. */
{ 8 * 16384 + 2 * 65536 + 3 * 131072, 131072}, /* Sector 17. */
{ 8 * 16384 + 2 * 65536 + 4 * 131072, 131072}, /* Sector 18. */
{ 8 * 16384 + 2 * 65536 + 5 * 131072, 131072} /* Sector 19. */
};
/* Sector table for 2M device banks. */
static const flash_sector_descriptor_t efl_lld_sect_2m[STM32_FLASH_SECTORS_TOTAL_2M] = {
{ 0, 16384}, /* Sector 0. */
{ 1 * 16384, 16384}, /* Sector 1. */
{ 2 * 16384, 16384}, /* Sector 2. */
{ 3 * 16384, 16384}, /* Sector 3. */
{ 4 * 16384, 65536}, /* Sector 4. */
{ 4 * 16384 + 1 * 65536, 131072}, /* Sector 5. */
{ 4 * 16384 + 1 * 65536 + 1 * 131072, 131072}, /* Sector 6. */
{ 4 * 16384 + 1 * 65536 + 2 * 131072, 131072}, /* Sector 7. */
{ 4 * 16384 + 1 * 65536 + 3 * 131072, 131072}, /* Sector 8. */
{ 4 * 16384 + 1 * 65536 + 4 * 131072, 131072}, /* Sector 9. */
{ 4 * 16384 + 1 * 65536 + 5 * 131072, 131072}, /* Sector 10. */
{ 4 * 16384 + 1 * 65536 + 6 * 131072, 131072}, /* Sector 11. */
{ 4 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 12. */
{ 5 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 13. */
{ 6 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 14. */
{ 7 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 15. */
{ 8 * 16384 + 1 * 65536 + 7 * 131072, 65536}, /* Sector 16. */
{ 8 * 16384 + 2 * 65536 + 7 * 131072, 131072}, /* Sector 17. */
{ 8 * 16384 + 2 * 65536 + 8 * 131072, 131072}, /* Sector 18. */
{ 8 * 16384 + 2 * 65536 + 9 * 131072, 131072}, /* Sector 19. */
{ 8 * 16384 + 2 * 65536 + 10 * 131072, 131072}, /* Sector 20. */
{ 8 * 16384 + 2 * 65536 + 11 * 131072, 131072}, /* Sector 21. */
{ 8 * 16384 + 2 * 65536 + 12 * 131072, 131072}, /* Sector 22. */
{ 8 * 16384 + 2 * 65536 + 13 * 131072, 131072} /* Sector 23. */
/* The descriptors for 4032K device. */
static const flash_descriptor_t efl_lld_size_4032k[AT32_FLASH_NUMBER_OF_BANKS] = {
{ /* Bank 1 organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = AT32_FLASH_LINE_SIZE,
.sectors_count = 32 * 16, /* 32 blocks with 16 sectors in each */
.sectors = NULL,
.sectors_size = 4096,
.address = (uint8_t *)FLASH_BASE,
.size = 32 * 16 * 4096,
},
{ /* Bank 2 organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = AT32_FLASH_LINE_SIZE,
.sectors_count = 31 * 16, /* 31 blocks with 16 sectors in each */
.sectors = NULL,
.sectors_size = 4096,
.address = (uint8_t *)(FLASH_BASE + 32 * 16 * 4096),
.size = 31 * 16 * 4096,
}
};
/* The descriptors for 1M device. */
static const flash_descriptor_t efl_lld_size_1m[STM32_FLASH_NUMBER_OF_BANKS] = {
{ /* Bank 1 (SBM) organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH_SECTORS_TOTAL_1M_SBM,
.sectors = efl_lld_sect_1m_sbm,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH_SIZE_1M * STM32_FLASH_SIZE_SCALE
},
{ /* Bank 1 & 2 (DBM) organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH_SECTORS_TOTAL_1M_DBM,
.sectors = efl_lld_sect_1m_dbm,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH_SIZE_1M * STM32_FLASH_SIZE_SCALE
}
static const flash_descriptor_t efl_lld_size_1m[AT32_FLASH_NUMBER_OF_BANKS] = {
{ /* Bank 1 organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = AT32_FLASH_LINE_SIZE,
.sectors_count = 8 * 32, /* 8 blocks with 32 sectors in each */
.sectors = NULL,
.sectors_size = 2048,
.address = (uint8_t *)FLASH_BASE,
.size = 8 * 32 * 2048
},
{ /* Bank 2 organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = AT32_FLASH_LINE_SIZE,
.sectors_count = 8 * 32, /* 8 blocks with 32 sectors in each */
.sectors = NULL,
.sectors_size = 2048,
.address = (uint8_t *)(FLASH_BASE + 8 * 32 * 2048),
.size = 8 * 32 * 2048
}
};
/* The descriptors for 2M device. */
static const flash_descriptor_t efl_lld_size_2m[STM32_FLASH_NUMBER_OF_BANKS] = {
{ /* Dual bank organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH_SECTORS_TOTAL_2M,
.sectors = efl_lld_sect_2m,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH_SIZE_2M * STM32_FLASH_SIZE_SCALE
},
{ /* Dual bank organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH_SECTORS_TOTAL_2M,
.sectors = efl_lld_sect_2m,
.sectors_size = 0,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH_SIZE_2M * STM32_FLASH_SIZE_SCALE
}
/* The descriptors for 448K device. */
static const flash_descriptor_t efl_lld_size_448k[AT32_FLASH_NUMBER_OF_BANKS] = {
{ /* Bank 1 organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = AT32_FLASH_LINE_SIZE,
.sectors_count = 7 * 16, /* 7 blocks with 16 sectors in each */
.sectors = NULL,
.sectors_size = 4096,
.address = (uint8_t *)FLASH_BASE,
.size = 7 * 16 * 4096,
},
{ /* Single bank */
.size = 0,
}
};
/* The descriptors for 256K device. */
static const flash_descriptor_t efl_lld_size_256k[AT32_FLASH_NUMBER_OF_BANKS] = {
{ /* Bank 1 organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = AT32_FLASH_LINE_SIZE,
.sectors_count = 4 * 32, /* 7 blocks with 16 sectors in each */
.sectors = NULL,
.sectors_size = 2048,
.address = (uint8_t *)FLASH_BASE,
.size = 4 * 32 * 2048
},
{ /* Single bank */
.size = 0,
}
};
/* Table describing possible flash sizes and descriptors for this device. */
static const efl_lld_size_t efl_lld_flash_sizes[] = {
{
.desc = efl_lld_size_1m
},
{
.desc = efl_lld_size_2m
}
{
.desc = efl_lld_size_4032k
},
{
.desc = efl_lld_size_1m
},
{
.desc = efl_lld_size_448k
},
{
.desc = efl_lld_size_256k
}
};
#else
#error "This EFL driver does not support the selected device"
@ -393,72 +175,59 @@ static const efl_lld_size_t efl_lld_flash_sizes[] = {
/* Driver local functions. */
/*===========================================================================*/
static inline void stm32_flash_lock(EFlashDriver *eflp) {
static inline void at32_flash_lock(EFlashDriver *eflp) {
eflp->flash->CR |= FLASH_CR_LOCK;
eflp->flash->CTRL |= FLASH_CTRL_LOCK;
}
static inline void stm32_flash_unlock(EFlashDriver *eflp) {
static inline void at32_flash_unlock(EFlashDriver *eflp) {
eflp->flash->KEYR |= FLASH_KEY1;
eflp->flash->KEYR |= FLASH_KEY2;
}
static inline void stm32_flash_enable_pgm(EFlashDriver *eflp) {
/* Set parallelism. */
eflp->flash->CR &= ~FLASH_CR_PSIZE;
eflp->flash->CR |= STM32_FLASH_PSIZE << FLASH_CR_PSIZE_Pos;
static inline void at32_flash_enable_pgm(EFlashDriver *eflp) {
/* Enable programming. */
eflp->flash->CR |= FLASH_CR_PG;
eflp->flash->CTRL |= FLASH_CTRL_PRGM;
}
static inline void stm32_flash_disable_pgm(EFlashDriver *eflp) {
static inline void at32_flash_disable_pgm(EFlashDriver *eflp) {
eflp->flash->CR &= ~FLASH_CR_PG;
eflp->flash->CTRL &= ~FLASH_CTRL_PRGM;
}
static inline void stm32_flash_clear_status(EFlashDriver *eflp) {
static inline void at32_flash_clear_status(EFlashDriver *eflp) {
eflp->flash->SR = 0x0000FFFFU;
eflp->flash->STS = (FLASH_STS_PRGMERR | FLASH_STS_EPPERR | FLASH_STS_ODF);
}
static inline void stm32_flash_wait_busy(EFlashDriver *eflp) {
static inline void at32_flash_wait_busy(EFlashDriver *eflp) {
/* Wait for busy bit clear.*/
while ((eflp->flash->SR & FLASH_SR_BSY) != 0U) {
while ((eflp->flash->STS & FLASH_STS_OBF) != 0U) {
}
}
static inline size_t stm32_flash_get_size(void) {
return *(uint16_t*)((uint32_t) STM32_FLASH_SIZE_REGISTER) * STM32_FLASH_SIZE_SCALE;
static inline size_t at32_flash_get_size(void) {
return (*(uint32_t*)(AT32_FLASH_SIZE_REGISTER)) * AT32_FLASH_SIZE_SCALE;
}
static inline bool stm32_flash_dual_bank(EFlashDriver *eflp) {
#if STM32_FLASH_NUMBER_OF_BANKS > 1
return ((eflp->flash->OPTCR & FLASH_OPTCR_DB1M) != 0U || STM32_FLASH_DUAL_BANK_PERMANENT);
#endif
(void)eflp;
return false;
}
static inline flash_error_t stm32_flash_check_errors(EFlashDriver *eflp) {
uint32_t sr = eflp->flash->SR;
static inline flash_error_t at32_flash_check_errors(EFlashDriver *eflp) {
uint32_t sr = eflp->flash->STS;
/* Clearing error conditions.*/
eflp->flash->SR = sr & 0x0000FFFFU;
eflp->flash->STS = sr & (FLASH_STS_PRGMERR | FLASH_STS_EPPERR);
/* Some errors are only caught by assertion.*/
osalDbgAssert((sr & 0) == 0U, "unexpected flash error");
/* Decoding relevant errors.*/
if ((sr & FLASH_SR_WRPERR) != 0U) {
if ((sr & FLASH_STS_PRGMERR) != 0U) {
return FLASH_ERROR_HW_FAILURE;
}
if ((sr & (FLASH_SR_PGAERR | FLASH_SR_PGPERR | FLASH_SR_OPERR)) != 0U) {
if ((sr & FLASH_STS_EPPERR) != 0U) {
return eflp->state == FLASH_PGM ? FLASH_ERROR_PROGRAM : FLASH_ERROR_ERASE;
}
@ -482,15 +251,21 @@ void efl_lld_init(void) {
/* Driver initialization.*/
eflObjectInit(&EFLD1);
EFLD1.flash = FLASH;
eflObjectInit(&EFLD2);
EFLD1.flash = FLASH1;
/* Find the size of the flash and set descriptor reference. */
uint8_t i;
for (i = 0; i < (sizeof(efl_lld_flash_sizes) / sizeof(efl_lld_size_t)); i++) {
if (efl_lld_flash_sizes[i].desc->size == stm32_flash_get_size()) {
EFLD1.descriptor = efl_lld_flash_sizes[i].desc;
if (stm32_flash_dual_bank(&EFLD1)) {
/* Point to the dual bank descriptor. */
EFLD1.descriptor++;
if (efl_lld_flash_sizes[i].desc[0].size + efl_lld_flash_sizes[i].desc[1].size ==
at32_flash_get_size()) {
EFLD1.descriptor = &efl_lld_flash_sizes[i].desc[0];
if (efl_lld_flash_sizes[i].desc[1].size) {
/* We have second bank! */
EFLD2.descriptor = &efl_lld_flash_sizes[i].desc[1];
EFLD2.flash = FLASH2;
} else {
EFLD2.descriptor = NULL;
EFLD2.flash = NULL;
}
return;
}
@ -506,8 +281,8 @@ void efl_lld_init(void) {
* @notapi
*/
void efl_lld_start(EFlashDriver *eflp) {
stm32_flash_unlock(eflp);
FLASH->CR = 0x00000000U;
at32_flash_unlock(eflp);
eflp->flash->CTRL = 0x00000000U;
}
/**
@ -519,7 +294,7 @@ void efl_lld_start(EFlashDriver *eflp) {
*/
void efl_lld_stop(EFlashDriver *eflp) {
stm32_flash_lock(eflp);
at32_flash_lock(eflp);
}
/**
@ -560,6 +335,7 @@ flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U));
const flash_descriptor_t *bank = efl_lld_get_descriptor(instance);
osalDbgCheck(bank != NULL);
osalDbgCheck((size_t)offset + n <= (size_t)bank->size);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
@ -573,19 +349,12 @@ flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
devp->state = FLASH_READ;
/* Clearing error status bits.*/
stm32_flash_clear_status(devp);
at32_flash_clear_status(devp);
/* Actual read implementation.*/
memcpy((void *)rp, (const void *)efl_lld_get_descriptor(instance)->address
+ offset, n);
#if defined(FLASH_CR_RDERR)
/* Checking for errors after reading.*/
if ((devp->flash->SR & FLASH_SR_RDERR) != 0U) {
err = FLASH_ERROR_READ;
}
#endif
/* Ready state again.*/
devp->state = FLASH_READY;
@ -614,10 +383,12 @@ flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
size_t n, const uint8_t *pp) {
EFlashDriver *devp = (EFlashDriver *)instance;
const flash_descriptor_t *bank = efl_lld_get_descriptor(instance);
const flash_descriptor_t *bank;
flash_error_t err = FLASH_NO_ERROR;
osalDbgCheck((instance != NULL) && (pp != NULL) && (n > 0U));
bank = efl_lld_get_descriptor(instance);
osalDbgCheck(bank != NULL);
osalDbgCheck((size_t)offset + n <= (size_t)bank->size);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
@ -631,10 +402,10 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
devp->state = FLASH_PGM;
/* Clearing error status bits.*/
stm32_flash_clear_status(devp);
at32_flash_clear_status(devp);
/* Enabling PGM mode in the controller.*/
stm32_flash_enable_pgm(devp);
at32_flash_enable_pgm(devp);
/* Actual program implementation.*/
while (n > 0U) {
@ -642,9 +413,9 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
/* Create an array of sufficient size to hold line(s). */
union {
uint32_t w[STM32_FLASH_LINE_SIZE / sizeof(uint32_t)];
uint16_t h[STM32_FLASH_LINE_SIZE / sizeof(uint16_t)];
uint8_t b[STM32_FLASH_LINE_SIZE / sizeof(uint8_t)];
uint32_t w[AT32_FLASH_LINE_SIZE / sizeof(uint32_t)];
uint16_t h[AT32_FLASH_LINE_SIZE / sizeof(uint16_t)];
uint8_t b[AT32_FLASH_LINE_SIZE / sizeof(uint8_t)];
} line;
/* Unwritten bytes are initialized to all ones.*/
@ -655,19 +426,19 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
/* Programming address aligned to flash lines.*/
address = (volatile uint32_t *)(bank->address +
(offset & ~STM32_FLASH_LINE_MASK));
(offset & ~AT32_FLASH_LINE_MASK));
/* Copying data inside the prepared line(s).*/
do {
line.b[offset & STM32_FLASH_LINE_MASK] = *pp;
line.b[offset & AT32_FLASH_LINE_MASK] = *pp;
offset++;
n--;
pp++;
}
while ((n > 0U) & ((offset & STM32_FLASH_LINE_MASK) != 0U));
while ((n > 0U) & ((offset & AT32_FLASH_LINE_MASK) != 0U));
/* Programming line according to parallelism.*/
switch (STM32_FLASH_LINE_SIZE) {
switch (AT32_FLASH_LINE_SIZE) {
case 1:
address[0] = line.b[0];
break;
@ -690,15 +461,15 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
break;
}
stm32_flash_wait_busy(devp);
err = stm32_flash_check_errors(devp);
at32_flash_wait_busy(devp);
err = at32_flash_check_errors(devp);
if (err != FLASH_NO_ERROR) {
break;
}
}
/* Disabling PGM mode in the controller.*/
stm32_flash_disable_pgm(devp);
at32_flash_disable_pgm(devp);
/* Ready state again.*/
devp->state = FLASH_READY;
@ -733,32 +504,18 @@ flash_error_t efl_lld_start_erase_all(void *instance) {
return FLASH_BUSY_ERASING;
}
#if defined(FLASH_CR_MER2)
/* If dual bank is active then mass erase bank2. */
if (stm32_flash_dual_bank(devp)) {
/* FLASH_ERASE state while the operation is performed.*/
devp->state = FLASH_ERASE;
/* FLASH_ERASE state while the operation is performed.*/
devp->state = FLASH_ERASE;
/* Clearing error status bits.*/
at32_flash_clear_status(devp);
/* Clearing error status bits.*/
stm32_flash_clear_status(devp);
/* Bank erase */
devp->flash->CTRL |= FLASH_CTRL_BANKERS;
/* Start */
devp->flash->CTRL |= FLASH_CTRL_ERSTR;
/* Erase the currently unused bank, based on Flash Bank Mode */
if ((SYSCFG->MEMRMP & SYSCFG_MEMRMP_UFB_MODE) != 0U) {
/* Bank 2 in use, erase Bank 1 */
devp->flash->CR |= FLASH_CR_MER;
}
else {
/* Bank 1 in use, erase Bank 2 */
devp->flash->CR |= FLASH_CR_MER2;
}
devp->flash->CR |= FLASH_CR_STRT;
return FLASH_NO_ERROR;
}
#endif
/* Mass erase not allowed. */
return FLASH_ERROR_UNIMPLEMENTED;
return FLASH_NO_ERROR;
}
/**
@ -779,7 +536,7 @@ flash_error_t efl_lld_start_erase_sector(void *instance,
flash_sector_t sector) {
EFlashDriver *devp = (EFlashDriver *)instance;
const flash_descriptor_t *bank = efl_lld_get_descriptor(instance);
osalDbgCheck(instance != NULL);
osalDbgCheck(bank != NULL);
osalDbgCheck(sector < bank->sectors_count);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
@ -793,32 +550,17 @@ flash_error_t efl_lld_start_erase_sector(void *instance,
devp->state = FLASH_ERASE;
/* Clearing error status bits.*/
stm32_flash_clear_status(devp);
at32_flash_clear_status(devp);
/* Write the sector to be erased in the FLASH_ADDRx register; */
devp->flash->ADDR = (flash_offset_t)bank->address +
flashGetSectorOffset(getBaseFlash(devp), sector);
/* Enable sector erase.*/
devp->flash->CR |= FLASH_CR_SER;
/* Mask off the sector and parallelism selection bits.*/
devp->flash->CR &= ~FLASH_CR_SNB;
devp->flash->CR &= ~FLASH_CR_PSIZE;
#if defined(FLASH_CR_MER2)
/* Adjust sector value for dual-bank devices
* For STM32F42x_43x devices (dual-bank), FLASH_CR_SNB values jump to 0b10000
* for sectors 12 and up.
*/
if (sector >= 12) {
sector -= 12;
sector |= 0x10U;
}
#endif
/* Set sector and parallelism. */
devp->flash->CR |= (sector << FLASH_CR_SNB_Pos) |
(STM32_FLASH_PSIZE << FLASH_CR_PSIZE_Pos);
devp->flash->CTRL |= FLASH_CTRL_SECERS;
/* Start the erase.*/
devp->flash->CR |= FLASH_CR_STRT;
devp->flash->CTRL |= FLASH_CTRL_ERSTR;
return FLASH_NO_ERROR;
}
@ -846,17 +588,15 @@ flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) {
if (devp->state == FLASH_ERASE) {
/* Checking for operation in progress.*/
if ((devp->flash->SR & FLASH_SR_BSY) == 0U) {
if ((devp->flash->STS & FLASH_STS_OBF) == 0U) {
/* Disabling the various erase control bits.*/
devp->flash->CR &= ~(FLASH_CR_MER |
#if defined(FLASH_CR_MER2)
FLASH_CR_MER2 |
#endif
FLASH_CR_SER);
devp->flash->CTRL &= ~(FLASH_CTRL_SECERS |
FLASH_CTRL_BLKERS |
FLASH_CTRL_BANKERS);
/* No operation in progress, checking for errors.*/
err = stm32_flash_check_errors(devp);
err = at32_flash_check_errors(devp);
/* Back to ready state.*/
devp->state = FLASH_READY;
@ -865,7 +605,7 @@ flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) {
/* Recommended time before polling again. This is a simplified
implementation.*/
if (msec != NULL) {
*msec = (uint32_t)STM32_FLASH_WAIT_TIME_MS;
*msec = (uint32_t)AT32_FLASH_WAIT_TIME_MS;
}
err = FLASH_BUSY_ERASING;
@ -894,11 +634,13 @@ flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) {
flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) {
EFlashDriver *devp = (EFlashDriver *)instance;
uint32_t *address;
const flash_descriptor_t *bank = efl_lld_get_descriptor(instance);
const flash_descriptor_t *bank;
flash_error_t err = FLASH_NO_ERROR;
unsigned i;
osalDbgCheck(instance != NULL);
bank = efl_lld_get_descriptor(instance);
osalDbgCheck(bank != NULL);
osalDbgCheck(sector < bank->sectors_count);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");

72
os/hal/ports/AT32/AT32F4xx/hal_efl_lld.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
ChibiOS - Copyright (C) 2023 Andrey Gusakov
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -16,7 +16,7 @@
/**
* @file hal_efl_lld.h
* @brief STM32F4xx Embedded Flash subsystem low level driver header.
* @brief AT32F43X Embedded Flash subsystem low level driver header.
*
* @addtogroup HAL_EFL
* @{
@ -36,14 +36,14 @@
/*===========================================================================*/
/**
* @name STM32F412/413 EFL driver configuration options
* @name AT32F435/437 EFL driver configuration options
* @{
*/
/**
* @brief Suggested wait time during erase operations polling.
*/
#if !defined(STM32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__)
#define STM32_FLASH_WAIT_TIME_MS 5
#if !defined(AT32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__)
#define AT32_FLASH_WAIT_TIME_MS 5
#endif
/** @} */
@ -51,67 +51,16 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if defined(STM32F413xx) || defined(STM32F412xx) || \
defined(STM32F40_41xxx) || defined(__DOXYGEN__)
/* Flash size register. */
#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22
#define STM32_FLASH_SIZE_SCALE 1024U
/*
* Device flash size...
*
*/
#define STM32_FLASH_NUMBER_OF_BANKS 1
#define STM32_FLASH1_SIZE 1536U
#define STM32_FLASH2_SIZE 1024U
#define STM32_FLASH1_SECTORS_TOTAL 16
#define STM32_FLASH2_SECTORS_TOTAL 12
#elif defined(STM32F401xx) || defined(STM32F411xx) || \
/* TODO: add and use Artery defines */
#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
defined(__DOXYGEN__)
/* Flash size register. */
#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22
#define STM32_FLASH_SIZE_SCALE 1024U
#define AT32_FLASH_SIZE_REGISTER 0x1FFFF7E0
#define AT32_FLASH_SIZE_SCALE 1024U
/*
* Device flash size...
*
*/
#define STM32_FLASH_NUMBER_OF_BANKS 1
#define STM32_FLASH1_SIZE 128U
#define STM32_FLASH2_SIZE 512U
#define STM32_FLASH3_SIZE 384U
#define STM32_FLASH4_SIZE 512U
#define STM32_FLASH1_SECTORS_TOTAL 5
#define STM32_FLASH2_SECTORS_TOTAL 6
#define STM32_FLASH3_SECTORS_TOTAL 7
#define STM32_FLASH4_SECTORS_TOTAL 8
#define AT32_FLASH_NUMBER_OF_BANKS 2
#elif defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
defined(__DOXYGEN__)
/* Flash size register. */
#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22
#define STM32_FLASH_SIZE_SCALE 1024U
/*
* Device flash size is:
* 1M for STM32F4x7/4x9 suffix G devices
* 2M for STM32F4x7/4x9 suffix I devices.
*
* For 1M devices SBM is organised as 16K x 4 + 64K + 128K x 7 sectors.
* For 1M devices DBM is organised as 16K x 4 + 64K + 128K x 3 sectors per bank.
*
* For 2M devices are organised as 16K x 4 + 64K + 128K x 7 sectors per bank.
*/
#define STM32_FLASH_NUMBER_OF_BANKS 2
#define STM32_FLASH_SIZE_1M 1024U
#define STM32_FLASH_SIZE_2M 2048U
#define STM32_FLASH_SECTORS_TOTAL_1M_SBM 12
#define STM32_FLASH_SECTORS_TOTAL_1M_DBM 20
#define STM32_FLASH_SECTORS_TOTAL_2M 24
#else
#error "This EFL driver does not support the selected device"
#endif
@ -150,6 +99,7 @@ typedef struct {
#if !defined(__DOXYGEN__)
extern EFlashDriver EFLD1;
extern EFlashDriver EFLD2;
#endif
#ifdef __cplusplus

4
os/hal/ports/AT32/AT32F4xx/hal_lld_type1.h
View File

@ -812,7 +812,6 @@
#define STM32_6WS_THRESHOLD 0
#define STM32_7WS_THRESHOLD 0
#define STM32_8WS_THRESHOLD 0
#define STM32_FLASH_PSIZE 2
#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
#define STM32_0WS_THRESHOLD 24000000
#define STM32_1WS_THRESHOLD 48000000
@ -823,7 +822,6 @@
#define STM32_6WS_THRESHOLD 168000000
#define STM32_7WS_THRESHOLD 180000000
#define STM32_8WS_THRESHOLD 0
#define STM32_FLASH_PSIZE 1
#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
#define STM32_0WS_THRESHOLD 22000000
#define STM32_1WS_THRESHOLD 44000000
@ -834,7 +832,6 @@
#define STM32_6WS_THRESHOLD 154000000
#define STM32_7WS_THRESHOLD 176000000
#define STM32_8WS_THRESHOLD 180000000
#define STM32_FLASH_PSIZE 1
#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
#define STM32_0WS_THRESHOLD 20000000
#define STM32_1WS_THRESHOLD 40000000
@ -845,7 +842,6 @@
#define STM32_6WS_THRESHOLD 140000000
#define STM32_7WS_THRESHOLD 168000000
#define STM32_8WS_THRESHOLD 0
#define STM32_FLASH_PSIZE 0
#else
#error "invalid VDD voltage specified"
#endif

2
testhal/STM32/multi/EFL-MFS/Makefile
View File

@ -6,12 +6,14 @@ all:
@echo
@echo === Building for STM32L476-Discovery ===============================
+@make --no-print-directory -f ./make/stm32l476_discovery.make all
+@make --no-print-directory -f ./make/at32f435_start.make all
@echo ====================================================================
@echo
clean:
@echo
+@make --no-print-directory -f ./make/stm32l476_discovery.make clean
+@make --no-print-directory -f ./make/at32f435_start.make clean
@echo
#

759
testhal/STM32/multi/EFL-MFS/cfg/at32f435_start/chconf.h Normal file
View File

@ -0,0 +1,759 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file rt/templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef CHCONF_H
#define CHCONF_H
#define _CHIBIOS_RT_CONF_
#define _CHIBIOS_RT_CONF_VER_6_1_
#define ON_LOCK_HOOK {}
#define ON_UNLOCK_HOOK {}
/*===========================================================================*/
/**
* @name System timers settings
* @{
*/
/*===========================================================================*/
/**
* @brief System time counter resolution.
* @note Allowed values are 16, 32 or 64 bits.
*/
#if !defined(CH_CFG_ST_RESOLUTION)
#define CH_CFG_ST_RESOLUTION 32
#endif
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_CFG_ST_FREQUENCY)
#define CH_CFG_ST_FREQUENCY 10000
#endif
/**
* @brief Time intervals data size.
* @note Allowed values are 16, 32 or 64 bits.
*/
#if !defined(CH_CFG_INTERVALS_SIZE)
#define CH_CFG_INTERVALS_SIZE 32
#endif
/**
* @brief Time types data size.
* @note Allowed values are 16 or 32 bits.
*/
#if !defined(CH_CFG_TIME_TYPES_SIZE)
#define CH_CFG_TIME_TYPES_SIZE 32
#endif
/**
* @brief Time delta constant for the tick-less mode.
* @note If this value is zero then the system uses the classic
* periodic tick. This value represents the minimum number
* of ticks that is safe to specify in a timeout directive.
* The value one is not valid, timeouts are rounded up to
* this value.
*/
#if !defined(CH_CFG_ST_TIMEDELTA)
#define CH_CFG_ST_TIMEDELTA 2
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
* @note The round robin preemption is not supported in tickless mode and
* must be set to zero in that case.
*/
#if !defined(CH_CFG_TIME_QUANTUM)
#define CH_CFG_TIME_QUANTUM 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread. The application @p main()
* function becomes the idle thread and must implement an
* infinite loop.
*/
#if !defined(CH_CFG_NO_IDLE_THREAD)
#define CH_CFG_NO_IDLE_THREAD FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_OPTIMIZE_SPEED)
#define CH_CFG_OPTIMIZE_SPEED TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Time Measurement APIs.
* @details If enabled then the time measurement APIs are included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_TM)
#define CH_CFG_USE_TM TRUE
#endif
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_REGISTRY)
#define CH_CFG_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_WAITEXIT)
#define CH_CFG_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_SEMAPHORES)
#define CH_CFG_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special
* requirements.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)
#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MUTEXES)
#define CH_CFG_USE_MUTEXES TRUE
#endif
/**
* @brief Enables recursive behavior on mutexes.
* @note Recursive mutexes are heavier and have an increased
* memory footprint.
*
* @note The default is @p FALSE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)
#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
#endif
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
#if !defined(CH_CFG_USE_CONDVARS)
#define CH_CFG_USE_CONDVARS TRUE
#endif
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_CONDVARS.
*/
#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)
#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_EVENTS)
#define CH_CFG_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_EVENTS.
*/
#if !defined(CH_CFG_USE_EVENTS_TIMEOUT)
#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MESSAGES)
#define CH_CFG_USE_MESSAGES TRUE
#endif
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special
* requirements.
* @note Requires @p CH_CFG_USE_MESSAGES.
*/
#if !defined(CH_CFG_USE_MESSAGES_PRIORITY)
#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/
#if !defined(CH_CFG_USE_DYNAMIC)
#define CH_CFG_USE_DYNAMIC TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name OSLIB options
* @{
*/
/*===========================================================================*/
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#if !defined(CH_CFG_USE_MAILBOXES)
#define CH_CFG_USE_MAILBOXES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MEMCORE)
#define CH_CFG_USE_MEMCORE TRUE
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_CFG_USE_MEMCORE.
*/
#if !defined(CH_CFG_MEMCORE_SIZE)
#define CH_CFG_MEMCORE_SIZE 0
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
* @p CH_CFG_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#if !defined(CH_CFG_USE_HEAP)
#define CH_CFG_USE_HEAP TRUE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MEMPOOLS)
#define CH_CFG_USE_MEMPOOLS TRUE
#endif
/**
* @brief Objects FIFOs APIs.
* @details If enabled then the objects FIFOs APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_FIFOS)
#define CH_CFG_USE_OBJ_FIFOS TRUE
#endif
/**
* @brief Pipes APIs.
* @details If enabled then the pipes APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_PIPES)
#define CH_CFG_USE_PIPES TRUE
#endif
/**
* @brief Objects Caches APIs.
* @details If enabled then the objects caches APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_CACHES)
#define CH_CFG_USE_OBJ_CACHES TRUE
#endif
/**
* @brief Delegate threads APIs.
* @details If enabled then the delegate threads APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_DELEGATES)
#define CH_CFG_USE_DELEGATES TRUE
#endif
/**
* @brief Jobs Queues APIs.
* @details If enabled then the jobs queues APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_JOBS)
#define CH_CFG_USE_JOBS TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Objects factory options
* @{
*/
/*===========================================================================*/
/**
* @brief Objects Factory APIs.
* @details If enabled then the objects factory APIs are included in the
* kernel.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_CFG_USE_FACTORY)
#define CH_CFG_USE_FACTORY TRUE
#endif
/**
* @brief Maximum length for object names.
* @details If the specified length is zero then the name is stored by
* pointer but this could have unintended side effects.
*/
#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
#endif
/**
* @brief Enables the registry of generic objects.
*/
#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
#endif
/**
* @brief Enables factory for generic buffers.
*/
#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
#endif
/**
* @brief Enables factory for semaphores.
*/
#if !defined(CH_CFG_FACTORY_SEMAPHORES)
#define CH_CFG_FACTORY_SEMAPHORES TRUE
#endif
/**
* @brief Enables factory for mailboxes.
*/
#if !defined(CH_CFG_FACTORY_MAILBOXES)
#define CH_CFG_FACTORY_MAILBOXES TRUE
#endif
/**
* @brief Enables factory for objects FIFOs.
*/
#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
#endif
/**
* @brief Enables factory for Pipes.
*/
#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)
#define CH_CFG_FACTORY_PIPES TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, kernel statistics.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_STATISTICS)
#define CH_DBG_STATISTICS FALSE
#endif
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK)
#define CH_DBG_SYSTEM_STATE_CHECK TRUE
#endif
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS)
#define CH_DBG_ENABLE_CHECKS TRUE
#endif
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS)
#define CH_DBG_ENABLE_ASSERTS TRUE
#endif
/**
* @brief Debug option, trace buffer.
* @details If enabled then the trace buffer is activated.
*
* @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
*/
#if !defined(CH_DBG_TRACE_MASK)
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
#endif
/**
* @brief Trace buffer entries.
* @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
* different from @p CH_DBG_TRACE_MASK_DISABLED.
*/
#if !defined(CH_DBG_TRACE_BUFFER_SIZE)
#define CH_DBG_TRACE_BUFFER_SIZE 128
#endif
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS)
#define CH_DBG_FILL_THREADS FALSE
#endif
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p thread_t structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p FALSE.
* @note This debug option is not currently compatible with the
* tickless mode.
*/
#if !defined(CH_DBG_THREADS_PROFILING)
#define CH_DBG_THREADS_PROFILING FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief System structure extension.
* @details User fields added to the end of the @p ch_system_t structure.
*/
#define CH_CFG_SYSTEM_EXTRA_FIELDS \
/* Add threads custom fields here.*/
/**
* @brief System initialization hook.
* @details User initialization code added to the @p chSysInit() function
* just before interrupts are enabled globally.
*/
#define CH_CFG_SYSTEM_INIT_HOOK() { \
/* Add threads initialization code here.*/ \
}
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p thread_t structure.
*/
#define CH_CFG_THREAD_EXTRA_FIELDS \
/* Add threads custom fields here.*/
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p _thread_init() function.
*
* @note It is invoked from within @p _thread_init() and implicitly from all
* the threads creation APIs.
*/
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*/
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* Context switch code here.*/ \
}
/**
* @brief ISR enter hook.
*/
#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
/* IRQ prologue code here.*/ \
}
/**
* @brief ISR exit hook.
*/
#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
/* IRQ epilogue code here.*/ \
}
/**
* @brief Idle thread enter hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
#define CH_CFG_IDLE_ENTER_HOOK() { \
/* Idle-enter code here.*/ \
}
/**
* @brief Idle thread leave hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
#define CH_CFG_IDLE_LEAVE_HOOK() { \
/* Idle-leave code here.*/ \
}
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#define CH_CFG_IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#define CH_CFG_SYSTEM_TICK_HOOK() { \
/* System tick event code here.*/ \
}
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
/* System halt code here.*/ \
}
/**
* @brief Trace hook.
* @details This hook is invoked each time a new record is written in the
* trace buffer.
*/
#define CH_CFG_TRACE_HOOK(tep) { \
/* Trace code here.*/ \
}
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* CHCONF_H */
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef HALCONF_H
#define HALCONF_H
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_1_
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the cryptographic subsystem.
*/
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
#define HAL_USE_CRY FALSE
#endif
/**
* @brief Enables the DAC subsystem.
*/
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
#define HAL_USE_DAC FALSE
#endif
/**
* @brief Enables the EFlash subsystem.
*/
#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)
#define HAL_USE_EFL TRUE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the I2S subsystem.
*/
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
#define HAL_USE_I2S FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SIO subsystem.
*/
#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
#define HAL_USE_SIO FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the TRNG subsystem.
*/
#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
#define HAL_USE_TRNG FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/**
* @brief Enables the WDG subsystem.
*/
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
#define HAL_USE_WDG FALSE
#endif
/**
* @brief Enables the WSPI subsystem.
*/
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
#define HAL_USE_WSPI FALSE
#endif
/*===========================================================================*/
/* PAL driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
#define PAL_USE_CALLBACKS FALSE
#endif
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
#define PAL_USE_WAIT FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/**
* @brief Enforces the driver to use direct callbacks rather than OSAL events.
*/
#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
#define CAN_ENFORCE_USE_CALLBACKS FALSE
#endif
/*===========================================================================*/
/* CRY driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the SW fall-back of the cryptographic driver.
* @details When enabled, this option, activates a fall-back software
* implementation for algorithms not supported by the underlying
* hardware.
* @note Fall-back implementations may not be present for all algorithms.
*/
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_USE_FALLBACK FALSE
#endif
/**
* @brief Makes the driver forcibly use the fall-back implementations.
*/
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_ENFORCE_FALLBACK FALSE
#endif
/*===========================================================================*/
/* DAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
#define DAC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define DAC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the zero-copy API.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/**
* @brief OCR initialization constant for V20 cards.
*/
#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
#define SDC_INIT_OCR_V20 0x50FF8000U
#endif
/**
* @brief OCR initialization constant for non-V20 cards.
*/
#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
#define SDC_INIT_OCR 0x80100000U
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
/**
* @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
* @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#endif
/**
* @brief Serial over USB number of buffers.
* @note The default is 2 buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_NUMBER 2
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables circular transfers APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
#define SPI_USE_CIRCULAR FALSE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/**
* @brief Handling method for SPI CS line.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
#endif
/*===========================================================================*/
/* UART driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
#define UART_USE_WAIT FALSE
#endif
/**
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define UART_USE_MUTUAL_EXCLUSION FALSE
#endif
/*===========================================================================*/
/* USB driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
#define USB_USE_WAIT FALSE
#endif
/*===========================================================================*/
/* WSPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
#define WSPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* HALCONF_H */
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
#define STM32F437_MCUCONF
/*
* Config pll clock resource
* common frequency config list: pll source selected hick or hext (8mhz)
* _________________________________________________________________________________________________
* | | | | | | | | | | |
* |pll(mhz)| 288 | 252 | 216 | 192 | 180 | 144 | 108 | 72 | 36 |
* |________|_________|_________|_________|_________|_________|_________|_________|_________________|
* | | | | | | | | | | |
* |pll_ns | 144 | 126 | 108 | 96 | 90 | 72 | 108 | 72 | 72 |
* | | | | | | | | | | |
* |pll_ms | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
* | | | | | | | | | | |
* |pll_fr | FR_4 | FR_4 | FR_4 | FR_4 | FR_4 | FR_4 | FR_8 | FR_8 | FR_16|
* |________|_________|_________|_________|_________|_________|_________|_________|________|________|
*
* if pll clock source selects hext with other frequency values, or configure pll to other
* frequency values, please use the at32 new clock configuration tool for configuration.
*/
#if 0
/* Defaults for 96MHz from DS */
#define STM32_PLLM_VALUE 2
#define STM32_PLLN_VALUE 192
#define STM32_PLLP_VALUE 8
#define STM32_PPRE1 STM32_PPRE1_DIV1 /* max 144 MHz */
#define STM32_PPRE2 STM32_PPRE2_DIV1 /* max 144 MHz */
#endif
#if 0
/* 144 MHz */
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 72
#define STM32_PLLP_VALUE 4
#define STM32_PPRE1 STM32_PPRE1_DIV1 /* max 144 MHz */
#define STM32_PPRE2 STM32_PPRE2_DIV1 /* max 144 MHz */
#endif
#if 0
/* 216 MHz */
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 108
#define STM32_PLLP_VALUE 4
#define STM32_PPRE1 STM32_PPRE1_DIV2 /* max 144 MHz */
#define STM32_PPRE2 STM32_PPRE2_DIV2 /* max 144 MHz */
#endif
#if 1
/* 288 MHz */
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 144
#define STM32_PLLP_VALUE 4
#define STM32_PPRE1 STM32_PPRE1_DIV2 /* max 144 MHz */
#define STM32_PPRE2 STM32_PPRE2_DIV2 /* max 144 MHz */
#endif
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
#define STM32_IRQ_TIM8_CC_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART3_PRIORITY 12
#define STM32_IRQ_UART4_PRIORITY 12
#define STM32_IRQ_UART5_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
#define STM32_IRQ_UART7_PRIORITY 12
#define STM32_IRQ_UART8_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_USE_ADC2 TRUE
#define STM32_ADC_USE_ADC3 TRUE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM10 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM13 FALSE
#define STM32_GPT_USE_TIM14 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_USE_TIM10 FALSE
#define STM32_ICU_USE_TIM11 FALSE
#define STM32_ICU_USE_TIM12 FALSE
#define STM32_ICU_USE_TIM13 FALSE
#define STM32_ICU_USE_TIM14 FALSE
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_USE_TIM10 FALSE
#define STM32_PWM_USE_TIM11 FALSE
#define STM32_PWM_USE_TIM12 FALSE
#define STM32_PWM_USE_TIM13 FALSE
#define STM32_PWM_USE_TIM14 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SDC driver system settings.
*/
#define STM32_SDC_SDIO_DMA_PRIORITY 3
#define STM32_SDC_SDIO_IRQ_PRIORITY 9
#define STM32_SDC_WRITE_TIMEOUT_MS 1000
#define STM32_SDC_READ_TIMEOUT_MS 1000
#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 TRUE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_USE_SPI4 FALSE
#define STM32_SPI_USE_SPI5 FALSE
#define STM32_SPI_USE_SPI6 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI4_DMA_PRIORITY 1
#define STM32_SPI_SPI5_DMA_PRIORITY 1
#define STM32_SPI_SPI6_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 FALSE
#define STM32_USB_USE_OTG2 FALSE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

73
testhal/STM32/multi/EFL-MFS/cfg/at32f435_start/portab.c Normal file
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@ -0,0 +1,73 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file portab.c
* @brief Application portability module code.
*
* @addtogroup application_portability
* @{
*/
#include "hal.h"
#include "hal_mfs.h"
#include "portab.h"
/*===========================================================================*/
/* Module local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Module exported variables. */
/*===========================================================================*/
const MFSConfig mfscfg1 = {
.flashp = (BaseFlash *)&EFLD2,
.erased = 0xFFFFFFFFU,
.bank_size = 4096U,
.bank0_start = 0U,
.bank0_sectors = 2U,
.bank1_start = 2U,
.bank1_sectors = 2U
};
/*===========================================================================*/
/* Module local types. */
/*===========================================================================*/
/*===========================================================================*/
/* Module local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Module local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Module exported functions. */
/*===========================================================================*/
void portab_setup(void) {
/*
* LED line as output.
*/
palSetLineMode(LINE_LED_GREEN, PAL_MODE_OUTPUT_PUSHPULL);
}
/** @} */

78
testhal/STM32/multi/EFL-MFS/cfg/at32f435_start/portab.h Normal file
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@ -0,0 +1,78 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file portab.h
* @brief Application portability macros and structures.
*
* @addtogroup application_portability
* @{
*/
#ifndef PORTAB_H
#define PORTAB_H
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
#define PORTAB_LINE_LED1 LINE_LED_GREEN
#define PORTAB_LINE_LED2 LINE_LED_RED
#define PORTAB_LED_OFF PAL_HIGH
#define PORTAB_LED_ON PAL_LOW
#define PORTAB_LINE_BUTTON LINE_BUTTON
#define PORTAB_BUTTON_PRESSED PAL_HIGH
#define PORTAB_SD1 SD1
#define PORTAB_EFLD EFLD2
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Module data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Module macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void portab_setup(void);
#ifdef __cplusplus
}
#endif
/*===========================================================================*/
/* Module inline functions. */
/*===========================================================================*/
#endif /* PORTAB_H */
/** @} */

12
testhal/STM32/multi/EFL-MFS/cfg/stm32l476_discovery/portab.c
View File

@ -24,6 +24,8 @@
#include "hal.h"
#include "hal_mfs.h"
#include "portab.h"
/*===========================================================================*/
@ -34,6 +36,16 @@
/* Module exported variables. */
/*===========================================================================*/
const MFSConfig mfscfg1 = {
.flashp = (BaseFlash *)&EFLD1,
.erased = 0xFFFFFFFFU,
.bank_size = 4096U,
.bank0_start = 128U,
.bank0_sectors = 2U,
.bank1_start = 130U,
.bank1_sectors = 2U
};
/*===========================================================================*/
/* Module local types. */
/*===========================================================================*/

2
testhal/STM32/multi/EFL-MFS/cfg/stm32l476_discovery/portab.h
View File

@ -39,6 +39,8 @@
#define PORTAB_SD1 SD2
#define PORTAB_EFLD EFLD1
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/

12
testhal/STM32/multi/EFL-MFS/main.c
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@ -25,15 +25,7 @@
#include "portab.h"
const MFSConfig mfscfg1 = {
.flashp = (BaseFlash *)&EFLD1,
.erased = 0xFFFFFFFFU,
.bank_size = 4096U,
.bank0_start = 128U,
.bank0_sectors = 2U,
.bank1_start = 130U,
.bank1_sectors = 2U
};
extern const MFSConfig mfscfg1;
/*
* LED blinker thread, times are in milliseconds.
@ -70,7 +62,7 @@ int main(void) {
portab_setup();
/* Starting EFL driver.*/
eflStart(&EFLD1, NULL);
eflStart(&PORTAB_EFLD, NULL);
/* Starting a serial port for test report output.*/
sdStart(&PORTAB_SD1, NULL);

226
testhal/STM32/multi/EFL-MFS/make/at32f435_start.make Normal file
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@ -0,0 +1,226 @@
##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O0 -gdwarf-3 -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# Linker extra options here.
ifeq ($(USE_LDOPT),)
USE_LDOPT =
endif
# Enable this if you want link time optimizations (LTO)
ifeq ($(USE_LTO),)
USE_LTO = yes
endif
# If enabled, this option allows to compile the application in THUMB mode.
ifeq ($(USE_THUMB),)
USE_THUMB = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
# If enabled, this option makes the build process faster by not compiling
# modules not used in the current configuration.
ifeq ($(USE_SMART_BUILD),)
USE_SMART_BUILD = yes
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
# Stack size to be allocated to the Cortex-M process stack. This stack is
# the stack used by the main() thread.
ifeq ($(USE_PROCESS_STACKSIZE),)
USE_PROCESS_STACKSIZE = 0x400
endif
# Stack size to the allocated to the Cortex-M main/exceptions stack. This
# stack is used for processing interrupts and exceptions.
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
USE_EXCEPTIONS_STACKSIZE = 0x400
endif
# Enables the use of FPU (no, softfp, hard).
ifeq ($(USE_FPU),)
USE_FPU = no
endif
# FPU-related options.
ifeq ($(USE_FPU_OPT),)
USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16
endif
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, sources and paths
#
# Define project name here
PROJECT = ch
# Imported source files and paths
CHIBIOS := ../../../..
CONFDIR := ./cfg/at32f435_start
BUILDDIR := ./build/at32f435_start
DEPDIR := ./.dep/at32f435_start
# Licensing files.
include $(CHIBIOS)/os/license/license.mk
# Startup files.
include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f4xx.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/ports/AT32/AT32F4xx/platform.mk
include $(CHIBIOS)/os/hal/boards/AT_START_F435/board.mk
include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
# Auto-build files in ./source recursively.
include $(CHIBIOS)/tools/mk/autobuild.mk
# Other files (optional).
include $(CHIBIOS)/test/lib/test.mk
include $(CHIBIOS)/test/mfs/mfs_test.mk
include $(CHIBIOS)/os/hal/lib/complex/mfs/hal_mfs.mk
include $(CHIBIOS)/os/hal/lib/streams/streams.mk
# Define linker script file here
LDSCRIPT= $(STARTUPLD)/AT32F435ZMxx.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(ALLCSRC) \
$(TESTSRC) \
$(CONFDIR)/portab.c \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC = $(ALLCPPSRC)
# C sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACSRC =
# C++ sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACPPSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCPPSRC =
# List ASM source files here
ASMSRC = $(ALLASMSRC)
ASMXSRC = $(ALLXASMSRC)
INCDIR = $(ALLINC) $(TESTINC) $(CONFDIR)
#
# Project, sources and paths
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS = -DMFS_CFG_MEMORY_ALIGNMENT=8
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user section
##############################################################################
##############################################################################
# Compiler settings
#
MCU = cortex-m4
#TRGT = arm-elf-
TRGT = arm-none-eabi-
CC = $(TRGT)gcc
CPPC = $(TRGT)g++
# Enable loading with g++ only if you need C++ runtime support.
# NOTE: You can use C++ even without C++ support if you are careful. C++
# runtime support makes code size explode.
LD = $(TRGT)gcc
#LD = $(TRGT)g++
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
AR = $(TRGT)ar
OD = $(TRGT)objdump
SZ = $(TRGT)size
HEX = $(CP) -O ihex
BIN = $(CP) -O binary
# ARM-specific options here
AOPT =
# THUMB-specific options here
TOPT = -mthumb -DTHUMB
# Define C warning options here
CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
# Define C++ warning options here
CPPWARN = -Wall -Wextra -Wundef
#
# Compiler settings
##############################################################################
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk
include $(RULESPATH)/rules.mk