Fixed Bug #745

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9526 35acf78f-673a-0410-8e92-d51de3d6d3f4

os/hal/ports/STM32/STM32F4xx/hal_lld.h

@@ -432,19 +432,6 @@
 #define STM32_PLLI2SR_MASK      (7 << 28)   /**< PLLI2SR mask.              */
 /** @} */
 
-/**
- * @name    RCC_PLLSAICFGR register bits definitions
- * @{
- */
-#define STM32_SAIR_DIV2         (0 << 16)   /**< R divided by 2.            */
-#define STM32_SAIR_DIV4         (1 << 16)   /**< R divided by 4.            */
-#define STM32_SAIR_DIV8         (2 << 16)   /**< R divided by 8.            */
-#define STM32_SAIR_DIV16        (3 << 16)   /**< R divided by 16.           */
-
-#define STM32_SAISRC_NOCLOCK    (0 << 23)   /**< No clock.                  */
-#define STM32_SAISRC_PLL        (1 << 23)   /**< SAI_CKIN is PLL.           */
-/** @} */
-
 /**
  * @name    RCC_BDCR register bits definitions
  * @{
@@ -1353,21 +1340,10 @@
 #error "invalid STM32_PLLI2SR_VALUE value specified"
 #endif
 
-/*
- * PLLSAI enable check.
- */
-#if !defined(STM32_SAISRC)
-#define STM32_SAISRC                STM32_SAISRC_NOCLOCK
-#endif
-
 /**
  * @brief   PLLSAI activation flag.
  */
-#if (STM32_SAISRC == STM32_SAISRC_PLL) || defined(__DOXYGEN__)
-#define STM32_ACTIVATE_PLLSAI       TRUE
-#else
 #define STM32_ACTIVATE_PLLSAI       FALSE
-#endif
 
 /**
  * @brief   STM32_PLLSAIN field.

readme.txt

@@ -113,6 +113,7 @@
 - RT:  Merged RT4.
 - NIL: Merged NIL2.
 - NIL: Added STM32F7 demo.
+- HAL: Removed wrong SAI masks in STM32F4xx hal_lld.h (bug #745).
 - HAL: Fixed wrong mask placement in STM32F4xx hal_lld.h (bug #744).
 - HAL: Fixed wrong indent in STM32F4xx hal_lld.h (bug #743).
 - HAL: Removed unused macros in STM32F7xx and STM32F4xx hal_lld.h (bug #742).