Fixed Bug #745
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9526 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -432,19 +432,6 @@
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#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
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#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
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/** @} */
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/** @} */
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/**
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* @name RCC_PLLSAICFGR register bits definitions
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* @{
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*/
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#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
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#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
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#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
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#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
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#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
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#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
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/** @} */
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/**
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/**
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* @name RCC_BDCR register bits definitions
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* @name RCC_BDCR register bits definitions
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* @{
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* @{
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@ -1353,21 +1340,10 @@
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#error "invalid STM32_PLLI2SR_VALUE value specified"
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#error "invalid STM32_PLLI2SR_VALUE value specified"
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#endif
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#endif
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/*
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* PLLSAI enable check.
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*/
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#if !defined(STM32_SAISRC)
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#define STM32_SAISRC STM32_SAISRC_NOCLOCK
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#endif
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/**
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/**
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* @brief PLLSAI activation flag.
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* @brief PLLSAI activation flag.
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*/
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*/
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#if (STM32_SAISRC == STM32_SAISRC_PLL) || defined(__DOXYGEN__)
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#define STM32_ACTIVATE_PLLSAI TRUE
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#else
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#define STM32_ACTIVATE_PLLSAI FALSE
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#define STM32_ACTIVATE_PLLSAI FALSE
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#endif
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/**
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/**
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* @brief STM32_PLLSAIN field.
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* @brief STM32_PLLSAIN field.
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@ -113,6 +113,7 @@
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- RT: Merged RT4.
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- RT: Merged RT4.
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- NIL: Merged NIL2.
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- NIL: Merged NIL2.
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- NIL: Added STM32F7 demo.
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- NIL: Added STM32F7 demo.
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- HAL: Removed wrong SAI masks in STM32F4xx hal_lld.h (bug #745).
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- HAL: Fixed wrong mask placement in STM32F4xx hal_lld.h (bug #744).
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- HAL: Fixed wrong mask placement in STM32F4xx hal_lld.h (bug #744).
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- HAL: Fixed wrong indent in STM32F4xx hal_lld.h (bug #743).
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- HAL: Fixed wrong indent in STM32F4xx hal_lld.h (bug #743).
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- HAL: Removed unused macros in STM32F7xx and STM32F4xx hal_lld.h (bug #742).
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- HAL: Removed unused macros in STM32F7xx and STM32F4xx hal_lld.h (bug #742).
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