andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

STM32H7-related fixes. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12017 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
Giovanni Di Sirio 2018-05-10 10:55:35 +00:00
parent 85d08595ab
commit eaeabaf3c2
5 changed files with 22 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.h
View File

@ -243,14 +243,14 @@
#define STM32_USBCLK STM32_48CLK
#elif defined(STM32H7XX)
/* Defines directly STM32_USBCLK.*/
#define rccEnableOTG_FS rccEnableUSB1_OTG_HS
#define rccDisableOTG_FS rccDisableUSB1_OTG_HS
#define rccResetOTG_FS rccResetUSB1_OTG_HS
#define rccEnableOTG_HS rccEnableUSB2_OTG_HS
#define rccDisableOTG_HS rccDisableUSB2_OTG_HS
#define rccResetOTG_HS rccResetUSB2_OTG_HS
#define rccEnableOTG_HSULPI rccEnableUSB2_HSULPI
#define rccDisableOTG_HSULPI rccDisableUSB2_HSULPI
#define rccEnableOTG_FS rccEnableUSB2_OTG_HS
#define rccDisableOTG_FS rccDisableUSB2_OTG_HS
#define rccResetOTG_FS rccResetUSB2_OTG_HS
#define rccEnableOTG_HS rccEnableUSB1_OTG_HS
#define rccDisableOTG_HS rccDisableUSB1_OTG_HS
#define rccResetOTG_HS rccResetUSB1_OTG_HS
#define rccEnableOTG_HSULPI rccEnableUSB1_HSULPI
#define rccDisableOTG_HSULPI rccDisableUSB1_HSULPI
#else
#error "unsupported STM32 platform for OTG functionality"
#endif

2
os/hal/ports/STM32/STM32H7xx/hal_lld.c
View File

@ -102,7 +102,7 @@ static inline void init_pwr(void) {
PWR->CR3 = STM32_PWR_CR3;
PWR->CPUCR = STM32_PWR_CPUCR;
PWR->D3CR = STM32_VOS;
while ((PWR->CSR1 & PWR_CSR1_ACTVOS) == 0)
while ((PWR->D3CR & PWR_D3CR_VOSRDY) == 0)
;
#if STM32_PWR_CR2 & PWR_CR2_BREN
// while ((PWR->CR2 & PWR_CR2_BRRDY) == 0)

24
testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h
View File

@ -85,8 +85,8 @@
#define STM32_PLL1_DIVN_VALUE 400
#define STM32_PLL1_FRACN_VALUE 0
#define STM32_PLL1_DIVP_VALUE 2
#define STM32_PLL1_DIVQ_VALUE 8
#define STM32_PLL1_DIVR_VALUE 8
#define STM32_PLL1_DIVQ_VALUE 4
#define STM32_PLL1_DIVR_VALUE 2
#define STM32_PLL2_ENABLED TRUE
#define STM32_PLL2_P_ENABLED TRUE
#define STM32_PLL2_Q_ENABLED TRUE
@ -101,12 +101,12 @@
#define STM32_PLL3_P_ENABLED TRUE
#define STM32_PLL3_Q_ENABLED TRUE
#define STM32_PLL3_R_ENABLED TRUE
#define STM32_PLL3_DIVM_VALUE 4
#define STM32_PLL3_DIVN_VALUE 240
#define STM32_PLL3_DIVM_VALUE 8
#define STM32_PLL3_DIVN_VALUE 336
#define STM32_PLL3_FRACN_VALUE 0
#define STM32_PLL3_DIVP_VALUE 10
#define STM32_PLL3_DIVQ_VALUE 10
#define STM32_PLL3_DIVR_VALUE 10
#define STM32_PLL3_DIVP_VALUE 2
#define STM32_PLL3_DIVQ_VALUE 7
#define STM32_PLL3_DIVR_VALUE 2
/*
* Core clocks dynamic settings (can be changed at runtime).
@ -115,11 +115,11 @@
#define STM32_SW STM32_SW_PLL1_P_CK
#define STM32_RTCSEL STM32_RTCSEL_LSE_CK
#define STM32_D1CPRE STM32_D1CPRE_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV4
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV1
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV1
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV1
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV2
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2
/*
* Peripherals clocks static settings.

6
testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/portab.c
View File

@ -51,12 +51,6 @@
void portab_setup(void) {
/*
* ARD_D13 is programmed as output (board LED).
*/
palClearLine(LINE_ARD_D13);
palSetLineMode(LINE_ARD_D13, PAL_MODE_OUTPUT_PUSHPULL);
}
/** @} */

2
testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/portab.h
View File

@ -33,7 +33,7 @@
#define PORTAB_SDU1 SDU1
#define PORTAB_BLINK_LED1 LINE_ARD_D13
#define PORTAB_BLINK_LED1 LINE_LED1
/*===========================================================================*/
/* Module pre-compile time settings. */