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ChibiOS
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Various fixes after mass test-compile. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11268 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2018-01-14 09:34:28 +00:00
parent 3ae6678900
commit ecd03e17ce
7 changed files with 11 additions and 9 deletions
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4
demos/STM32/RT-STM32-LWIP-FATFS-USB/cfg-stm32f107_goldbull/portab.c
View File

@ -30,10 +30,10 @@
/*===========================================================================*/
/* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first).*/
static const SPIConfig hs_spicfg = {NULL, IOPORT3, GPIOC_SPI3_SD_CS, 0, 0};
static const SPIConfig hs_spicfg = {false, NULL, IOPORT3, GPIOC_SPI3_SD_CS, 0, 0};
/* Low speed SPI configuration (281.250kHz, CPHA=0, CPOL=0, MSb first).*/
static const SPIConfig ls_spicfg = {NULL, IOPORT3, GPIOC_SPI3_SD_CS,
static const SPIConfig ls_spicfg = {false, NULL, IOPORT3, GPIOC_SPI3_SD_CS,
SPI_CR1_BR_2 | SPI_CR1_BR_1,
0};

4
demos/STM32/RT-STM32F103-OLIMEX_STM32_P103-FATFS/main.c
View File

@ -106,10 +106,10 @@ static FATFS SDC_FS;
static bool fs_ready = FALSE;
/* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first).*/
static SPIConfig hs_spicfg = {NULL, IOPORT2, GPIOB_SPI2NSS, 0, 0};
static SPIConfig hs_spicfg = {false, NULL, IOPORT2, GPIOB_SPI2NSS, 0, 0};
/* Low speed SPI configuration (281.250kHz, CPHA=0, CPOL=0, MSb first).*/
static SPIConfig ls_spicfg = {NULL, IOPORT2, GPIOB_SPI2NSS,
static SPIConfig ls_spicfg = {false, NULL, IOPORT2, GPIOB_SPI2NSS,
SPI_CR1_BR_2 | SPI_CR1_BR_1,
0};

2
demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h
View File

@ -41,7 +41,7 @@
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#define HAL_USE_ADC TRUE
#endif
/**

1
os/hal/ports/LPC/LPC214x/hal_pal_lld.c
View File

@ -100,6 +100,7 @@ void _pal_lld_setgroupmode(ioportid_t port,
break;
case PAL_MODE_UNCONNECTED:
port->FIO_PIN |= mask;
/* Falls through.*/
case PAL_MODE_OUTPUT_PUSHPULL:
port->FIO_DIR |= mask;
break;

1
os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c
View File

@ -588,6 +588,7 @@ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
#else
osalDbgAssert(false, "isochronous support disabled");
#endif
/* Falls through.*/
case USB_EP_MODE_TYPE_BULK:
epr = EPR_EP_TYPE_BULK;
break;

2
os/hal/ports/STM32/STM32F7xx/stm32_rcc.h
View File

@ -528,7 +528,7 @@
*/
#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \
RCC_AHB1ENR_ETHMACTXEN | \
RCC_AHB1ENR_ETHMACRXEN)
RCC_AHB1ENR_ETHMACRXEN, lp)
/**
* @brief Disables the ETH peripheral clock.

6
os/hal/src/hal_usb.c
View File

@ -892,7 +892,7 @@ void _usb_ep0in(USBDriver *usbp, usbep_t ep) {
usbp->ep0state = USB_EP0_IN_WAITING_TX0;
return;
}
/* Falls into, it is intentional.*/
/* Falls through.*/
case USB_EP0_IN_WAITING_TX0:
/* Transmit phase over, receiving the zero sized status packet.*/
usbp->ep0state = USB_EP0_OUT_WAITING_STS;
@ -916,7 +916,7 @@ void _usb_ep0in(USBDriver *usbp, usbep_t ep) {
case USB_EP0_OUT_RX:
/* All the above are invalid states in the IN phase.*/
osalDbgAssert(false, "EP0 state machine error");
/* Falling through is intentional.*/
/* Falls through.*/
case USB_EP0_ERROR:
/* Error response, the state machine goes into an error state, the low
level layer will have to reset it to USB_EP0_WAITING_SETUP after
@ -975,7 +975,7 @@ void _usb_ep0out(USBDriver *usbp, usbep_t ep) {
case USB_EP0_IN_SENDING_STS:
/* All the above are invalid states in the IN phase.*/
osalDbgAssert(false, "EP0 state machine error");
/* Falling through is intentional.*/
/* Falls through.*/
case USB_EP0_ERROR:
/* Error response, the state machine goes into an error state, the low
level layer will have to reset it to USB_EP0_WAITING_SETUP after