Fixed bug 3224681.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_2.2.x@2829 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -71,7 +71,7 @@
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ioportmask_t palReadBus(IOBus *bus) {
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ioportmask_t palReadBus(IOBus *bus) {
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chDbgCheck((bus != NULL) &&
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chDbgCheck((bus != NULL) &&
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(bus->bus_offset > PAL_IOPORTS_WIDTH), "palReadBus");
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(bus->bus_offset < PAL_IOPORTS_WIDTH), "palReadBus");
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return palReadGroup(bus->bus_portid, bus->bus_mask, bus->bus_offset);
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return palReadGroup(bus->bus_portid, bus->bus_mask, bus->bus_offset);
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}
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}
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@ -96,7 +96,7 @@ ioportmask_t palReadBus(IOBus *bus) {
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void palWriteBus(IOBus *bus, ioportmask_t bits) {
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void palWriteBus(IOBus *bus, ioportmask_t bits) {
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chDbgCheck((bus != NULL) &&
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chDbgCheck((bus != NULL) &&
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(bus->bus_offset > PAL_IOPORTS_WIDTH), "palWriteBus");
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(bus->bus_offset < PAL_IOPORTS_WIDTH), "palWriteBus");
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palWriteGroup(bus->bus_portid, bus->bus_mask, bus->bus_offset, bits);
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palWriteGroup(bus->bus_portid, bus->bus_mask, bus->bus_offset, bits);
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}
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}
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@ -119,7 +119,7 @@ void palWriteBus(IOBus *bus, ioportmask_t bits) {
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void palSetBusMode(IOBus *bus, uint_fast8_t mode) {
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void palSetBusMode(IOBus *bus, uint_fast8_t mode) {
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chDbgCheck((bus != NULL) &&
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chDbgCheck((bus != NULL) &&
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(bus->bus_offset > PAL_IOPORTS_WIDTH), "palSetBusMode");
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(bus->bus_offset < PAL_IOPORTS_WIDTH), "palSetBusMode");
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palSetGroupMode(bus->bus_portid, bus->bus_mask, mode);
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palSetGroupMode(bus->bus_portid, bus->bus_mask, mode);
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}
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}
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@ -69,6 +69,7 @@
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*****************************************************************************
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*****************************************************************************
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*** 2.2.3 ***
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*** 2.2.3 ***
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- FIX: Fixed wrong checks in PAL driver (bug 3224681).
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- FIX: Fixed wrong checks in I/O Queues (bug 3219197).
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- FIX: Fixed wrong checks in I/O Queues (bug 3219197).
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- FIX: Fixed invalid assertion in adcConvert() (bug 3205410).
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- FIX: Fixed invalid assertion in adcConvert() (bug 3205410).
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- NEW: Improved preemption implementation for the Cortex-M0, now it uses
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- NEW: Improved preemption implementation for the Cortex-M0, now it uses
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