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ChibiOS
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Experimental port working now. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13492 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-03-31 11:59:10 +00:00
parent 69370d58d3
commit ed791a2588
5 changed files with 24 additions and 25 deletions
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2
demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/Makefile
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@ -5,7 +5,7 @@
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).

2
demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/debug/RT-STM32L552ZE-NUCLEO144-TEST (ST-Link GDB Server, Flash and Run).launch
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File diff suppressed because one or more lines are too long

4
os/common/ports/ARMv8-M-ML/chcore.c
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@ -60,13 +60,13 @@
void *port_swap_stacks(void *sp) {
thread_t *ntp;
chSysLockFromISR();
chSysLock();
/* TODO statistics, tracing etc */
currp->ctx.sp = sp;
ntp = chSchRunAhead();
chSysUnlockFromISR();
chSysUnlock();
return ntp->ctx.sp;
}

22
os/common/ports/ARMv8-M-ML/chcore.h
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@ -128,7 +128,7 @@
* reduce this value to zero when compiling with optimizations.
*/
#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
#define PORT_IDLE_THREAD_STACK_SIZE 16
#define PORT_IDLE_THREAD_STACK_SIZE 64
#endif
/**
@ -359,14 +359,15 @@ struct port_context {
* @details This code usually setup the context switching frame represented
* by an @p port_intctx structure.
*/
#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \
#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) do { \
(tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \
sizeof (struct port_intctx)); \
(tp)->ctx.sp->r4 = (uint32_t)(pf); \
(tp)->ctx.sp->r5 = (uint32_t)(arg); \
(tp)->ctx.sp->lr_exc = (uint32_t)0xFFFFFFFD; \
(tp)->ctx.sp->xpsr = (uint32_t)0x01000000; \
(tp)->ctx.sp->pc = (uint32_t)_port_thread_start; \
(tp)->ctx.sp->basepri = CORTEX_BASEPRI_KERNEL; \
(tp)->ctx.sp->r5 = (uint32_t)(arg); \
(tp)->ctx.sp->r4 = (uint32_t)(pf); \
(tp)->ctx.sp->lr_exc = (uint32_t)0xFFFFFFFD; \
(tp)->ctx.sp->xpsr = (uint32_t)0x01000000; \
(tp)->ctx.sp->pc = (uint32_t)__port_thread_start; \
} while (false)
/**
@ -402,9 +403,11 @@ struct port_context {
* enabled to invoke system APIs.
*/
#define PORT_IRQ_EPILOGUE() do { \
port_lock_from_isr(); \
if (chSchIsPreemptionRequired()) { \
SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; \
} \
port_unlock_from_isr(); \
} while (false)
/**
@ -441,9 +444,11 @@ struct port_context {
*/
#if (CH_DBG_ENABLE_STACK_CHECK == FALSE) || defined(__DOXYGEN__)
#define port_switch(ntp, otp) do { \
_dbg_leave_lock(); \
register thread_t *_ntp asm ("r0") = (ntp); \
register thread_t *_otp asm ("r1") = (otp); \
asm volatile ("svc #0" : : "r" (_otp), "r" (_ntp) : "memory"); \
_dbg_enter_lock(); \
} while (false)
#else
#define port_switch(ntp, otp) do { \
@ -467,7 +472,7 @@ struct port_context {
extern "C" {
#endif
void port_init(void);
void _port_thread_start(void);
void __port_thread_start(void);
#ifdef __cplusplus
}
#endif
@ -584,6 +589,7 @@ __STATIC_FORCEINLINE void port_suspend(void) {
__STATIC_FORCEINLINE void port_enable(void) {
__set_BASEPRI(CORTEX_BASEPRI_DISABLED);
__enable_irq();
}
/**

19
os/common/ports/ARMv8-M-ML/compilers/GCC/chcoreasm.S
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@ -75,14 +75,14 @@
.thumb_func
.globl SVC_Handler
SVC_Handler:
mrs r2, PSP
mrs r3, BASEPRI
mrs r2, PSP
stmdb r2!, {r3-r11,lr}
str r2, [r1, #CONTEXT_OFFSET]
ldr r2, [r0, #CONTEXT_OFFSET]
ldmia r2!, {r3-r11, lr}
msr BASEPRI, r3
msr PSP, r2
msr BASEPRI, r3
bx lr
/*--------------------------------------------------------------------------*
@ -91,13 +91,13 @@ SVC_Handler:
.thumb_func
.globl PendSV_Handler
PendSV_Handler:
mrs r0, PSP
mrs r3, BASEPRI
mrs r0, PSP
stmdb r0!, {r3-r11,lr}
bl port_swap_stacks
ldmia r0!, {r3-r11, lr}
msr BASEPRI, r3
msr PSP, r0
msr BASEPRI, r3
bx lr
/*--------------------------------------------------------------------------*
@ -109,23 +109,16 @@ PendSV_Handler:
* called on thread function return.
*--------------------------------------------------------------------------*/
.thumb_func
.globl _port_thread_start
_port_thread_start:
.globl __port_thread_start
__port_thread_start:
#if CH_DBG_ENABLE_STACK_CHECK && PORT_ENABLE_GUARD_PAGES
bl _port_set_region
#endif
#if CH_DBG_SYSTEM_STATE_CHECK
bl _dbg_check_unlock
#endif
#if CH_DBG_STATISTICS
bl _stats_stop_measure_crit_thd
#endif
#if CORTEX_SIMPLIFIED_PRIORITY
cpsie i
#else
movs r3, #0 /* CORTEX_BASEPRI_DISABLED */
msr BASEPRI, r3
#endif
mov r0, r5
blx r4
movs r0, #0 /* MSG_OK */