git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_2.4.x@4481 35acf78f-673a-0410-8e92-d51de3d6d3f4

2012-07-28 09:36:51 +00:00 · 2012-07-28 09:36:51 +00:00 · eebebb6e02
parent 84d3528b70
commit eebebb6e02
6 changed files with 188 additions and 13 deletions
--- a/docs/reports/STM32F103-72-GCC.txt
+++ b/docs/reports/STM32F103-72-GCC.txt
@ -5,8 +5,8 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states)

 *** ChibiOS/RT test suite
 ***
-*** Kernel:       2.4.1
-*** Compiled:     May 12 2012 - 09:13:44
+*** Kernel:       2.4.2
+*** Compiled:     Jul 28 2012 - 10:34:29
 *** Compiler:     GCC 4.6.2
 *** Architecture: ARMv7-M
 *** Core Variant: Cortex-M3
--- a/os/hal/platforms/STM32F2xx/platform.dox
+++ b/os/hal/platforms/STM32F2xx/platform.dox
@ -229,6 +229,23 @@
 * @ingroup STM32F2xx_DRIVERS
 */

+/**
+ * @defgroup STM32F2xx_SDC STM32F2xx SDC Support
+ * @details The STM32F2xx SDC driver uses the SDIO peripheral.
+ *
+ * @section stm32f2xx_sdc_1 Supported HW resources
+ * - SDIO.
+ * - DMA2.
+ * .
+ * @section stm32f2xx_sdc_2 STM32F4xx SDC driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Programmable interrupt priority.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * .
+ * @ingroup STM32F2xx_DRIVERS
+ */
+
 /**
 * @defgroup STM32F2xx_SERIAL STM32F2xx Serial Support
 * @details The STM32F2xx Serial driver uses the USART/UART peripherals in a
--- a/os/hal/platforms/STM32F2xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F2xx/stm32_rcc.h
@ -398,12 +398,11 @@
 /** @} */

 /**
- * @name   PWR interface specific RCC operations
+ * @name    PWR interface specific RCC operations
 * @{
 */
 /**
 * @brief   Enables the PWR interface clock.
- * @note    The @p lp parameter is ignored in this family.
 *
 * @param[in] lp        low power enable flag
 *
@ -413,7 +412,6 @@

 /**
 * @brief   Disables PWR interface clock.
- * @note    The @p lp parameter is ignored in this family.
 *
 * @param[in] lp        low power enable flag
 *
@ -429,6 +427,62 @@
 #define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
 /** @} */

+
+/**
+ * @name    CAN peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the CAN1 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp)
+
+/**
+ * @brief   Disables the CAN1 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp)
+
+/**
+ * @brief   Resets the CAN1 peripheral.
+ *
+ * @api
+ */
+#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST)
+
+/**
+ * @brief   Enables the CAN2 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp)
+
+/**
+ * @brief   Disables the CAN2 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp)
+
+/**
+ * @brief   Resets the CAN2 peripheral.
+ *
+ * @api
+ */
+#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST)
+/** @} */
+
 /**
 * @name    ETH peripheral specific RCC operations
 * @{
@ -575,6 +629,39 @@
 #define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)
 /** @} */

+/**
+ * @name    SDIO peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the SDIO peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSDIO(lp) rccEnableAPB2(RCC_APB2ENR_SDIOEN, lp)
+
+/**
+ * @brief   Disables the SDIO peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSDIO(lp) rccDisableAPB2(RCC_APB2ENR_SDIOEN, lp)
+
+/**
+ * @brief   Resets the SDIO peripheral.
+ * @note    Not supported in this family, does nothing.
+ *
+ * @api
+ */
+#define rccResetSDIO() rccResetAPB2(RCC_APB2RSTR_SDIORST)
+/** @} */
+
 /**
 * @name    SPI peripherals specific RCC operations
 * @{
--- a/os/hal/platforms/STM32F4xx/platform.dox
+++ b/os/hal/platforms/STM32F4xx/platform.dox
@ -77,18 +77,18 @@
 */

 /**
- * @defgroup STM32F2xx_CAN STM32F2xx CAN Support
- * @details The STM32F2xx CAN driver uses the CAN peripherals.
+ * @defgroup STM32F4xx_CAN STM32F4xx CAN Support
+ * @details The STM32F4xx CAN driver uses the CAN peripherals.
 *
- * @section stm32f2xx_can_1 Supported HW resources
+ * @section stm32f4xx_can_1 Supported HW resources
 * - bxCAN1.
 * .
- * @section stm32f2xx_can_2 STM32F2xx CAN driver implementation features
+ * @section stm32f4xx_can_2 STM32F4xx CAN driver implementation features
 * - Clock stop for reduced power usage when the driver is in stop state.
 * - Support for bxCAN sleep mode.
 * - Programmable bxCAN interrupts priority level.
 * .
- * @ingroup STM32F2xx_DRIVERS
+ * @ingroup STM32F4xx_DRIVERS
 */

 /**
@ -229,6 +229,23 @@
 * @ingroup STM32F4xx_DRIVERS
 */

+/**
+ * @defgroup STM32F4xx_SDC STM32F4xx SDC Support
+ * @details The STM32F4xx SDC driver uses the SDIO peripheral.
+ *
+ * @section stm32f4xx_sdc_1 Supported HW resources
+ * - SDIO.
+ * - DMA2.
+ * .
+ * @section stm32f4xx_sdc_2 STM32F4xx SDC driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Programmable interrupt priority.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * .
+ * @ingroup STM32F4xx_DRIVERS
+ */
+
 /**
 * @defgroup STM32F4xx_SERIAL STM32F4xx Serial Support
 * @details The STM32F4xx Serial driver uses the USART/UART peripherals in a
--- a/os/hal/platforms/STM32F4xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F4xx/stm32_rcc.h
@ -403,7 +403,6 @@
 */
 /**
 * @brief   Enables the PWR interface clock.
- * @note    The @p lp parameter is ignored in this family.
 *
 * @param[in] lp        low power enable flag
 *
@ -413,7 +412,6 @@

 /**
 * @brief   Disables PWR interface clock.
- * @note    The @p lp parameter is ignored in this family.
 *
 * @param[in] lp        low power enable flag
 *
@ -429,6 +427,62 @@
 #define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
 /** @} */

+
+/**
+ * @name    CAN peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the CAN1 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp)
+
+/**
+ * @brief   Disables the CAN1 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp)
+
+/**
+ * @brief   Resets the CAN1 peripheral.
+ *
+ * @api
+ */
+#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST)
+
+/**
+ * @brief   Enables the CAN2 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp)
+
+/**
+ * @brief   Disables the CAN2 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp)
+
+/**
+ * @brief   Resets the CAN2 peripheral.
+ *
+ * @api
+ */
+#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST)
+/** @} */
+
 /**
 * @name    ETH peripheral specific RCC operations
 * @{
--- a/readme.txt
+++ b/readme.txt
@ -88,7 +88,7 @@
  3536070).
 - FIX: Fixed issue with DMA channel init in STM32 ADC and SPI drivers (bug
  3535938).
- FIX: Fixed unreliable PHY initialization (bug 3534819)(backported to 2.4.2).
+- FIX: Fixed unreliable PHY initialization (bug 3534819).
 - FIX: Fixed wrong ADC callback buffer pointer in ADC driver (bug 3534767).
 - FIX: Fixed lwIP-related files missing from version 2.4.1 (bug 3533887).
 - FIX: Fixed problem with arm-v6m and state checker (bug 3532591).