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G4 PWR improvements. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13322 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-02-06 13:56:02 +00:00
parent b9e9c165e3
commit ef9ec13cfe
5 changed files with 106 additions and 103 deletions
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4
demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h
View File

@ -42,7 +42,9 @@
*/
#define STM32_NO_INIT FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (STM32_PLS_LEV0 | STM32_PVDE_DISABLED)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE

104
demos/STM32/RT-STM32G474RE-NUCLEO64/debug/RT-STM32G474RE-NUCLEO64 (OpenOCD, Flash and Run).launch
View File

@ -1,52 +1,52 @@
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34
os/hal/ports/STM32/STM32G4xx/hal_lld.c
View File

@ -104,19 +104,6 @@ static void hal_lld_backup_domain_init(void) {
*/
void hal_lld_init(void) {
/* Reset of all peripherals.
Note, GPIOs are not reset because initialized before this point in
board files.*/
rccResetAHB1(~0);
rccResetAHB2(~STM32_GPIO_EN_MASK);
rccResetAHB3(~0);
rccResetAPB1R1(~RCC_APB1RSTR1_PWRRST);
rccResetAPB1R2(~0);
rccResetAPB2(~0);
/* PWR clock enabled.*/
rccEnablePWRInterface(true);
/* Initializes the backup domain.*/
hal_lld_backup_domain_init();
@ -142,11 +129,22 @@ void hal_lld_init(void) {
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* Reset of all peripherals.
Note, GPIOs are not reset because initialized before this point in
board files.*/
rccResetAHB1(~0);
rccResetAHB2(~STM32_GPIO_EN_MASK);
rccResetAHB3(~0);
rccResetAPB1R1(~0);
rccResetAPB1R2(~0);
rccResetAPB2(~0);
/* PWR clock enable.*/
#if defined(HAL_USE_RTC) && defined(RCC_APBENR1_RTCAPBEN)
RCC->APB1ENR1 = RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN;
rccEnableAPB1R1(RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN, false)
#else
RCC->APB1ENR1 = RCC_APB1ENR1_PWREN;
rccEnableAPB1R1(RCC_APB1ENR1_PWREN, false)
#endif
/* Core voltage setup.*/
@ -154,6 +152,12 @@ void stm32_clock_init(void) {
while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */
; /* stable. */
/* Additional PWR configurations.*/
PWR->CR2 = STM32_PWR_CR2;
PWR->CR3 = STM32_PWR_CR3;
PWR->CR4 = STM32_PWR_CR4;
PWR->CR5 = STM32_CR5BITS;
#if STM32_HSI16_ENABLED
/* HSI activation.*/
RCC->CR |= RCC_CR_HSION;

63
os/hal/ports/STM32/STM32G4xx/hal_lld.h
View File

@ -90,7 +90,7 @@
/** @} */
/**
* @name PWR_CR1 register bits definitions
* @name VOS field definitions
* @{
*/
#define STM32_VOS_MASK (3U << 9U) /**< Core voltage mask. */
@ -98,37 +98,6 @@
#define STM32_VOS_RANGE2 (2U << 9U) /**< Core voltage 1.0 Volts. */
/** @} */
/**
* @name PWR_CR2 register bits definitions
* @{
*/
#define STM32_PVDE_DISABLED (0U << 1U) /**< PVD enable bit off. */
#define STM32_PVDE_ENABLED (1U << 1U) /**< PVD enable bit on. */
#define STM32_PLS_MASK (7U << 1U) /**< PLS bits mask. */
#define STM32_PLS(n) ((n) << 1U) /**< PLS level. */
#define STM32_PLS_LEV0 STM32_PLS(0U) /**< PLS level 0. */
#define STM32_PLS_LEV1 STM32_PLS(1U) /**< PLS level 1. */
#define STM32_PLS_LEV2 STM32_PLS(2U) /**< PLS level 2. */
#define STM32_PLS_LEV3 STM32_PLS(3U) /**< PLS level 3. */
#define STM32_PLS_LEV4 STM32_PLS(4U) /**< PLS level 4. */
#define STM32_PLS_LEV5 STM32_PLS(5U) /**< PLS level 5. */
#define STM32_PLS_LEV6 STM32_PLS(6U) /**< PLS level 6. */
#define STM32_PLS_LEV7 STM32_PLS(7U) /**< PLS level 7. */
#define STM32_PVMEN1_DISABLED (0U << 6U) /**< PVMEN1 enable bit off. */
#define STM32_PVMEN1_ENABLED (1U << 6U) /**< PVMEN1 enable bit on. */
#define STM32_PVMEN2_DISABLED (0U << 7U) /**< PVMEN2 enable bit off. */
#define STM32_PVMEN2_ENABLED (1U << 7U) /**< PVMEN2 enable bit on. */
/** @} */
/**
* @name RCC_CR register bits definitions
* @{
*/
/** @} */
/**
* @name RCC_CFGR register bits definitions
* @{
@ -348,8 +317,21 @@
* @brief PWR CR2 register initialization value.
*/
#if !defined(STM32_PWR_CR2) || defined(__DOXYGEN__)
#define STM32_PWR_CR2 (STM32_PLS_LEV0 | \
STM32_PVDE_DISABLED)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#endif
/**
* @brief PWR CR3 register initialization value.
*/
#if !defined(STM32_PWR_CR3) || defined(__DOXYGEN__)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#endif
/**
* @brief PWR CR4 register initialization value.
*/
#if !defined(STM32_PWR_CR4) || defined(__DOXYGEN__)
#define STM32_PWR_CR4 (0U)
#endif
/**
@ -704,6 +686,11 @@
*/
#define STM32_SYSCLK_MAX 170000000
/**
* @brief Maximum SYSCLK clock frequency without voltage boost.
*/
#define STM32_SYSCLK_MAX_NOBOOST 150000000
/**
* @brief Maximum HSE clock frequency at current voltage setting.
*/
@ -827,6 +814,7 @@
#elif STM32_VOS == STM32_VOS_RANGE2
#define STM32_SYSCLK_MAX 26000000
#define STM32_SYSCLK_MAX_NOBOOST 150000000
#define STM32_HSECLK_MAX 26000000
#define STM32_HSECLK_BYP_MAX 26000000
#define STM32_HSECLK_MIN 8000000
@ -1827,6 +1815,13 @@
#define STM32_FLASHBITS FLASH_ACR_LATENCY_8WS
#endif
/* Frequency-dependent settings for PWR_CR5.*/
#if STM32_SYSCLK > STM32_SYSCLK_MAX_NOBOOST
#define STM32_CR5BITS 0
#else
#define STM32_CR5BITS PWR_CR5_R1MODE
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/

4
tools/ftl/processors/conf/mcuconf_stm32g4x4xx/mcuconf.h.ftl
View File

@ -53,7 +53,9 @@
*/
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(STM32_PLS_LEV0 | STM32_PVDE_DISABLED)"}
#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(PWR_CR2_PLS_LEV0)"}
#define STM32_PWR_CR3 ${doc.STM32_PWR_CR3!"(PWR_CR3_EIWF)"}
#define STM32_PWR_CR4 ${doc.STM32_PWR_CR4!"(0U)"}
#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"TRUE"}
#define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"TRUE"}
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"TRUE"}