git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5121 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
8311f8dc8e
commit
efc74c184b
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@ -31,59 +31,10 @@
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/* BAM info, SWT off, WTE off, VLE from settings.*/
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.section .bam, "ax"
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.long 0x015A0000
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.long .clear_ecc
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/* RAM clearing, this device requires a write to all RAM location in
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order to initialize the ECC detection hardware, this is going to
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slow down the startup but there is no way around.
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Note all registers are cleared in order to avoid possible problems
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with lockstep mode.*/
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.clear_ecc:
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xor %r0, %r0, %r0
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xor %r1, %r1, %r1
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xor %r2, %r2, %r2
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xor %r3, %r3, %r3
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xor %r4, %r4, %r4
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xor %r5, %r5, %r5
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xor %r6, %r6, %r6
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xor %r7, %r7, %r7
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xor %r8, %r8, %r8
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xor %r9, %r9, %r9
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xor %r10, %r10, %r10
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xor %r11, %r11, %r11
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xor %r12, %r12, %r12
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xor %r13, %r13, %r13
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xor %r14, %r14, %r14
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xor %r15, %r15, %r15
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xor %r16, %r16, %r16
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xor %r17, %r17, %r17
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xor %r18, %r18, %r18
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xor %r19, %r19, %r19
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xor %r20, %r20, %r20
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xor %r21, %r21, %r21
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xor %r22, %r22, %r22
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xor %r23, %r23, %r23
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xor %r24, %r24, %r24
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xor %r25, %r25, %r25
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xor %r26, %r26, %r26
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xor %r27, %r27, %r27
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xor %r28, %r28, %r28
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xor %r29, %r29, %r29
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xor %r30, %r30, %r30
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xor %r31, %r31, %r31
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lis %r4, __ram_start__@h
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ori %r4, %r4, __ram_start__@l
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lis %r5, __ram_end__@h
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ori %r5, %r5, __ram_end__@l
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.cleareccloop:
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cmpl cr0, %r4, %r5
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bge cr0, .cleareccend
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stmw %r16, 0(%r4)
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addi %r4, %r4, 64
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b .cleareccloop
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.cleareccend:
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.long .init
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/* HW configuration.*/
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.init:
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bl _coreinit
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b _boot_address
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@ -158,35 +158,28 @@
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/*
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* Unhandled exceptions handler.
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*/
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.weak _IVOR0
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_IVOR0:
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.weak _IVOR1
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_IVOR1:
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.weak _IVOR2
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_IVOR2:
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.weak _IVOR3
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_IVOR3:
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.weak _IVOR5
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_IVOR5:
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.weak _IVOR6
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_IVOR6:
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.weak _IVOR7
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_IVOR7:
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.weak _IVOR8
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_IVOR8:
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.weak _IVOR9
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_IVOR9:
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.weak _IVOR11
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_IVOR11:
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.weak _IVOR12
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_IVOR12:
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.weak _IVOR13
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_IVOR13:
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.weak _IVOR14
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_IVOR14:
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.weak _IVOR15
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_IVOR15:
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.weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
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.weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
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.weak _IVOR12, _IVOR13, _IVOR14, _IVOR15, _IVOR32, _IVOR33
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.weak _IVOR34
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.weak _unhandled_exception
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_IVOR0:
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_IVOR1:
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_IVOR2:
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_IVOR3:
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_IVOR5:
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_IVOR6:
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_IVOR7:
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_IVOR8:
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_IVOR9:
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_IVOR11:
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_IVOR12:
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_IVOR13:
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_IVOR14:
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_IVOR15:
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_IVOR32:
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_IVOR33:
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_IVOR34:
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.type _unhandled_exception, @function
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_unhandled_exception:
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b _unhandled_exception
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@ -197,13 +190,63 @@ _unhandled_exception:
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.globl _coreinit
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.type _coreinit, @function
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_coreinit:
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/*
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* RAM clearing, this device requires a write to all RAM location in
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* order to initialize the ECC detection hardware, this is going to
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* slow down the startup but there is no way around.
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* Note all registers are cleared in order to avoid possible problems
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* with lockstep mode.
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*/
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.clear_ecc:
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xor %r0, %r0, %r0
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xor %r1, %r1, %r1
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xor %r2, %r2, %r2
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xor %r3, %r3, %r3
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xor %r4, %r4, %r4
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xor %r5, %r5, %r5
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xor %r6, %r6, %r6
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xor %r7, %r7, %r7
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xor %r8, %r8, %r8
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xor %r9, %r9, %r9
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xor %r10, %r10, %r10
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xor %r11, %r11, %r11
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xor %r12, %r12, %r12
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xor %r13, %r13, %r13
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xor %r14, %r14, %r14
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xor %r15, %r15, %r15
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xor %r16, %r16, %r16
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xor %r17, %r17, %r17
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xor %r18, %r18, %r18
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xor %r19, %r19, %r19
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xor %r20, %r20, %r20
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xor %r21, %r21, %r21
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xor %r22, %r22, %r22
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xor %r23, %r23, %r23
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xor %r24, %r24, %r24
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xor %r25, %r25, %r25
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xor %r26, %r26, %r26
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xor %r27, %r27, %r27
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xor %r28, %r28, %r28
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xor %r29, %r29, %r29
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xor %r30, %r30, %r30
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xor %r31, %r31, %r31
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lis %r4, __ram_start__@h
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ori %r4, %r4, __ram_start__@l
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lis %r5, __ram_end__@h
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ori %r5, %r5, __ram_end__@l
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.cleareccloop:
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cmpl %cr0, %r4, %r5
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bge %cr0, .cleareccend
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stmw %r16, 0(%r4)
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addi %r4, %r4, 64
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b .cleareccloop
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.cleareccend:
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/*
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* Special function registers clearing, required in order to avoid
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* possible problems with lockstep mode.
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*/
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xor %r31, %r31, %r31
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mtcrf 0xFF, %r31
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mtspr 8, %r31 /* LR */
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mtspr 9, %r31 /* CTR */
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mtspr 22, %r31 /* DEC */
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mtspr 26, %r31 /* SRR0-1 */
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@ -231,7 +274,9 @@ _coreinit:
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mtspr 604, %r31 /* SPRG8-9 */
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mtspr 605, %r31
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/* MSR initialization.*/
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/*
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* MSR initialization.
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*/
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lis %r3, MSR_DEFAULT@h
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ori %r3, %r3, MSR_DEFAULT@l
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mtMSR %r3
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