More L4+ code.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12195 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
Giovanni Di Sirio
parent
feb706f4bb
commit
f06b6487f9
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* STM32L4R5xI memory setup.
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*/
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MEMORY
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{
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flash0 : org = 0x08000000, len = 2M
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flash1 : org = 0x00000000, len = 0
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flash2 : org = 0x00000000, len = 0
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flash3 : org = 0x00000000, len = 0
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flash4 : org = 0x00000000, len = 0
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flash5 : org = 0x00000000, len = 0
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flash6 : org = 0x00000000, len = 0
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flash7 : org = 0x00000000, len = 0
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ram0 : org = 0x20000000, len = 640k /* SRAM1+SRAM2+SRAM3 */
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ram1 : org = 0x20000000, len = 192k /* SRAM1 */
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ram2 : org = 0x00000000, len = 64k /* SRAM2 */
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ram3 : org = 0x00000000, len = 384k /* SRAM3 */
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ram4 : org = 0x10000000, len = 64k /* SRAM2 alias */
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ram5 : org = 0x00000000, len = 0
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ram6 : org = 0x00000000, len = 0
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ram7 : org = 0x00000000, len = 0
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}
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/* For each data/text section two region are defined, a virtual region
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and a load region (_LMA suffix).*/
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/* Flash region to be used for exception vectors.*/
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REGION_ALIAS("VECTORS_FLASH", flash0);
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REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
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/* Flash region to be used for constructors and destructors.*/
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REGION_ALIAS("XTORS_FLASH", flash0);
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REGION_ALIAS("XTORS_FLASH_LMA", flash0);
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/* Flash region to be used for code text.*/
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REGION_ALIAS("TEXT_FLASH", flash0);
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REGION_ALIAS("TEXT_FLASH_LMA", flash0);
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/* Flash region to be used for read only data.*/
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REGION_ALIAS("RODATA_FLASH", flash0);
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REGION_ALIAS("RODATA_FLASH_LMA", flash0);
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/* Flash region to be used for various.*/
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REGION_ALIAS("VARIOUS_FLASH", flash0);
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REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
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/* Flash region to be used for RAM(n) initialization data.*/
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REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
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/* RAM region to be used for Main stack. This stack accommodates the processing
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of all exceptions and interrupts.*/
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REGION_ALIAS("MAIN_STACK_RAM", ram0);
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/* RAM region to be used for the process stack. This is the stack used by
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the main() function.*/
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REGION_ALIAS("PROCESS_STACK_RAM", ram0);
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/* RAM region to be used for data segment.*/
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REGION_ALIAS("DATA_RAM", ram0);
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REGION_ALIAS("DATA_RAM_LMA", flash0);
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/* RAM region to be used for BSS segment.*/
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REGION_ALIAS("BSS_RAM", ram0);
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/* RAM region to be used for the default heap.*/
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REGION_ALIAS("HEAP_RAM", ram0);
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/* Generic rules inclusion.*/
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INCLUDE rules.ld
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# Required platform files.
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PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
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$(CHIBIOS)/os/hal/ports/STM32/STM32L4xx+/stm32_isr.c \
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$(CHIBIOS)/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
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# Required include directories.
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PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
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$(CHIBIOS)/os/hal/ports/STM32/STM32L4xx+
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# Optional platform files.
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ifeq ($(USE_SMART_BUILD),yes)
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# Configuration files directory
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ifeq ($(CONFDIR),)
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CONFDIR = .
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endif
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HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h | egrep -e "\#define"))
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else
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endif
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# Drivers compatible with the platform.
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
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# Shared variables
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ALLCSRC += $(PLATFORMSRC)
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ALLINC += $(PLATFORMINC)
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@ -0,0 +1,255 @@
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32L4xx+/stm32_isr.h
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* @brief STM32L4xx+ ISR handler code.
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*
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* @addtogroup SRM32L4xxp_ISR
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* @{
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*/
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#include "hal.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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#define exti_serve_irq(pr, channel) { \
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\
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if ((pr) & (1U << (channel))) { \
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_pal_isr_code(channel); \
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} \
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__)
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#if !defined(STM32_DISABLE_EXTI0_HANDLER)
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/**
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* @brief EXTI[0] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector58) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR1;
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pr &= EXTI->IMR1 & (1U << 0);
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EXTI->PR1 = pr;
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exti_serve_irq(pr, 0);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI1_HANDLER)
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/**
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* @brief EXTI[1] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector5C) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR1;
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pr &= EXTI->IMR1 & (1U << 1);
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EXTI->PR1 = pr;
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exti_serve_irq(pr, 1);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI2_HANDLER)
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/**
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* @brief EXTI[2] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector60) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR1;
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pr &= EXTI->IMR1 & (1U << 2);
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EXTI->PR1 = pr;
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exti_serve_irq(pr, 2);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI3_HANDLER)
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/**
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* @brief EXTI[3] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector64) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR1;
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pr &= EXTI->IMR1 & (1U << 3);
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EXTI->PR1 = pr;
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exti_serve_irq(pr, 3);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI4_HANDLER)
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/**
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* @brief EXTI[4] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector68) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR1;
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pr &= EXTI->IMR1 & (1U << 4);
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EXTI->PR1 = pr;
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exti_serve_irq(pr, 4);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI5_9_HANDLER)
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/**
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* @brief EXTI[5]...EXTI[9] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector9C) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR1;
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pr &= EXTI->IMR1 & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
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(1U << 9));
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EXTI->PR1 = pr;
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exti_serve_irq(pr, 5);
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exti_serve_irq(pr, 6);
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exti_serve_irq(pr, 7);
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exti_serve_irq(pr, 8);
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exti_serve_irq(pr, 9);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI10_15_HANDLER)
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/**
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* @brief EXTI[10]...EXTI[15] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorE0) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR1;
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pr &= EXTI->IMR1 & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
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(1U << 14) | (1U << 15));
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EXTI->PR1 = pr;
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exti_serve_irq(pr, 10);
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exti_serve_irq(pr, 11);
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exti_serve_irq(pr, 12);
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exti_serve_irq(pr, 13);
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exti_serve_irq(pr, 14);
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exti_serve_irq(pr, 15);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Enables IRQ sources.
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*
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* @notapi
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*/
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void irqInit(void) {
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#if HAL_USE_PAL
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nvicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY);
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nvicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY);
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nvicEnableVector(EXTI2_IRQn, STM32_IRQ_EXTI2_PRIORITY);
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nvicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY);
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nvicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY);
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nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY);
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nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY);
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#endif
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}
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/**
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* @brief Disables IRQ sources.
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*
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* @notapi
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*/
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void irqDeinit(void) {
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#if HAL_USE_PAL
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nvicDisableVector(EXTI0_IRQn);
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nvicDisableVector(EXTI1_IRQn);
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nvicDisableVector(EXTI2_IRQn);
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nvicDisableVector(EXTI3_IRQn);
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nvicDisableVector(EXTI4_IRQn);
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nvicDisableVector(EXTI9_5_IRQn);
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nvicDisableVector(EXTI15_10_IRQn);
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#endif
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}
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/** @} */
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@ -0,0 +1,152 @@
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
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|
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Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
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|
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/**
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* @file STM32L4xx+/stm32_isr.h
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* @brief STM32L4xx+ ISR handler header.
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*
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* @addtogroup SRM32L4xxp_ISR
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* @{
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*/
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#ifndef STM32_ISR_H
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#define STM32_ISR_H
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief EXTI0 interrupt priority level setting.
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*/
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#if !defined(STM32_IRQ_EXTI0_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_IRQ_EXTI0_PRIORITY 6
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#endif
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/**
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* @brief EXTI1 interrupt priority level setting.
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*/
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#if !defined(STM32_IRQ_EXTI1_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_IRQ_EXTI1_PRIORITY 6
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#endif
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/**
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* @brief EXTI2 interrupt priority level setting.
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*/
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#if !defined(STM32_IRQ_EXTI2_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_IRQ_EXTI2_PRIORITY 6
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#endif
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/**
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* @brief EXTI3 interrupt priority level setting.
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*/
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#if !defined(STM32_IRQ_EXTI3_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_IRQ_EXTI3_PRIORITY 6
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#endif
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/**
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* @brief EXTI4 interrupt priority level setting.
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||||
*/
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#if !defined(STM32_IRQ_EXTI4_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_IRQ_EXTI4_PRIORITY 6
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#endif
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/**
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* @brief EXTI9..5 interrupt priority level setting.
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||||
*/
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#if !defined(STM32_IRQ_EXTI5_9_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_IRQ_EXTI5_9_PRIORITY 6
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#endif
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|
||||
/**
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* @brief EXTI15..10 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI10_15_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_IRQ_EXTI10_15_PRIORITY 6
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#endif
|
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|
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/**
|
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* @brief EXTI16-EXTI35..38 interrupt priority level setting.
|
||||
*/
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||||
#if !defined(STM32_IRQ_EXTI1635_38_PRIORITY) || defined(__DOXYGEN__)
|
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#define STM32_IRQ_EXTI1635_38_IRQ_PRIORIT 6
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#endif
|
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|
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/**
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* @brief EXTI18 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI18_PRIORITY) || defined(__DOXYGEN__)
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||||
#define STM32_IRQ_EXTI18_PRIORITY 6
|
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#endif
|
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|
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/**
|
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* @brief EXTI19 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI19_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI19_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI20 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI20_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI20_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI21..22 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI21_22_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI21_22_PRIORITY 6
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void irqInit(void);
|
||||
void irqDeinit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32_ISR_H */
|
||||
|
||||
/** @} */
|
||||
Loading…
Reference in New Issue