diff --git a/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.c b/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.c index 73dbb3af3..c61549e19 100644 --- a/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.c +++ b/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.c @@ -136,6 +136,262 @@ static struct { /* Driver interrupt handlers. */ /*===========================================================================*/ +#if defined(STM32_GPDMA1_CH0_HANDLER) || defined(__DOXYGEN__) +/** + * @brief GPDMA1 channel 0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_GPDMA1_CH0_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpdmaServeInterrupt(STM32_GPDMA1_CHANNEL0); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_GPDMA1_CH1_HANDLER) || defined(__DOXYGEN__) +/** + * @brief GPDMA1 channel 1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_GPDMA1_CH1_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpdmaServeInterrupt(STM32_GPDMA1_CHANNEL1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_GPDMA1_CH2_HANDLER) || defined(__DOXYGEN__) +/** + * @brief GPDMA1 channel 2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_GPDMA1_CH2_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpdmaServeInterrupt(STM32_GPDMA1_CHANNEL2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_GPDMA1_CH3_HANDLER) || defined(__DOXYGEN__) +/** + * @brief GPDMA1 channel 3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_GPDMA1_CH3_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpdmaServeInterrupt(STM32_GPDMA1_CHANNEL3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_GPDMA1_CH4_HANDLER) || defined(__DOXYGEN__) +/** + * @brief GPDMA1 channel 4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_GPDMA1_CH4_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpdmaServeInterrupt(STM32_GPDMA1_CHANNEL4); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_GPDMA1_CH5_HANDLER) || defined(__DOXYGEN__) +/** + * @brief GPDMA1 channel 5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_GPDMA1_CH5_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpdmaServeInterrupt(STM32_GPDMA1_CHANNEL5); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_GPDMA1_CH6_HANDLER) || defined(__DOXYGEN__) +/** + * @brief GPDMA1 channel 6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_GPDMA1_CH6_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpdmaServeInterrupt(STM32_GPDMA1_CHANNEL6); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_GPDMA1_CH7_HANDLER) || defined(__DOXYGEN__) +/** + * @brief GPDMA1 channel 7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_GPDMA1_CH7_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpdmaServeInterrupt(STM32_GPDMA1_CHANNEL7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_GPDMA2_CH0_HANDLER) || defined(__DOXYGEN__) +/** + * @brief GPDMA2 channel 0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_GPDMA2_CH0_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpdmaServeInterrupt(STM32_GPDMA2_CHANNEL0); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_GPDMA2_CH1_HANDLER) || defined(__DOXYGEN__) +/** + * @brief GPDMA1 channel 2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_GPDMA2_CH1_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpdmaServeInterrupt(STM32_GPDMA2_CHANNEL1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_GPDMA2_CH2_HANDLER) || defined(__DOXYGEN__) +/** + * @brief GPDMA2 channel 2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_GPDMA2_CH2_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpdmaServeInterrupt(STM32_GPDMA2_CHANNEL2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_GPDMA2_CH3_HANDLER) || defined(__DOXYGEN__) +/** + * @brief GPDMA2 channel 3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_GPDMA2_CH3_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpdmaServeInterrupt(STM32_GPDMA2_CHANNEL3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_GPDMA2_CH4_HANDLER) || defined(__DOXYGEN__) +/** + * @brief GPDMA2 channel 4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_GPDMA2_CH4_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpdmaServeInterrupt(STM32_GPDMA2_CHANNEL4); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_GPDMA2_CH5_HANDLER) || defined(__DOXYGEN__) +/** + * @brief GPDMA2 channel 5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_GPDMA2_CH5_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpdmaServeInterrupt(STM32_GPDMA2_CHANNEL5); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_GPDMA2_CH6_HANDLER) || defined(__DOXYGEN__) +/** + * @brief GPDMA2 channel 6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_GPDMA2_CH6_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpdmaServeInterrupt(STM32_GPDMA2_CHANNEL6); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_GPDMA2_CH7_HANDLER) || defined(__DOXYGEN__) +/** + * @brief GPDMA2 channel 7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_GPDMA2_CH7_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpdmaServeInterrupt(STM32_GPDMA2_CHANNEL7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -318,20 +574,20 @@ void gpdmaChannelFree(const stm32_gpdma_channel_t *dmachp) { * @pre The channel must have been allocated using @p dmaChannelAlloc(). * @post After use the channel can be released using @p dmaChannelRelease(). * - * @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure + * @param[in] dmachp pointer to a @p stm32_gpdma_channel_t structure * * @special */ -void gpdmaChannelSuspend(const stm32_gpdma_channel_t *dmastp) { +void gpdmaChannelSuspend(const stm32_gpdma_channel_t *dmachp) { - osalDbgAssert((dmastp->channel->CCR & STM32_GPDMA_CCR_EN) != 0U, + osalDbgAssert((dmachp->channel->CCR & STM32_GPDMA_CCR_EN) != 0U, "not enabled"); - dmastp->channel->CCR |= STM32_GPDMA_CCR_SUSP; - while ((dmastp->channel->CSR & STM32_GPDMA_CSR_SUSPF) != 0U) { + dmachp->channel->CCR |= STM32_GPDMA_CCR_SUSP; + while ((dmachp->channel->CSR & STM32_GPDMA_CSR_SUSPF) != 0U) { /* Wait completion.*/ } - dmastp->channel->CFCR = STM32_GPDMA_CFCR_SUSPF; + dmachp->channel->CFCR = STM32_GPDMA_CFCR_SUSPF; } /** @@ -344,33 +600,33 @@ void gpdmaChannelSuspend(const stm32_gpdma_channel_t *dmastp) { * @pre The channel must have been allocated using @p dmaChannelAlloc(). * @post After use the channel can be released using @p dmaChannelRelease(). * - * @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure + * @param[in] dmachp pointer to a @p stm32_gpdma_channel_t structure * * @special */ -void gpdmaChannelDisable(const stm32_gpdma_channel_t *dmastp) { +void gpdmaChannelDisable(const stm32_gpdma_channel_t *dmachp) { /* Suspending channel, note, we don't know if it is still active at this point because the EN bit can be reset in HW.*/ - dmastp->channel->CCR |= STM32_GPDMA_CCR_SUSP; + dmachp->channel->CCR |= STM32_GPDMA_CCR_SUSP; /* If the channel was actually active.*/ - if ((dmastp->channel->CCR & STM32_GPDMA_CCR_EN) != 0U) { + if ((dmachp->channel->CCR & STM32_GPDMA_CCR_EN) != 0U) { /* Waiting for completion if suspend operation then resetting the completion flag.*/ - while ((dmastp->channel->CSR & STM32_GPDMA_CSR_SUSPF) != 0U) { + while ((dmachp->channel->CSR & STM32_GPDMA_CSR_SUSPF) != 0U) { /* Wait completion.*/ } - dmastp->channel->CFCR = STM32_GPDMA_CFCR_SUSPF; + dmachp->channel->CFCR = STM32_GPDMA_CFCR_SUSPF; } /* Now resetting the channel.*/ - dmastp->channel->CCR |= STM32_GPDMA_CCR_RESET; - dmastp->channel->CCR = 0U; + dmachp->channel->CCR |= STM32_GPDMA_CCR_RESET; + dmachp->channel->CCR = 0U; /* Clearing all interrupts.*/ - dmastp->channel->CFCR = STM32_GPDMA_CFCR_ALL; + dmachp->channel->CFCR = STM32_GPDMA_CFCR_ALL; } /** diff --git a/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.h b/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.h index 9d03cf3aa..3e4fa91d8 100644 --- a/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.h +++ b/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.h @@ -370,13 +370,13 @@ typedef struct { * @pre The channel must have been allocated using @p dmaStreamAlloc(). * @post After use the channel can be released using @p dmaStreamRelease(). * - * @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure + * @param[in] dmachp pointer to a @p stm32_gpdma_channel_t structure * @param[in] addr value to be written in the CPAR register * * @special */ -#define gpdmaStreamSetPeripheral(dmastp, addr) { \ - (dmastp)->channel->CPAR = (uint32_t)(addr); \ +#define gpdmaStreamSetPeripheral(dmachp, addr) { \ + (dmachp)->channel->CPAR = (uint32_t)(addr); \ } /** @@ -385,13 +385,13 @@ typedef struct { * @pre The channel must have been allocated using @p dmaStreamAlloc(). * @post After use the channel can be released using @p dmaStreamRelease(). * - * @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure + * @param[in] dmachp pointer to a @p stm32_gpdma_channel_t structure * @param[in] addr value to be written in the CMAR register * * @special */ -#define gpdmaStreamSetMemory0(dmastp, addr) { \ - (dmastp)->channel->CMAR = (uint32_t)(addr); \ +#define gpdmaStreamSetMemory0(dmachp, addr) { \ + (dmachp)->channel->CMAR = (uint32_t)(addr); \ } /** @@ -400,13 +400,13 @@ typedef struct { * @pre The channel must have been allocated using @p dmaStreamAlloc(). * @post After use the channel can be released using @p dmaStreamRelease(). * - * @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure + * @param[in] dmachp pointer to a @p stm32_gpdma_channel_t structure * @param[in] size value to be written in the CNDTR register * * @special */ -#define gpdmaStreamSetTransactionSize(dmastp, size) { \ - (dmastp)->channel->CNDTR = (uint32_t)(size); \ +#define gpdmaStreamSetTransactionSize(dmachp, size) { \ + (dmachp)->channel->CNDTR = (uint32_t)(size); \ } /** @@ -415,12 +415,12 @@ typedef struct { * @pre The channel must have been allocated using @p dmaStreamAlloc(). * @post After use the channel can be released using @p dmaStreamRelease(). * - * @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure + * @param[in] dmachp pointer to a @p stm32_gpdma_channel_t structure * @return The number of transfers to be performed. * * @special */ -#define gpdmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) +#define gpdmaStreamGetTransactionSize(dmachp) ((size_t)((dmachp)->channel->CNDTR)) /** * @brief Programs the channel mode settings. @@ -428,13 +428,13 @@ typedef struct { * @pre The channel must have been allocated using @p dmaStreamAlloc(). * @post After use the channel can be released using @p dmaStreamRelease(). * - * @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure + * @param[in] dmachp pointer to a @p stm32_gpdma_channel_t structure * @param[in] mode value to be written in the CCR register * * @special */ -#define gpdmaStreamSetMode(dmastp, mode) { \ - (dmastp)->channel->CCR = (uint32_t)(mode); \ +#define gpdmaStreamSetMode(dmachp, mode) { \ + (dmachp)->channel->CCR = (uint32_t)(mode); \ } /** @@ -443,12 +443,12 @@ typedef struct { * @pre The channel must have been allocated using @p dmaStreamAlloc(). * @post After use the channel can be released using @p dmaStreamRelease(). * - * @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure + * @param[in] dmachp pointer to a @p stm32_gpdma_channel_t structure * * @special */ -#define gpdmaStreamEnable(dmastp) { \ - (dmastp)->channel->CCR |= STM32_GPDMA_CR_EN; \ +#define gpdmaStreamEnable(dmachp) { \ + (dmachp)->channel->CCR |= STM32_GPDMA_CR_EN; \ } /** @@ -461,14 +461,14 @@ typedef struct { * @pre The channel must have been allocated using @p dmaStreamAlloc(). * @post After use the channel can be released using @p dmaStreamRelease(). * - * @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure + * @param[in] dmachp pointer to a @p stm32_gpdma_channel_t structure * * @special */ -#define ______gpdmaStreamDisable(dmastp) { \ - (dmastp)->channel->CCR &= ~(STM32_GPDMA_CR_TCIE | STM32_GPDMA_CR_HTIE | \ +#define ______gpdmaStreamDisable(dmachp) { \ + (dmachp)->channel->CCR &= ~(STM32_GPDMA_CR_TCIE | STM32_GPDMA_CR_HTIE | \ STM32_GPDMA_CR_TEIE | STM32_GPDMA_CR_EN); \ - dmaStreamClearInterrupt(dmastp); \ + dmaStreamClearInterrupt(dmachp); \ } /** @@ -477,12 +477,12 @@ typedef struct { * @pre The channel must have been allocated using @p dmaStreamAlloc(). * @post After use the channel can be released using @p dmaStreamRelease(). * - * @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure + * @param[in] dmachp pointer to a @p stm32_gpdma_channel_t structure * * @special */ -#define gpdmaStreamClearInterrupt(dmastp) { \ - (dmastp)->dma->IFCR = STM32_GPDMA_ISR_MASK << (dmastp)->shift; \ +#define gpdmaStreamClearInterrupt(dmachp) { \ + (dmachp)->dma->IFCR = STM32_GPDMA_ISR_MASK << (dmachp)->shift; \ } /** @@ -492,7 +492,7 @@ typedef struct { * @pre The channel must have been allocated using @p dmaStreamAlloc(). * @post After use the channel can be released using @p dmaStreamRelease(). * - * @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure + * @param[in] dmachp pointer to a @p stm32_gpdma_channel_t structure * @param[in] mode value to be written in the CCR register, this value * is implicitly ORed with: * - @p STM32_GPDMA_CR_MINC @@ -504,11 +504,11 @@ typedef struct { * @param[in] dst destination address * @param[in] n number of data units to copy */ -#define gpdmaStartMemCopy(dmastp, mode, src, dst, n) { \ - dmaStreamSetPeripheral(dmastp, src); \ - dmaStreamSetMemory0(dmastp, dst); \ - dmaStreamSetTransactionSize(dmastp, n); \ - dmaStreamSetMode(dmastp, (mode) | \ +#define gpdmaStartMemCopy(dmachp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmachp, src); \ + dmaStreamSetMemory0(dmachp, dst); \ + dmaStreamSetTransactionSize(dmachp, n); \ + dmaStreamSetMode(dmachp, (mode) | \ STM32_GPDMA_CR_MINC | STM32_GPDMA_CR_PINC | \ STM32_GPDMA_CR_DIR_M2M | STM32_GPDMA_CR_EN); \ } @@ -518,12 +518,12 @@ typedef struct { * @pre The channel must have been allocated using @p dmaStreamAlloc(). * @post After use the channel can be released using @p dmaStreamRelease(). * - * @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure + * @param[in] dmachp pointer to a @p stm32_gpdma_channel_t structure */ -#define gpdmaWaitCompletion(dmastp) { \ - while ((dmastp)->channel->CNDTR > 0U) \ +#define gpdmaWaitCompletion(dmachp) { \ + while ((dmachp)->channel->CNDTR > 0U) \ ; \ - dmaStreamDisable(dmastp); \ + dmaStreamDisable(dmachp); \ } /** @} */ @@ -549,13 +549,76 @@ extern "C" { void *param); void gpdmaChannelFreeI(const stm32_gpdma_channel_t *dmachp); void gpdmaChannelFree(const stm32_gpdma_channel_t *dmachp); - void gpdmaChannelSuspend(const stm32_gpdma_channel_t *dmastp); - void gpdmaChannelDisable(const stm32_gpdma_channel_t *dmastp); + void gpdmaChannelSuspend(const stm32_gpdma_channel_t *dmachp); + void gpdmaChannelDisable(const stm32_gpdma_channel_t *dmachp); void gpdmaServeInterrupt(const stm32_gpdma_channel_t *dmachp); #ifdef __cplusplus } #endif +/*===========================================================================*/ +/* Inline functions. */ +/*===========================================================================*/ + +/** + * @brief Prepares a GPDMA channel for transfer. + * + * @param[in] dmachp pointer to a @p stm32_gpdma_channel_t structure + * @param[in] cr CCR register initialization value + * @param[in] tr1 CTR1 register initialization value + * @param[in] tr2 CTR2 register initialization value + * @param[in] br1 CBR1 register initialization value + * @param[in] sar CSAR register initialization value + * @param[in] dar CDAR register initialization value + * @param[in] tr3 CTR3 register initialization value + * @param[in] br2 CBR2 register initialization value + * @param[in] llr CLLR register initialization value + * + * @api + */ +__STATIC_FORCEINLINE +void gpdmaSetupFullTransfer(const stm32_gpdma_channel_t *dmachp, + uint32_t cr, uint32_t tr1, uint32_t tr2, + uint32_t br1, const void *sar, void *dar, + uint32_t tr3, uint32_t br2, uint32_t llr) { + DMA_Channel_TypeDef *chp; + + /* Associated physical channel.*/ + chp = dmachp->channel; + + chp->CTR1 = tr1; + chp->CTR2 = tr2; + chp->CBR1 = br1; + chp->CSAR = (uint32_t)sar; + chp->CDAR = (uint32_t)dar; + chp->CTR3 = tr3; + chp->CBR2 = br2; + chp->CLLR = llr; + chp->CCR = cr; /* Last, because EN bit.*/ +} + +/** + * @brief Prepares a GPDMA channel for transfer. + * @note Unused channel registers are initialized to zero. + * + * @param[in] dmachp pointer to a @p stm32_gpdma_channel_t structure + * @param[in] cr CCR register initialization value + * @param[in] tr1 CTR1 register initialization value + * @param[in] tr2 CTR2 register initialization value + * @param[in] br1 CBR1 register initialization value + * @param[in] sar CSAR register initialization value + * @param[in] dar CDAR register initialization value + * + * @api + */ +__STATIC_FORCEINLINE +void gpdmaSetupImmediateTransfer(const stm32_gpdma_channel_t *dmachp, + uint32_t cr, uint32_t tr1, uint32_t tr2, + uint32_t br1, const void *sar, void *dar) { + + gpdmaSetupFullTransfer(dmachp, cr, tr1, br1, tr2, sar, dar, 0U, 0U, 0U); +} + #endif /* defined(STM32_GPDMA_REQUIRED) */ #endif /* STM32_GPDMA_H */ diff --git a/os/hal/ports/STM32/STM32H5xx/stm32_isr.h b/os/hal/ports/STM32/STM32H5xx/stm32_isr.h index cd69b7fbc..5dc34f818 100644 --- a/os/hal/ports/STM32/STM32H5xx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32H5xx/stm32_isr.h @@ -85,14 +85,14 @@ #define STM32_GPDMA1_CH5_HANDLER VectorC0 #define STM32_GPDMA1_CH6_HANDLER VectorC4 #define STM32_GPDMA1_CH7_HANDLER VectorC8 -#define STM32_GPDMA2_CH0_HANDLER Vector190 -#define STM32_GPDMA2_CH1_HANDLER Vector194 -#define STM32_GPDMA2_CH2_HANDLER Vector198 -#define STM32_GPDMA2_CH3_HANDLER Vector19C -#define STM32_GPDMA2_CH4_HANDLER Vector1A0 -#define STM32_GPDMA2_CH5_HANDLER Vector1A4 -#define STM32_GPDMA2_CH6_HANDLER Vector1A8 -#define STM32_GPDMA2_CH7_HANDLER Vector1AC +#define STM32_GPDMA2_CH0_HANDLER Vector1A8 +#define STM32_GPDMA2_CH1_HANDLER Vector1AC +#define STM32_GPDMA2_CH2_HANDLER Vector1B0 +#define STM32_GPDMA2_CH3_HANDLER Vector1B4 +#define STM32_GPDMA2_CH4_HANDLER Vector1B8 +#define STM32_GPDMA2_CH5_HANDLER Vector1BC +#define STM32_GPDMA2_CH6_HANDLER Vector1C0 +#define STM32_GPDMA2_CH7_HANDLER Vector1C4 #define STM32_GPDMA1_CH0_NUMBER 27 #define STM32_GPDMA1_CH1_NUMBER 28 @@ -201,13 +201,13 @@ #define STM32_USART3_HANDLER Vector130 #define STM32_UART4_HANDLER Vector134 #define STM32_UART5_HANDLER Vector138 -#define STM32_USART6_HANDLER Vector17C -#define STM32_UART7_HANDLER VectorB0 -#define STM32_UART8_HANDLER VectorB4 -#define STM32_UART9_HANDLER VectorB8 -#define STM32_USART10_HANDLER Vector180 -#define STM32_USART11_HANDLER Vector184 -#define STM32_UART12_HANDLER VectorBC +#define STM32_USART6_HANDLER Vector194 +#define STM32_UART7_HANDLER Vector1C8 +#define STM32_UART8_HANDLER Vector1CC +#define STM32_UART9_HANDLER Vector1D0 +#define STM32_USART10_HANDLER Vector198 +#define STM32_USART11_HANDLER Vector19C +#define STM32_UART12_HANDLER Vector1D4 #define STM32_LPUART1_HANDLER Vector13C #define STM32_USART1_NUMBER 58 diff --git a/os/hal/ports/STM32/STM32H5xx/stm32_registry.h b/os/hal/ports/STM32/STM32H5xx/stm32_registry.h index 434914a9b..d802cc858 100644 --- a/os/hal/ports/STM32/STM32H5xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32H5xx/stm32_registry.h @@ -69,6 +69,8 @@ #define STM32_RCC_PLL3_HAS_R TRUE /* GPDMA attributes.*/ +#define STM32_GPDMA_MEMORY_PORT 0U +#define STM32_GPDMA_PERIPHERAL_PORT 1U #define STM32_GPDMA1_NUM_CHANNELS 8U #define STM32_GPDMA1_MASK_FIFO2 0x0000000FU #define STM32_GPDMA1_MASK_FIFO4 0x00000030U