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Simplified demos using startup definitions (improved). 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15103 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-11-17 14:06:18 +00:00
parent 4a16777b33
commit f12ce2fbaf
3 changed files with 90 additions and 82 deletions
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22
demos/STM32/RT-STM32G474RE-NUCLEO64-SB_HOST_DYNAMIC/main.c
View File

@ -22,11 +22,7 @@
#include "rt_test_root.h"
#include "oslib_test_root.h"
/* Static memory areas used by sandboxes.*/
extern uint8_t __flash1_base__, __flash1_size__,
__flash2_base__, __flash2_size__,
__ram1_base__, __ram1_size__,
__ram2_base__, __ram2_size__;
#include "startup_defs.h"
/* Sandbox 1 configuration.*/
static const sb_config_t sb_config1 = {
@ -34,21 +30,21 @@ static const sb_config_t sb_config1 = {
.data_region = 1U,
.regions = {
[0] = {
{(uint8_t *)&__flash1_base__, (size_t)&__flash1_size__}, false
{STARTUP_FLASH1_BASE, STARTUP_FLASH1_SIZE}, false
},
[1] = {
{(uint8_t *)&__ram1_base__, (size_t)&__ram1_size__}, true
{STARTUP_RAM1_BASE, STARTUP_RAM1_SIZE}, true
}
},
.mpuregs = {
[0] = {
(uint32_t)&__flash1_base__, MPU_RASR_ATTR_AP_RO_RO |
(uint32_t)STARTUP_FLASH1_BASE, MPU_RASR_ATTR_AP_RO_RO |
MPU_RASR_ATTR_CACHEABLE_WT_NWA |
MPU_RASR_SIZE_32K |
MPU_RASR_ENABLE
},
[1] = {
(uint32_t)&__ram1_base__, MPU_RASR_ATTR_AP_RW_RW |
(uint32_t)STARTUP_RAM1_BASE, MPU_RASR_ATTR_AP_RW_RW |
MPU_RASR_ATTR_CACHEABLE_WB_WA |
MPU_RASR_SIZE_4K |
MPU_RASR_ENABLE
@ -65,21 +61,21 @@ static const sb_config_t sb_config2 = {
.data_region = 1U,
.regions = {
[0] = {
{(uint8_t *)&__flash2_base__, (size_t)&__flash2_size__}, false
{STARTUP_FLASH2_BASE, STARTUP_FLASH2_SIZE}, false
},
[1] = {
{(uint8_t *)&__ram2_base__, (size_t)&__ram2_size__}, true
{STARTUP_RAM2_BASE, STARTUP_RAM2_SIZE}, true
}
},
.mpuregs = {
[0] = {
(uint32_t)&__flash2_base__, MPU_RASR_ATTR_AP_RO_RO |
(uint32_t)STARTUP_FLASH2_BASE, MPU_RASR_ATTR_AP_RO_RO |
MPU_RASR_ATTR_CACHEABLE_WT_NWA |
MPU_RASR_SIZE_32K |
MPU_RASR_ENABLE
},
[1] = {
(uint32_t)&__ram2_base__, MPU_RASR_ATTR_AP_RW_RW |
(uint32_t)STARTUP_RAM2_BASE, MPU_RASR_ATTR_AP_RW_RW |
MPU_RASR_ATTR_CACHEABLE_WB_WA |
MPU_RASR_SIZE_4K |
MPU_RASR_ENABLE

14
demos/STM32/RT-STM32G474RE-NUCLEO64-SB_HOST_STATIC/main.c
View File

@ -22,11 +22,7 @@
#include "rt_test_root.h"
#include "oslib_test_root.h"
/* Static memory areas used by sandboxes.*/
extern uint8_t __flash1_base__, __flash1_size__,
__flash2_base__, __flash2_size__,
__ram1_base__, __ram1_size__,
__ram2_base__, __ram2_size__;
#include "startup_defs.h"
/* Sandbox 1 configuration.*/
static const sb_config_t sb_config1 = {
@ -34,10 +30,10 @@ static const sb_config_t sb_config1 = {
.data_region = 1U,
.regions = {
[0] = {
{(uint8_t *)&__flash1_base__, (size_t)&__flash1_size__}, false
{STARTUP_FLASH1_BASE, STARTUP_FLASH1_SIZE}, false
},
[1] = {
{(uint8_t *)&__ram1_base__, (size_t)&__ram1_size__}, true
{STARTUP_RAM1_BASE, STARTUP_RAM1_SIZE}, true
}
},
.stdin_stream = (SandboxStream *)&LPSD1,
@ -51,10 +47,10 @@ static const sb_config_t sb_config2 = {
.data_region = 1U,
.regions = {
[0] = {
{(uint8_t *)&__flash2_base__, (size_t)&__flash2_size__}, false
{STARTUP_FLASH2_BASE, STARTUP_FLASH2_SIZE}, false
},
[1] = {
{(uint8_t *)&__ram2_base__, (size_t)&__ram2_size__}, true
{STARTUP_RAM2_BASE, STARTUP_RAM2_SIZE}, true
}
},
.stdin_stream = (SandboxStream *)&LPSD1,

112
os/common/startup/ARMCMx/compilers/GCC/startup_defs.h
View File

@ -30,39 +30,55 @@
/* Module constants. */
/*===========================================================================*/
#define STARTUP_FLASH0_BASE ((uint32_t)&__flash0_base__)
#define STARTUP_FLASH0_END ((uint32_t)&__flash0_end__)
#define STARTUP_FLASH1_BASE ((uint32_t)&__flash1_base__)
#define STARTUP_FLASH1_END ((uint32_t)&__flash1_end__)
#define STARTUP_FLASH2_BASE ((uint32_t)&__flash2_base__)
#define STARTUP_FLASH2_END ((uint32_t)&__flash2_end__)
#define STARTUP_FLASH3_BASE ((uint32_t)&__flash3_base__)
#define STARTUP_FLASH3_END ((uint32_t)&__flash3_end__)
#define STARTUP_FLASH4_BASE ((uint32_t)&__flash4_base__)
#define STARTUP_FLASH4_END ((uint32_t)&__flash4_end__)
#define STARTUP_FLASH5_BASE ((uint32_t)&__flash5_base__)
#define STARTUP_FLASH5_END ((uint32_t)&__flash5_end__)
#define STARTUP_FLASH6_BASE ((uint32_t)&__flash6_base__)
#define STARTUP_FLASH6_END ((uint32_t)&__flash6_end__)
#define STARTUP_FLASH7_BASE ((uint32_t)&__flash7_base__)
#define STARTUP_FLASH7_END ((uint32_t)&__flash7_end__)
#define STARTUP_FLASH0_BASE ((void *)&__flash0_base__)
#define STARTUP_FLASH1_BASE ((void *)&__flash1_base__)
#define STARTUP_FLASH2_BASE ((void *)&__flash2_base__)
#define STARTUP_FLASH3_BASE ((void *)&__flash3_base__)
#define STARTUP_FLASH4_BASE ((void *)&__flash4_base__)
#define STARTUP_FLASH5_BASE ((void *)&__flash5_base__)
#define STARTUP_FLASH7_BASE ((void *)&__flash7_base__)
#define STARTUP_FLASH6_BASE ((void *)&__flash6_base__)
#define STARTUP_FLASH0_END ((void *)&__flash0_end__)
#define STARTUP_FLASH1_END ((void *)&__flash1_end__)
#define STARTUP_FLASH2_END ((void *)&__flash2_end__)
#define STARTUP_FLASH3_END ((void *)&__flash3_end__)
#define STARTUP_FLASH4_END ((void *)&__flash4_end__)
#define STARTUP_FLASH5_END ((void *)&__flash5_end__)
#define STARTUP_FLASH6_END ((void *)&__flash6_end__)
#define STARTUP_FLASH7_END ((void *)&__flash7_end__)
#define STARTUP_FLASH0_SIZE ((size_t)&__flash0_size__)
#define STARTUP_FLASH1_SIZE ((size_t)&__flash1_size__)
#define STARTUP_FLASH2_SIZE ((size_t)&__flash2_size__)
#define STARTUP_FLASH3_SIZE ((size_t)&__flash3_size__)
#define STARTUP_FLASH4_SIZE ((size_t)&__flash4_size__)
#define STARTUP_FLASH5_SIZE ((size_t)&__flash5_size__)
#define STARTUP_FLASH6_SIZE ((size_t)&__flash6_size__)
#define STARTUP_FLASH7_SIZE ((size_t)&__flash7_size__)
#define STARTUP_RAM0_BASE ((uint32_t)&__ram0_base__)
#define STARTUP_RAM0_END ((uint32_t)&__ram0_end__)
#define STARTUP_RAM1_BASE ((uint32_t)&__ram1_base__)
#define STARTUP_RAM1_END ((uint32_t)&__ram1_end__)
#define STARTUP_RAM2_BASE ((uint32_t)&__ram2_base__)
#define STARTUP_RAM2_END ((uint32_t)&__ram2_end__)
#define STARTUP_RAM3_BASE ((uint32_t)&__ram3_base__)
#define STARTUP_RAM3_END ((uint32_t)&__ram3_end__)
#define STARTUP_RAM4_BASE ((uint32_t)&__ram4_base__)
#define STARTUP_RAM4_END ((uint32_t)&__ram4_end__)
#define STARTUP_RAM5_BASE ((uint32_t)&__ram5_base__)
#define STARTUP_RAM5_END ((uint32_t)&__ram5_end__)
#define STARTUP_RAM6_BASE ((uint32_t)&__ram6_base__)
#define STARTUP_RAM6_END ((uint32_t)&__ram6_end__)
#define STARTUP_RAM7_BASE ((uint32_t)&__ram7_base__)
#define STARTUP_RAM7_END ((uint32_t)&__ram7_end__)
#define STARTUP_RAM0_BASE ((void *)&__ram0_base__)
#define STARTUP_RAM1_BASE ((void *)&__ram1_base__)
#define STARTUP_RAM2_BASE ((void *)&__ram2_base__)
#define STARTUP_RAM3_BASE ((void *)&__ram3_base__)
#define STARTUP_RAM4_BASE ((void *)&__ram4_base__)
#define STARTUP_RAM5_BASE ((void *)&__ram5_base__)
#define STARTUP_RAM6_BASE ((void *)&__ram6_base__)
#define STARTUP_RAM7_BASE ((void *)&__ram7_base__)
#define STARTUP_RAM0_END ((void *)&__ram0_end__)
#define STARTUP_RAM1_END ((void *)&__ram1_end__)
#define STARTUP_RAM2_END ((void *)&__ram2_end__)
#define STARTUP_RAM3_END ((void *)&__ram3_end__)
#define STARTUP_RAM4_END ((void *)&__ram4_end__)
#define STARTUP_RAM5_END ((void *)&__ram5_end__)
#define STARTUP_RAM6_END ((void *)&__ram6_end__)
#define STARTUP_RAM7_END ((void *)&__ram7_end__)
#define STARTUP_RAM0_SIZE ((size_t)&__ram0_size__)
#define STARTUP_RAM1_SIZE ((size_t)&__ram1_size__)
#define STARTUP_RAM2_SIZE ((size_t)&__ram2_size__)
#define STARTUP_RAM3_SIZE ((size_t)&__ram3_size__)
#define STARTUP_RAM4_SIZE ((size_t)&__ram4_size__)
#define STARTUP_RAM5_SIZE ((size_t)&__ram5_size__)
#define STARTUP_RAM6_SIZE ((size_t)&__ram6_size__)
#define STARTUP_RAM7_SIZE ((size_t)&__ram7_size__)
/*===========================================================================*/
/* Module pre-compile time settings. */
@ -84,22 +100,22 @@
/* External declarations. */
/*===========================================================================*/
extern uint32_t __flash0_base__, __flash0_end__;
extern uint32_t __flash1_base__, __flash1_end__;
extern uint32_t __flash2_base__, __flash2_end__;
extern uint32_t __flash3_base__, __flash3_end__;
extern uint32_t __flash4_base__, __flash4_end__;
extern uint32_t __flash5_base__, __flash5_end__;
extern uint32_t __flash6_base__, __flash6_end__;
extern uint32_t __flash7_base__, __flash7_end__;
extern uint32_t __ram0_base__, __ram0_end__;
extern uint32_t __ram1_base__, __ram1_end__;
extern uint32_t __ram2_base__, __ram2_end__;
extern uint32_t __ram3_base__, __ram3_end__;
extern uint32_t __ram4_base__, __ram4_end__;
extern uint32_t __ram5_base__, __ram5_end__;
extern uint32_t __ram6_base__, __ram6_end__;
extern uint32_t __ram7_base__, __ram7_end__;
extern uint8_t __flash0_base__, __flash0_size__, __flash0_end__;
extern uint8_t __flash1_base__, __flash1_size__, __flash1_end__;
extern uint8_t __flash2_base__, __flash2_size__, __flash2_end__;
extern uint8_t __flash3_base__, __flash3_size__, __flash3_end__;
extern uint8_t __flash4_base__, __flash4_size__, __flash4_end__;
extern uint8_t __flash5_base__, __flash5_size__, __flash5_end__;
extern uint8_t __flash6_base__, __flash6_size__, __flash6_end__;
extern uint8_t __flash7_base__, __flash7_size__, __flash7_end__;
extern uint8_t __ram0_base__, __ram0_size__, __ram0_end__;
extern uint8_t __ram1_base__, __ram1_size__, __ram1_end__;
extern uint8_t __ram2_base__, __ram2_size__, __ram2_end__;
extern uint8_t __ram3_base__, __ram3_size__, __ram3_end__;
extern uint8_t __ram4_base__, __ram4_size__, __ram4_end__;
extern uint8_t __ram5_base__, __ram5_size__, __ram5_end__;
extern uint8_t __ram6_base__, __ram6_size__, __ram6_end__;
extern uint8_t __ram7_base__, __ram7_size__, __ram7_end__;
#ifdef __cplusplus
extern "C" {