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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5450 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2013-03-18 10:47:25 +00:00
parent de8293ab3c
commit f24f61dc0e
9 changed files with 246 additions and 216 deletions
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2
os/hal/platforms/STM32F0xx/platform.mk
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@ -8,7 +8,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/pal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/i2c_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c

2
os/hal/platforms/STM32F30x/platform.mk
View File

@ -9,7 +9,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F30x/stm32_dma.c \
${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/pal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/i2c_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c \

231
os/hal/platforms/STM32F37x/adc_lld.c
View File

@ -37,24 +37,6 @@ int debugzero = 0;
/* Driver local definitions. */ /* Driver local definitions. */
/*===========================================================================*/ /*===========================================================================*/
#define ADC1_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN)
#define ADC2_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN)
#define ADC3_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN)
#define SDADC1_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_ADC_SDADC1_DMA_STREAM, STM32_SDADC1_DMA_CHN)
#define SDADC2_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_ADC_SDADC2_DMA_STREAM, STM32_SDADC2_DMA_CHN)
#define SDADC3_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_ADC_SDADC3_DMA_STREAM, STM32_SDADC3_DMA_CHN)
/*===========================================================================*/ /*===========================================================================*/
/* Driver exported variables. */ /* Driver exported variables. */
/*===========================================================================*/ /*===========================================================================*/
@ -90,20 +72,20 @@ ADCDriver SDADCD3;
#endif #endif
/*===========================================================================*/ /*===========================================================================*/
/* Driver local variables. */ /* Driver local variables and types. */
/*===========================================================================*/ /*===========================================================================*/
/*===========================================================================*/ /*===========================================================================*/
/* Driver local functions. */ /* Driver local functions. */
/*===========================================================================*/ /*===========================================================================*/
static bool_t isADCDriverForSigmaDeltaADC(ADCDriver *adcp);
static bool_t isADCDriverForSuccApproxADC(ADCDriver *adcp);
/** /**
* @brief ADC DMA ISR service routine. * @brief ADC DMA ISR service routine.
* *
* @param[in] adcp pointer to the @p ADCDriver object * @param[in] adcp pointer to the @p ADCDriver object
* @param[in] flags pre-shifted content of the ISR register * @param[in] flags pre-shifted content of the ISR register
*
* @notapi
*/ */
static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
/* DMA errors handling.*/ /* DMA errors handling.*/
@ -132,14 +114,13 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
/* Driver interrupt handlers. */ /* Driver interrupt handlers. */
/*===========================================================================*/ /*===========================================================================*/
#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || STM32_ADC_USE_ADC3 || \ #if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
defined(__DOXYGEN__)
/** /**
* @brief ADC interrupt handler. * @brief ADC interrupt handler.
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { CH_IRQ_HANDLER(Vector88) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
#if STM32_ADC_USE_ADC1 #if STM32_ADC_USE_ADC1
@ -165,64 +146,75 @@ void adc_lld_init(void) {
/* Driver initialization.*/ /* Driver initialization.*/
adcObjectInit(&ADCD1); adcObjectInit(&ADCD1);
ADCD1.adc = ADC1; ADCD1.adc = ADC1;
ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM); #if STM32_ADC_USE_SDADC
ADCD1.sdadc = NULL;
#endif
ADCD1.dmastp = STM32_DMA1_STREAM1;
ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) | ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
/* The shared vector is initialized on driver initialization and never
disabled.*/
nvicEnableVector(ADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); nvicEnableVector(ADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
#endif
#if STM32_ADC_USE_SDADC1 #if STM32_ADC_USE_SDADC1
/* Driver initialization.*/ /* Driver initialization.*/
adcObjectInit(&SDADCD1); adcObjectInit(&SDADCD1);
#if STM32_ADC_USE_ADC
SDADCD1.adc = NULL;
#endif
SDADCD1.sdadc = SDADC1; SDADCD1.sdadc = SDADC1;
SDADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_SDADC1_DMA_STREAM); SDADCD1.dmastp = STM32_DMA2_STREAM3;
SDADCD1.dmamode = STM32_DMA_CR_CHSEL(SDADC1_DMA_CHANNEL) | SDADCD1.dmamode = STM32_DMA_CR_CHSEL(SDADC1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_SDADC1_DMA_PRIORITY) | STM32_DMA_CR_PL(STM32_ADC_SDADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
nvicEnableVector(SDADC1_IRQn,
CORTEX_PRIORITY_MASK(STM32_ADC_SDADC1_IRQ_PRIORITY));
#endif #endif
#if STM32_ADC_USE_SDADC2 #if STM32_ADC_USE_SDADC2
/* Driver initialization.*/ /* Driver initialization.*/
adcObjectInit(&SDADCD2); adcObjectInit(&SDADCD2);
#if STM32_ADC_USE_ADC
SDADCD2.adc = NULL;
#endif
SDADCD2.sdadc = SDADC2; SDADCD2.sdadc = SDADC2;
SDADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_SDADC2_DMA_STREAM); SDADCD2.dmastp = STM32_DMA2_STREAM4;
SDADCD2.dmamode = STM32_DMA_CR_CHSEL(SDADC2_DMA_CHANNEL) | SDADCD2.dmamode = STM32_DMA_CR_CHSEL(SDADC2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_SDADC2_DMA_PRIORITY) | STM32_DMA_CR_PL(STM32_ADC_SDADC2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
nvicEnableVector(SDADC2_IRQn,
CORTEX_PRIORITY_MASK(STM32_ADC_SDADC2_IRQ_PRIORITY));
#endif #endif
#if STM32_ADC_USE_SDADC3 #if STM32_ADC_USE_SDADC3
/* Driver initialization.*/ /* Driver initialization.*/
adcObjectInit(&SDADCD3); adcObjectInit(&SDADCD3);
#if STM32_ADC_USE_ADC
SDADCD3.adc = NULL;
#endif
SDADCD3.sdadc = SDADC3; SDADCD3.sdadc = SDADC3;
SDADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_SDADC3_DMA_STREAM); SDADCD3.dmastp = STM32_DMA2_STREAM5;
SDADCD3.dmamode = STM32_DMA_CR_CHSEL(SDADC3_DMA_CHANNEL) | SDADCD3.dmamode = STM32_DMA_CR_CHSEL(SDADC3_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_SDADC3_DMA_PRIORITY) | STM32_DMA_CR_PL(STM32_ADC_SDADC3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
nvicEnableVector(SDADC3_IRQn,
CORTEX_PRIORITY_MASK(STM32_ADC_SDADC3_IRQ_PRIORITY));
#endif #endif
nvicEnableVector(SDADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_SDADC1_IRQ_PRIORITY));
nvicEnableVector(SDADC2_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_SDADC2_IRQ_PRIORITY));
nvicEnableVector(SDADC3_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_SDADC3_IRQ_PRIORITY));
} }
#if 0
/** /**
* @brief Initial config for SDADC peripheral. * @brief Initial config for SDADC peripheral.
* *
@ -289,8 +281,7 @@ void sdadc_lld_start_cr_init_helper(ADCDriver* adcdp,
adcdp->sdadc->CR2 = 0; adcdp->sdadc->CR2 = 0;
adcdp->sdadc->CR2 = SDADC_CR2_ADON; adcdp->sdadc->CR2 = SDADC_CR2_ADON;
} }
#endif
/** /**
* @brief Configures and activates the ADC peripheral. * @brief Configures and activates the ADC peripheral.
@ -329,9 +320,7 @@ void adc_lld_start(ADCDriver *adcdp) {
(stm32_dmaisr_t) adc_lld_serve_rx_interrupt, (stm32_dmaisr_t) adc_lld_serve_rx_interrupt,
&SDADC1->RDATAR, &SDADC1->RDATAR,
RCC_APB2ENR_SDADC1EN); RCC_APB2ENR_SDADC1EN);
rccEnablePWRInterface(FALSE);
PWR->CR |= PWR_CR_SDADC1EN; PWR->CR |= PWR_CR_SDADC1EN;
} }
#endif /* STM32_ADC_USE_SDADC1 */ #endif /* STM32_ADC_USE_SDADC1 */
@ -342,8 +331,6 @@ void adc_lld_start(ADCDriver *adcdp) {
(stm32_dmaisr_t) adc_lld_serve_rx_interrupt, (stm32_dmaisr_t) adc_lld_serve_rx_interrupt,
&SDADC2->RDATAR, &SDADC2->RDATAR,
RCC_APB2ENR_SDADC2EN); RCC_APB2ENR_SDADC2EN);
rccEnablePWRInterface(FALSE);
PWR->CR |= PWR_CR_SDADC2EN; PWR->CR |= PWR_CR_SDADC2EN;
} }
#endif /* STM32_ADC_USE_SDADC2 */ #endif /* STM32_ADC_USE_SDADC2 */
@ -355,11 +342,9 @@ void adc_lld_start(ADCDriver *adcdp) {
(stm32_dmaisr_t) adc_lld_serve_rx_interrupt, (stm32_dmaisr_t) adc_lld_serve_rx_interrupt,
&SDADC3->RDATAR, &SDADC3->RDATAR,
RCC_APB2ENR_SDADC3EN); RCC_APB2ENR_SDADC3EN);
rccEnablePWRInterface(FALSE);
PWR->CR |= PWR_CR_SDADC3EN; PWR->CR |= PWR_CR_SDADC3EN;
} }
#endif /* STM32_ADC_USE_SDADC3 */ #endif /* STM32_ADC_USE_SDADC3 */
} }
} }
@ -375,41 +360,42 @@ void adc_lld_stop(ADCDriver *adcdp) {
/* If in ready state then disables the ADC clock.*/ /* If in ready state then disables the ADC clock.*/
if (adcdp->state == ADC_READY) { if (adcdp->state == ADC_READY) {
dmaStreamRelease(adcdp->dmastp); dmaStreamRelease(adcdp->dmastp);
adcdp->adc->CR1 = 0;
adcdp->adc->CR2 = 0;
#if STM32_ADC_USE_ADC1 #if STM32_ADC_USE_ADC1
if (&ADCD1 == adcdp) if (&ADCD1 == adcdp) {
adcdp->adc->CR1 = 0;
adcdp->adc->CR2 = 0;
rccDisableADC1(FALSE); rccDisableADC1(FALSE);
#endif
#if STM32_ADC_USE_ADC2
if (&ADCD2 == adcdp)
rccDisableADC2(FALSE);
#endif
#if STM32_ADC_USE_ADC3
if (&ADCD3 == adcdp)
rccDisableADC3(FALSE);
#endif
} }
#endif
#if STM32_ADC_USE_SDADC1 #if STM32_ADC_USE_SDADC1
if (&SDADCD1 == adcdp) if (&SDADCD1 == adcdp) {
adcdp->sdadc-CR1 = 0;
adcdp->sdadc-CR2 = 0;
rccDisableSDADC1(FALSE); rccDisableSDADC1(FALSE);
PWR->CR &= ~PWR_CR_SDADC1EN;
}
#endif #endif
#if STM32_ADC_USE_SDADC2 #if STM32_ADC_USE_SDADC2
if (&SDADCD2 == adcdp) if (&SDADCD2 == adcdp) {
adcdp->sdadc-CR1 = 0;
adcdp->sdadc-CR2 = 0;
rccDisableSDADC2(FALSE); rccDisableSDADC2(FALSE);
PWR->CR &= ~PWR_CR_SDADC2EN;
}
#endif #endif
#if STM32_ADC_USE_SDADC3 #if STM32_ADC_USE_SDADC3
if (&SDADCD3 == adcdp) if (&SDADCD3 == adcdp) {
adcdp->sdadc-CR1 = 0;
adcdp->sdadc-CR2 = 0;
rccDisableSDADC3(FALSE); rccDisableSDADC3(FALSE);
PWR->CR &= ~PWR_CR_SDADC3EN;
}
#endif #endif
}
} }
/** /**
@ -421,7 +407,6 @@ void adc_lld_stop(ADCDriver *adcdp) {
*/ */
void adc_lld_start_conversion(ADCDriver *adcdp) { void adc_lld_start_conversion(ADCDriver *adcdp) {
uint32_t mode; uint32_t mode;
const ADCConversionGroup* grpp = adcdp->grpp; const ADCConversionGroup* grpp = adcdp->grpp;
/* DMA setup.*/ /* DMA setup.*/
@ -441,27 +426,34 @@ void adc_lld_start_conversion(ADCDriver *adcdp) {
dmaStreamSetMode(adcdp->dmastp, mode); dmaStreamSetMode(adcdp->dmastp, mode);
dmaStreamEnable(adcdp->dmastp); dmaStreamEnable(adcdp->dmastp);
if (isADCDriverForSuccApproxADC(adcdp)) { #if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
if (adcdp->adc != NULL) {
#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
#if STM32_ADC_USE_ADC
/* ADC setup.*/ /* ADC setup.*/
adcdp->adc->SR = 0; adcdp->adc->SR = 0;
adcdp->adc->SMPR1 = grpp->ll.adc.smpr1; adcdp->adc->SMPR1 = grpp->u.adc.smpr[0];
adcdp->adc->SMPR2 = grpp->ll.adc.smpr2; adcdp->adc->SMPR2 = grpp->u.adc.smpr[1];
adcdp->adc->SQR1 = grpp->ll.adc.sqr1; adcdp->adc->SQR1 = grpp->u.adc.sqr[0] |
adcdp->adc->SQR2 = grpp->ll.adc.sqr2; ADC_SQR1_NUM_CH(grpp->num_channels);
adcdp->adc->SQR3 = grpp->ll.adc.sqr3; adcdp->adc->SQR2 = grpp->u.adc.sqr[1];
adcdp->adc->SQR3 = grpp->u.adc.sqr[2];
/* ADC configuration and start, the start is performed using the method /* ADC configuration and start, the start is performed using the method
specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/ specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
adcdp->adc->CR1 = grpp->ll.adc.cr1 | ADC_CR1_SCAN; adcdp->adc->CR1 = grpp->u.adc.cr1 | ADC_CR1_SCAN;
if ((grpp->ll.adc.cr2 & ADC_CR2_SWSTART) != 0) if ((grpp->u.adc.cr2 & ADC_CR2_SWSTART) != 0)
adcdp->adc->CR2 = grpp->ll.adc.cr2 | ADC_CR2_CONT adcdp->adc->CR2 = grpp->u.adc.cr2 | ADC_CR2_CONT
| ADC_CR2_DMA | ADC_CR2_ADON; | ADC_CR2_DMA | ADC_CR2_ADON;
else else
adcdp->adc->CR2 = grpp->ll.adc.cr2 | ADC_CR2_DMA | ADC_CR2_ADON; adcdp->adc->CR2 = grpp->u.adc.cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
#endif /* STM32_ADC_USE_ADC */
#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
} }
else if (isADCDriverForSigmaDeltaADC(adcdp)) { else if (adcdp->sdadc != NULL) {
/* For Sigma-Delta ADC */ #endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
#if STM32_ADC_USE_SDADC
/* SDADC setup.*/
sdadcSTM32SetInitializationMode(adcdp, true); sdadcSTM32SetInitializationMode(adcdp, true);
/* SDADC setup.*/ /* SDADC setup.*/
@ -477,10 +469,14 @@ void adc_lld_start_conversion(ADCDriver *adcdp) {
specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/ specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
adcdp->sdadc->CR1 = grpp->ll.sdadc.cr1 | SDADC_CR1_RDMAEN; adcdp->sdadc->CR1 = grpp->ll.sdadc.cr1 | SDADC_CR1_RDMAEN;
adcdp->sdadc->CR2 = grpp->ll.sdadc.cr2 | SDADC_CR2_ADON; adcdp->sdadc->CR2 = grpp->ll.sdadc.cr2 | SDADC_CR2_ADON;
#endif /* STM32_ADC_USE_SDADC */
#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
} }
else {
chDbgAssert(FALSE, "adc_lld_start_conversion(), #1", "invalid state");
}
#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
} }
bool_t stopconv = FALSE;
/** /**
* @brief Stops an ongoing conversion. * @brief Stops an ongoing conversion.
@ -490,66 +486,36 @@ bool_t stopconv = FALSE;
* @notapi * @notapi
*/ */
void adc_lld_stop_conversion(ADCDriver *adcdp) { void adc_lld_stop_conversion(ADCDriver *adcdp) {
/* Disabling the associated DMA stream.*/
dmaStreamDisable(adcdp->dmastp); dmaStreamDisable(adcdp->dmastp);
if (isADCDriverForSuccApproxADC(adcdp)) { #if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
if (adcdp->adc != NULL) {
#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
#if STM32_ADC_USE_ADC
adcdp->adc->CR1 = 0; adcdp->adc->CR1 = 0;
adcdp->adc->CR2 = 0; adcdp->adc->CR2 = 0;
adcdp->adc->CR2 = ADC_CR2_ADON; adcdp->adc->CR2 = ADC_CR2_ADON;
#endif /* STM32_ADC_USE_ADC */
#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
} }
else if (isADCDriverForSigmaDeltaADC(adcdp)) { else if (adcdp->sdadc != NULL) {
#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
#if STM32_ADC_USE_SDADC
adcdp->sdadc->CR1 = 0; adcdp->sdadc->CR1 = 0;
adcdp->sdadc->CR2 = 0; adcdp->sdadc->CR2 = 0;
adcdp->sdadc->CR2 = ADC_CR2_ADON; adcdp->sdadc->CR2 = ADC_CR2_ADON;
#endif /* STM32_ADC_USE_SDADC */
#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
} }
else {
chDbgAssert(FALSE, "adc_lld_stop_conversion(), #1", "invalid state");
}
#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
} }
#if 0 #if STM32_ADC_USE_SDADC || defined(__DOXYGEN__)
/**
* @brief Enables the TSVREFE bit.
* @details The TSVREFE bit is required in order to sample the internal
* temperature sensor and internal reference voltage.
* @note This is an STM32-only functionality.
*/
void adcSTM32EnableTSVREFE(void) {
ADC->CCR |= ADC_CCR_TSVREFE;
}
/**
* @brief Disables the TSVREFE bit.
* @details The TSVREFE bit is required in order to sample the internal
* temperature sensor and internal reference voltage.
* @note This is an STM32-only functionality.
*/
void adcSTM32DisableTSVREFE(void) {
ADC->CCR &= ~ADC_CCR_TSVREFE;
}
/**
* @brief Enables the VBATE bit.
* @details The VBATE bit is required in order to sample the VBAT channel.
* @note This is an STM32-only functionality.
* @note This function is meant to be called after @p adcStart().
*/
void adcSTM32EnableVBATE(void) {
ADC->CCR |= ADC_CCR_VBATE;
}
/**
* @brief Disables the VBATE bit.
* @details The VBATE bit is required in order to sample the VBAT channel.
* @note This is an STM32-only functionality.
* @note This function is meant to be called after @p adcStart().
*/
void adcSTM32DisableVBATE(void) {
ADC->CCR &= ~ADC_CCR_VBATE;
}
#endif
/** /**
* @brief Sets the VREF for the 3 Sigma-Delta ADC Converters * @brief Sets the VREF for the 3 Sigma-Delta ADC Converters
* @details VREF can be changed only when all SDADCs are disabled. Disables all SDADCs, sets the value and then sleeps 5 ms waiting for the change to occur. * @details VREF can be changed only when all SDADCs are disabled. Disables all SDADCs, sets the value and then sleeps 5 ms waiting for the change to occur.
@ -697,14 +663,7 @@ void sdadcSTM32Calibrate(ADCDriver* adcdp,
/* cleanup by clearing EOCALF flag */ /* cleanup by clearing EOCALF flag */
adcdp->sdadc->CLRISR |= SDADC_ISR_CLREOCALF; adcdp->sdadc->CLRISR |= SDADC_ISR_CLREOCALF;
} }
#endif /* STM32_ADC_USE_SDADC */
static bool_t isADCDriverForSigmaDeltaADC(ADCDriver *adcdp) {
return (adcdp->sdadc != NULL);
}
static bool_t isADCDriverForSuccApproxADC(ADCDriver *adcdp) {
return (adcdp->adc != NULL);
}
#endif /* HAL_USE_ADC */ #endif /* HAL_USE_ADC */

94
os/hal/platforms/STM32F37x/adc_lld.h
View File

@ -252,6 +252,18 @@
/* Derived constants and error checks. */ /* Derived constants and error checks. */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief At least an ADC unit is in use.
*/
#define STM32_ADC_USE_ADC STM32_ADC_USE_ADC1
/**
* @brief At least an SDADC unit is in use.
*/
#define STM32_ADC_USE_SDADC (STM32_ADC_USE_SDADC1 || \
STM32_ADC_USE_SDADC2 || \
STM32_ADC_USE_SDADC3)
#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 #if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
#error "ADC1 not present in the selected device" #error "ADC1 not present in the selected device"
#endif #endif
@ -268,8 +280,7 @@
#error "SDADC3 not present in the selected device" #error "SDADC3 not present in the selected device"
#endif #endif
#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_SDADC1 && \ #if !STM32_ADC_USE_ADC && !STM32_ADC_USE_SDADC
!STM32_ADC_USE_SDADC2 && !STM32_ADC_USE_SDADC3
#error "ADC driver activated but no ADC/SDADC peripheral assigned" #error "ADC driver activated but no ADC/SDADC peripheral assigned"
#endif #endif
@ -419,6 +430,7 @@ typedef struct {
* is not NULL, then use the sdadc struct. * is not NULL, then use the sdadc struct.
*/ */
union { union {
#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
struct { struct {
/** /**
* @brief ADC CR1 register initialization data. * @brief ADC CR1 register initialization data.
@ -434,33 +446,16 @@ typedef struct {
*/ */
uint32_t cr2; uint32_t cr2;
/** /**
* @brief ADC SMPR1 register initialization data. * @brief ADC SMPRx registers initialization data.
* @details In this field must be specified the sample times for channels
* 10...18.
*/ */
uint32_t smpr1; uint32_t smpr[2];
/** /**
* @brief ADC SMPR2 register initialization data. * @brief ADC SQRx register initialization data.
* @details In this field must be specified the sample times for channels
* 0...9.
*/ */
uint32_t smpr2; uint32_t sqr[3];
/**
* @brief ADC SQR1 register initialization data.
* @details Conversion group sequence 13...16 + sequence length.
*/
uint32_t sqr1;
/**
* @brief ADC SQR2 register initialization data.
* @details Conversion group sequence 7...12.
*/
uint32_t sqr2;
/**
* @brief ADC SQR3 register initialization data.
* @details Conversion group sequence 1...6.
*/
uint32_t sqr3;
} adc; } adc;
#endif /* STM32_ADC_USE_ADC */
#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__)
struct { struct {
/** /**
* @brief SDADC CR2 register initialization data. * @brief SDADC CR2 register initialization data.
@ -494,6 +489,7 @@ typedef struct {
*/ */
uint32_t confchr2; uint32_t confchr2;
} sdadc; } sdadc;
#endif /* STM32_ADC_USE_SDADC */
} u; } u;
} ADCConversionGroup; } ADCConversionGroup;
@ -502,10 +498,14 @@ typedef struct {
* @note It could be empty on some architectures. * @note It could be empty on some architectures.
*/ */
typedef struct { typedef struct {
#if STM32_ADC_USE_SDADC
/** /**
* @brief SDADC CR1 register initialization data. * @brief SDADC CR1 register initialization data.
*/ */
uint32_t cr1; uint32_t cr1;
#else /* !STM32_ADC_USE_SDADC */
uint32_t dummy;
#endif /* !STM32_ADC_USE_SDADC */
} ADCConfig; } ADCConfig;
/** /**
@ -553,15 +553,18 @@ struct ADCDriver {
ADC_DRIVER_EXT_FIELDS ADC_DRIVER_EXT_FIELDS
#endif #endif
/* End of the mandatory fields.*/ /* End of the mandatory fields.*/
#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
/** /**
* @brief Pointer to the ADCx registers block. * @brief Pointer to the ADCx registers block.
*/ */
ADC_TypeDef *adc; ADC_TypeDef *adc;
#endif
#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__)
/** /**
* @brief Pointer to the SDADCx registers block. * @brief Pointer to the SDADCx registers block.
*/ */
SDADC_TypeDef *sdadc; SDADC_TypeDef *sdadc;
#endif
/** /**
* @brief Pointer to associated DMA channel. * @brief Pointer to associated DMA channel.
*/ */
@ -584,13 +587,10 @@ struct ADCDriver {
* @brief Number of channels in a conversion sequence. * @brief Number of channels in a conversion sequence.
*/ */
#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) #define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/
#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ #define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/
#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ #define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/
#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ #define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/
#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ #define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */
#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ #define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */
@ -599,10 +599,12 @@ struct ADCDriver {
#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ #define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/
#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ #define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/
#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ #define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */
#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ #define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */
#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ #define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */
#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ #define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
/** @} */ /** @} */
/** /**
@ -633,18 +635,6 @@ struct ADCDriver {
#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */ #define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */
/** @} */ /** @} */
/**
* @name Channel config settings helper macros
* @{
*/
#define sdadcSTM32Channel1TO7Config(SDADC_Channel, SDADC_Conf) ((uint32_t) (SDADC_Conf << (( SDADC_Channel >> 16) << 2)))
#define sdadcSTM32Channel8Config(SDADC_Channel, SDADC_Conf) ((uint32_t) SDADC_CONF)
#define sdadcSTM32ChannelSelect(SDADC_Channel) ((uint32_t) (SDADC_Channel & 0xffff0000))
/** @} */
/*===========================================================================*/ /*===========================================================================*/
/* External declarations. */ /* External declarations. */
/*===========================================================================*/ /*===========================================================================*/
@ -673,14 +663,12 @@ extern "C" {
void adc_lld_stop(ADCDriver *adcp); void adc_lld_stop(ADCDriver *adcp);
void adc_lld_start_conversion(ADCDriver *adcp); void adc_lld_start_conversion(ADCDriver *adcp);
void adc_lld_stop_conversion(ADCDriver *adcp); void adc_lld_stop_conversion(ADCDriver *adcp);
void adcSTM32EnableTSVREFE(void); #if STM32_ADC_USE_SDADC
void adcSTM32DisableTSVREFE(void);
void adcSTM32EnableVBATE(void);
void adcSTM32DisableVBATE(void);
void sdadcSTM32SetInitializationMode(ADCDriver* adcdp, bool_t enterInitMode); void sdadcSTM32SetInitializationMode(ADCDriver* adcdp, bool_t enterInitMode);
void sdadcSTM32VREFSelect(SDADC_VREF_SEL svs); void sdadcSTM32VREFSelect(SDADC_VREF_SEL svs);
void sdadcSTM32Calibrate(ADCDriver* adcdp, SDADC_NUM_CALIB_SEQ numCalibSequences, void sdadcSTM32Calibrate(ADCDriver* adcdp, SDADC_NUM_CALIB_SEQ numCalibSequences,
ADCConversionGroup* grpp); ADCConversionGroup* grpp);
#endif /* STM32_ADC_USE_SDADC */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

2
os/hal/platforms/STM32F37x/platform.mk
View File

@ -9,7 +9,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F37x/stm32_dma.c \
${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/pal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/i2c_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c \

80
os/hal/platforms/STM32F37x/stm32_rcc.h
View File

@ -368,6 +368,86 @@
#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) #define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
/** @} */ /** @} */
/**
* @name SDADC peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the SDADC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableSDADC1(lp) rccEnableAPB2(RCC_APB2ENR_SDADC1EN, lp)
/**
* @brief Disables the SDADC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableSDADC1(lp) rccDisableAPB2(RCC_APB2ENR_SDADC1EN, lp)
/**
* @brief Resets the SDADC1 peripheral.
*
* @api
*/
#define rccResetSDADC1() rccResetAPB2(RCC_APB2RSTR_SDADC1RST)
/**
* @brief Enables the SDADC2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableSDADC2(lp) rccEnableAPB2(RCC_APB2ENR_SDADC2EN, lp)
/**
* @brief Disables the SDADC2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableSDADC2(lp) rccDisableAPB2(RCC_APB2ENR_SDADC2EN, lp)
/**
* @brief Resets the SDADC2 peripheral.
*
* @api
*/
#define rccResetSDADC2() rccResetAPB2(RCC_APB2RSTR_SDADC2RST)
/**
* @brief Enables the SDADC3 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableSDADC3(lp) rccEnableAPB2(RCC_APB2ENR_SDADC3EN, lp)
/**
* @brief Disables the SDADC3 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableSDADC3(lp) rccDisableAPB2(RCC_APB2ENR_SDADC3EN, lp)
/**
* @brief Resets the SDADC3 peripheral.
*
* @api
*/
#define rccResetSDADC3() rccResetAPB2(RCC_APB2RSTR_SDADC3RST)
/** @} */
/** /**
* @name SPI peripherals specific RCC operations * @name SPI peripherals specific RCC operations
* @{ * @{

22
testhal/STM32F37x/ADC/main.c
View File

@ -61,21 +61,22 @@ static const ADCConversionGroup adcgrpcfg1 = {
ADC_GRP1_NUM_CHANNELS, ADC_GRP1_NUM_CHANNELS,
NULL, NULL,
adcerrorcallback, adcerrorcallback,
0, /* CFGR */ .u.adc = {
ADC_TR(0, 4095), /* TR1 */ 0, /* CR1 */
0, /* CCR */ 0, /* CR2 */
{ /* SMPR[2] */ { /* SMPR[2] */
0, 0,
0 0
}, },
{ /* SQR[4] */ { /* SQR[3] */
ADC_SQR1_SQ1_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN8),
0, 0,
0, 0,
0 0
} }
}
}; };
#if 0
/* /*
* ADC conversion group. * ADC conversion group.
* Mode: Continuous, 16 samples of 8 channels, SW triggered. * Mode: Continuous, 16 samples of 8 channels, SW triggered.
@ -104,6 +105,7 @@ static const ADCConversionGroup adcgrpcfg2 = {
0 0
} }
}; };
#endif
/* /*
* Red LEDs blinker thread, times are in milliseconds. * Red LEDs blinker thread, times are in milliseconds.
@ -114,9 +116,9 @@ static msg_t Thread1(void *arg) {
(void)arg; (void)arg;
chRegSetThreadName("blinker"); chRegSetThreadName("blinker");
while (TRUE) { while (TRUE) {
palSetPad(GPIOE, GPIOE_LED10_RED); palClearPad(GPIOC, GPIOC_LED1);
chThdSleepMilliseconds(500); chThdSleepMilliseconds(500);
palClearPad(GPIOE, GPIOE_LED10_RED); palSetPad(GPIOC, GPIOC_LED1);
chThdSleepMilliseconds(500); chThdSleepMilliseconds(500);
} }
return 0; return 0;
@ -162,14 +164,14 @@ int main(void) {
/* /*
* Starts an ADC continuous conversion. * Starts an ADC continuous conversion.
*/ */
adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH); // adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH);
/* /*
* Normal main() thread activity, in this demo it does nothing. * Normal main() thread activity, in this demo it does nothing.
*/ */
while (TRUE) { while (TRUE) {
if (palReadPad(GPIOA, GPIOA_BUTTON)) { if (palReadPad(GPIOA, GPIOA_WKUP_BUTTON)) {
adcStopConversion(&ADCD1); // adcStopConversion(&ADCD1);
} }
chThdSleepMilliseconds(500); chThdSleepMilliseconds(500);
} }

6
testhal/STM32F37x/ADC/mcuconf.h
View File

@ -67,9 +67,9 @@
* ADC driver system settings. * ADC driver system settings.
*/ */
#define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_USE_SDADC1 TRUE #define STM32_ADC_USE_SDADC1 FALSE
#define STM32_ADC_USE_SDADC2 TRUE #define STM32_ADC_USE_SDADC2 FALSE
#define STM32_ADC_USE_SDADC3 TRUE #define STM32_ADC_USE_SDADC3 FALSE
#define STM32_ADC_SDADC_SLOW_MODE FALSE #define STM32_ADC_SDADC_SLOW_MODE FALSE
#define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_SDADC1_DMA_PRIORITY 2 #define STM32_ADC_SDADC1_DMA_PRIORITY 2

3
testhal/STM32F37x/ADC/readme.txt
View File

@ -8,7 +8,8 @@ The demo runs on an STMicroelectronics STM32373C-EVAL board.
** The Demo ** ** The Demo **
The application demonstrates the use of the STM32F37x ADC/SDADC driver. The application demonstrates the use of the STM32F37x ADC driver on the
ADC peripheral.
** Board Setup ** ** Board Setup **