git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1429 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -42,8 +42,10 @@ typedef enum {
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* @brief PWM logic mode.
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*/
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typedef enum {
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PWM_ACTIVE_HIGH = 0, /**< @brief Idle is logic level 0. */
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PWM_ACTIVE_LOW = 1 /**< @brief Idle is logic level 1. */
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PWM_OUTPUT_DISABLED = 0, /**< @brief Output not driven, callback
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only. */
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PWM_OUTPUT_ACTIVE_HIGH = 1, /**< @brief Idle is logic level 0. */
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PWM_OUTPUT_ACTIVE_LOW = 2 /**< @brief Idle is logic level 1. */
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} pwmmode_t;
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/**
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@ -129,6 +129,16 @@ void _pal_lld_setgroupmode(ioportid_t port,
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0, /* PAL_MODE_INPUT_ANALOG */
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3, /* PAL_MODE_OUTPUT_PUSHPULL, 50MHz.*/
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7, /* PAL_MODE_OUTPUT_OPENDRAIN, 50MHz.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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0xB, /* PAL_MODE_STM32_ALTERNATE_PUSHPULL, 50MHz.*/
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0xF, /* PAL_MODE_STM32_ALTERNATE_OPENDRAIN, 50MHz.*/
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};
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uint32_t mh, ml, crh, crl, cfg;
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unsigned i;
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@ -33,6 +33,16 @@
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/* I/O Ports Types and constants. */
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/*===========================================================================*/
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/**
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* @brief STM32 specific alternate push-pull output mode.
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*/
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#define PAL_MODE_STM32_ALTERNATE_PUSHPULL 16
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/**
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* @brief STM32 specific alternate open-drain output mode.
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*/
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#define PAL_MODE_STM32_ALTERNATE_OPENDRAIN 17
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/**
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* @brief GPIO port setup info.
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*/
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@ -95,7 +95,7 @@ CH_IRQ_HANDLER(VectorAC) {
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CH_IRQ_PROLOGUE();
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sr = TIM1->SR;
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sr = TIM1->SR & TIM1->DIER;
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TIM1->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF | TIM_SR_CC4IF);
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if ((sr & TIM_SR_CC1IF) != 0)
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PWMD1.pd_config->pc_channels[0].pcc_callback();
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@ -160,19 +160,45 @@ void pwm_lld_start(PWMDriver *pwmp) {
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pwmp->pd_tim->PSC = pwmp->pd_config->pc_psc;
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pwmp->pd_tim->CNT = 0;
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pwmp->pd_tim->ARR = pwmp->pd_config->pc_arr;
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ccer = TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E;
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if (pwmp->pd_config->pc_channels[0].pcc_mode == PWM_ACTIVE_LOW)
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/* Output enables and polarities setup.*/
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ccer = 0;
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switch (pwmp->pd_config->pc_channels[0].pcc_mode) {
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case PWM_OUTPUT_ACTIVE_LOW:
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ccer |= TIM_CCER_CC1P;
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if (pwmp->pd_config->pc_channels[1].pcc_mode == PWM_ACTIVE_LOW)
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case PWM_OUTPUT_ACTIVE_HIGH:
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ccer |= TIM_CCER_CC1E;
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default:
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;
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}
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switch (pwmp->pd_config->pc_channels[1].pcc_mode) {
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case PWM_OUTPUT_ACTIVE_LOW:
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ccer |= TIM_CCER_CC2P;
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if (pwmp->pd_config->pc_channels[2].pcc_mode == PWM_ACTIVE_LOW)
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case PWM_OUTPUT_ACTIVE_HIGH:
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ccer |= TIM_CCER_CC2E;
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default:
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;
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}
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switch (pwmp->pd_config->pc_channels[2].pcc_mode) {
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case PWM_OUTPUT_ACTIVE_LOW:
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ccer |= TIM_CCER_CC3P;
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if (pwmp->pd_config->pc_channels[3].pcc_mode == PWM_ACTIVE_LOW)
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case PWM_OUTPUT_ACTIVE_HIGH:
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ccer |= TIM_CCER_CC3E;
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default:
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;
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}
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switch (pwmp->pd_config->pc_channels[3].pcc_mode) {
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case PWM_OUTPUT_ACTIVE_LOW:
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ccer |= TIM_CCER_CC4P;
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case PWM_OUTPUT_ACTIVE_HIGH:
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ccer |= TIM_CCER_CC4E;
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default:
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;
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}
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pwmp->pd_tim->CCER = ccer;
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pwmp->pd_tim->EGR = TIM_EGR_UG; /* Update event. */
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pwmp->pd_tim->SR = 0; /* Clear pending IRQs. */
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pwmp->pd_tim->DIER = pwmp->pd_config->pc_callback == NULL ? 0 : TIM_DIER_UIE;
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pwmp->pd_tim->BDTR = TIM_BDTR_MOE;
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pwmp->pd_tim->CR1 = TIM_CR1_ARPE | TIM_CR1_URS |
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TIM_CR1_CEN; /* Timer configured and started.*/
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}
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@ -187,6 +213,7 @@ void pwm_lld_stop(PWMDriver *pwmp) {
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if (pwmp->pd_state == PWM_READY) {
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stop_channels(pwmp);
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pwmp->pd_tim->CR1 = 0;
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pwmp->pd_tim->BDTR = 0;
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pwmp->pd_tim->DIER = 0;
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#if USE_STM32_PWM1
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@ -3,6 +3,13 @@
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*****************************************************************************
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*** 1.3.6 ***
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- FIX: Fixed missing STM32 PWM low level driver error in platform.mk by
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adding the driver files (bug 2913560).
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- NEW: STM32 PWM driver implementation.
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- NEW: Added custom mode settings to the STM32 PAL driver:
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- PAL_MODE_STM32_ALTERNATE_PUSHPULL
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- PAL_MODE_STM32_ALTERNATE_OPENDRAIN
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- CHANGE: Changes to the PWM driver model, made it simpler.
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*** 1.3.5 ***
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- FIX: Fixed problem with memory core allocator (bug 2912528).
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