Added STM32L496xx/STM32L4A6xx support.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11089 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio
parent
17ed462d6f
commit
f35ebd89d4
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@ -0,0 +1,85 @@
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/*
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ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* STM32L496xG memory setup.
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*/
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MEMORY
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{
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flash0 : org = 0x08000000, len = 1M
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flash1 : org = 0x00000000, len = 0
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flash2 : org = 0x00000000, len = 0
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flash3 : org = 0x00000000, len = 0
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flash4 : org = 0x00000000, len = 0
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flash5 : org = 0x00000000, len = 0
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flash6 : org = 0x00000000, len = 0
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flash7 : org = 0x00000000, len = 0
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ram0 : org = 0x20000000, len = 256k
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ram1 : org = 0x00000000, len = 0
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ram2 : org = 0x00000000, len = 0
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ram3 : org = 0x00000000, len = 0
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ram4 : org = 0x10000000, len = 64k /* This memory also mapped at address 0x20040000 */
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ram5 : org = 0x00000000, len = 0
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ram6 : org = 0x00000000, len = 0
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ram7 : org = 0x00000000, len = 0
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}
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/* For each data/text section two region are defined, a virtual region
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and a load region (_LMA suffix).*/
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/* Flash region to be used for exception vectors.*/
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REGION_ALIAS("VECTORS_FLASH", flash0);
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REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
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/* Flash region to be used for constructors and destructors.*/
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REGION_ALIAS("XTORS_FLASH", flash0);
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REGION_ALIAS("XTORS_FLASH_LMA", flash0);
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/* Flash region to be used for code text.*/
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REGION_ALIAS("TEXT_FLASH", flash0);
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REGION_ALIAS("TEXT_FLASH_LMA", flash0);
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/* Flash region to be used for read only data.*/
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REGION_ALIAS("RODATA_FLASH", flash0);
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REGION_ALIAS("RODATA_FLASH_LMA", flash0);
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/* Flash region to be used for various.*/
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REGION_ALIAS("VARIOUS_FLASH", flash0);
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REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
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/* Flash region to be used for RAM(n) initialization data.*/
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REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
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/* RAM region to be used for Main stack. This stack accommodates the processing
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of all exceptions and interrupts.*/
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REGION_ALIAS("MAIN_STACK_RAM", ram0);
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/* RAM region to be used for the process stack. This is the stack used by
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the main() function.*/
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REGION_ALIAS("PROCESS_STACK_RAM", ram0);
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/* RAM region to be used for data segment.*/
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REGION_ALIAS("DATA_RAM", ram0);
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REGION_ALIAS("DATA_RAM_LMA", flash0);
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/* RAM region to be used for BSS segment.*/
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REGION_ALIAS("BSS_RAM", ram0);
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/* RAM region to be used for the default heap.*/
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REGION_ALIAS("HEAP_RAM", ram0);
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/* Generic rules inclusion.*/
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INCLUDE rules.ld
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@ -48,7 +48,11 @@
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* @note This number does not include the 16 system vectors and must be
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* rounded to a multiple of 8.
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*/
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#if defined(STM32L496xx) || defined(STM32L4A6xx)
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#define CORTEX_NUM_VECTORS 96
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#else
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#define CORTEX_NUM_VECTORS 88
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#endif
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/* The following code is not processed when the file is included from an
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asm module.*/
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@ -59,7 +63,8 @@
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definition compatible with the vendor include file.*/
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#if !defined(STM32L471xx) && !defined(STM32L475xx) && \
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!defined(STM32L476xx) && !defined(STM32L485xx) && \
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!defined (STM32L486xx)
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!defined(STM32L486xx) && !defined(STM32L496xx) && \
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!defined(STM32L4A6xx)
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#include "board.h"
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#endif
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@ -253,12 +253,20 @@ void stm32_clock_init(void) {
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#if STM32_ACTIVATE_PLL || STM32_ACTIVATE_PLLSAI1 || STM32_ACTIVATE_PLLSAI2
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/* PLLM and PLLSRC are common to all PLLs.*/
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#if defined(STM32L496xx) || defined(STM32L4A6xx)
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RCC->PLLCFGR = STM32_PLLPDIV | STM32_PLLR |
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STM32_PLLREN | STM32_PLLQ |
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STM32_PLLQEN | STM32_PLLP |
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STM32_PLLPEN | STM32_PLLN |
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STM32_PLLM | STM32_PLLSRC;
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#else
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RCC->PLLCFGR = STM32_PLLR | STM32_PLLREN |
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STM32_PLLQ | STM32_PLLQEN |
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STM32_PLLP | STM32_PLLPEN |
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STM32_PLLN | STM32_PLLM |
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STM32_PLLSRC;
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#endif
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#endif
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#if STM32_ACTIVATE_PLL
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/* PLL activation.*/
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@ -271,10 +279,17 @@ void stm32_clock_init(void) {
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#if STM32_ACTIVATE_PLLSAI1
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/* PLLSAI1 activation.*/
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#if defined(STM32L496xx) || defined(STM32L4A6xx)
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RCC->PLLSAI1CFGR = STM32_PLLSAI1PDIV | STM32_PLLSAI1R |
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STM32_PLLSAI1REN | STM32_PLLSAI1Q |
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STM32_PLLSAI1QEN | STM32_PLLSAI1P |
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STM32_PLLSAI1PEN | STM32_PLLSAI1N;
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#else
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RCC->PLLSAI1CFGR = STM32_PLLSAI1R | STM32_PLLSAI1REN |
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STM32_PLLSAI1Q | STM32_PLLSAI1QEN |
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STM32_PLLSAI1P | STM32_PLLSAI1PEN |
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STM32_PLLSAI1N;
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#endif
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RCC->CR |= RCC_CR_PLLSAI1ON;
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/* Waiting for PLL lock.*/
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@ -284,9 +299,15 @@ void stm32_clock_init(void) {
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#if STM32_ACTIVATE_PLLSAI2
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/* PLLSAI2 activation.*/
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#if defined(STM32L496xx) || defined(STM32L4A6xx)
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RCC->PLLSAI2CFGR = STM32_PLLSAI2PDIV | STM32_PLLSAI2R |
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STM32_PLLSAI2REN | STM32_PLLSAI2P |
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STM32_PLLSAI2PEN | STM32_PLLSAI2N;
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#else
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RCC->PLLSAI2CFGR = STM32_PLLSAI2R | STM32_PLLSAI2REN |
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STM32_PLLSAI2P | STM32_PLLSAI2PEN |
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STM32_PLLSAI2N;
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#endif
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RCC->CR |= RCC_CR_PLLSAI2ON;
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/* Waiting for PLL lock.*/
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@ -49,10 +49,10 @@
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*/
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#if defined(STM32L432xx) || defined(STM32L471xx) || \
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defined(STM32L475xx) || defined(STM32L476xx) || \
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defined(__DOXYGEN__)
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defined(STM32L496xx) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32L4xx Ultra Low Power"
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#elif defined(STM32L485xx) || defined(STM32L486xx)
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#elif defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx)
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#define PLATFORM_NAME "STM32L4xx Ultra Low Power with Crypto"
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#else
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@ -166,6 +166,7 @@
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#define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */
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#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */
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#define STM32_MCOSEL_LSE (7 << 24) /**< LSE clock on MCO pin. */
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#define STM32_MCOSEL_HSI48 (8 << 24) /**< HSI48 clock on MCO pin. */
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#define STM32_MCOPRE_MASK (7 << 28) /**< MCOPRE field mask. */
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#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */
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@ -1236,6 +1237,18 @@
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#error "invalid STM32_PLLR_VALUE value specified"
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#endif
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#if defined(STM32L496xx) || defined(STM32L4A6xx)
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/**
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* @brief STM32_PLLPDIV field. (Only for STM32L496xx/4A6xx)
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*/
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#if ((STM32_PLLPDIV_VALUE != 1) && (STM32_PLLPDIV_VALUE <= 31)) || \
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defined(__DOXYGEN__)
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#define STM32_PLLPDIV (STM32_PLLPDIV_VALUE << 27)
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#else
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#error "invalid STM32_PLLPDIV_VALUE value specified"
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#endif
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#endif
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/**
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* @brief STM32_PLLPEN field.
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*/
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@ -1527,6 +1540,18 @@
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#error "invalid STM32_PLLSAI1R_VALUE value specified"
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#endif
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#if defined(STM32L496xx) || defined(STM32L4A6xx)
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/**
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* @brief STM32_PLLSAI1PDIV field. (Only for STM32L496xx/4A6xx)
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*/
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#if ((STM32_PLLSAI1PDIV_VALUE != 1) && (STM32_PLLSAI1PDIV_VALUE <= 31)) || \
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defined(__DOXYGEN__)
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#define STM32_PLLSAI1PDIV (STM32_PLLSAI1PDIV_VALUE << 27)
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#else
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#error "invalid STM32_PLLSAI1PDIV_VALUE value specified"
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#endif
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#endif
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/**
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* @brief STM32_PLLSAI1PEN field.
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*/
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@ -1670,6 +1695,18 @@
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#error "invalid STM32_PLLSAI2R_VALUE value specified"
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#endif
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#if defined(STM32L496xx) || defined(STM32L4A6xx)
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/**
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* @brief STM32_PLLSAI2PDIV field. (Only for STM32L496xx/4A6xx)
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*/
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#if ((STM32_PLLSAI2PDIV_VALUE != 1) && (STM32_PLLSAI2PDIV_VALUE <= 31)) || \
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defined(__DOXYGEN__)
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#define STM32_PLLSAI2PDIV (STM32_PLLSAI2PDIV_VALUE << 27)
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#else
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#error "invalid STM32_PLLSAI2PDIV_VALUE value specified"
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#endif
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#endif
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/**
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* @brief STM32_PLLSAI2PEN field.
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*/
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@ -2090,7 +2127,6 @@
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#include "nvic.h"
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#include "stm32_dma.h"
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#include "stm32_rcc.h"
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#include "stm32_isr.h"
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#ifdef __cplusplus
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extern "C" {
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@ -31,6 +31,8 @@
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#elif defined(STM32L476xx)
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#define STM32L476xx
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#elif defined(STM32L496xx)
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#define STM32L496xx
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#else
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#error "STM32L4xx device not specified"
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#endif
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@ -766,6 +768,428 @@
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#endif /* defined(STM32L476xx) */
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/*===========================================================================*/
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/* STM32L496xx. */
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/*===========================================================================*/
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#if defined(STM32L496xx)
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_HANDLER Vector88
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#define STM32_ADC1_NUMBER 18
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 TRUE
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#define STM32_ADC2_HANDLER Vector88
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#define STM32_ADC2_NUMBER 18
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#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_ADC2_DMA_CHN 0x00000000
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#define STM32_HAS_ADC3 TRUE
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#define STM32_ADC3_HANDLER VectorFC
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#define STM32_ADC3_NUMBER 47
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#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_ADC3_DMA_CHN 0x00000000
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 TRUE
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#define STM32_CAN_MAX_FILTERS 14
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#define STM32_CAN1_TX_HANDLER Vector8C
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#define STM32_CAN1_RX0_HANDLER Vector90
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#define STM32_CAN1_RX1_HANDLER Vector94
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#define STM32_CAN1_SCE_HANDLER Vector98
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#define STM32_CAN1_TX_NUMBER 19
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#define STM32_CAN1_RX0_NUMBER 20
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#define STM32_CAN1_RX1_NUMBER 21
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#define STM32_CAN1_SCE_NUMBER 22
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#define STM32_HAS_CAN2 TRUE
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#define STM32_CAN_MAX_FILTERS 14
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#define STM32_CAN2_TX_HANDLER Vector198
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#define STM32_CAN2_RX0_HANDLER Vector19C
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#define STM32_CAN2_RX1_HANDLER Vector1A0
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#define STM32_CAN2_SCE_HANDLER Vector1A4
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#define STM32_CAN2_TX_NUMBER 86
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#define STM32_CAN2_RX0_NUMBER 87
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#define STM32_CAN2_RX1_NUMBER 88
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#define STM32_CAN2_SCE_NUMBER 89
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#define STM32_HAS_CAN3 FALSE
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)|\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_DAC1_CH1_DMA_CHN 0x00003600
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#define STM32_HAS_DAC1_CH2 TRUE
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#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)|\
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_DAC1_CH2_DMA_CHN 0x00035000
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_DMA_SUPPORTS_CSELR TRUE
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#define STM32_DMA1_NUM_CHANNELS 7
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#define STM32_DMA1_CH1_HANDLER Vector6C
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#define STM32_DMA1_CH2_HANDLER Vector70
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#define STM32_DMA1_CH3_HANDLER Vector74
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#define STM32_DMA1_CH4_HANDLER Vector78
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#define STM32_DMA1_CH5_HANDLER Vector7C
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#define STM32_DMA1_CH6_HANDLER Vector80
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#define STM32_DMA1_CH7_HANDLER Vector84
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#define STM32_DMA1_CH1_NUMBER 11
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#define STM32_DMA1_CH2_NUMBER 12
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#define STM32_DMA1_CH3_NUMBER 13
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#define STM32_DMA1_CH4_NUMBER 14
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#define STM32_DMA1_CH5_NUMBER 15
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#define STM32_DMA1_CH6_NUMBER 16
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#define STM32_DMA1_CH7_NUMBER 17
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#define STM32_DMA2_NUM_CHANNELS 7
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#define STM32_DMA2_CH1_HANDLER Vector120
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#define STM32_DMA2_CH2_HANDLER Vector124
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#define STM32_DMA2_CH3_HANDLER Vector128
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#define STM32_DMA2_CH4_HANDLER Vector12C
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#define STM32_DMA2_CH5_HANDLER Vector130
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#define STM32_DMA2_CH6_HANDLER Vector150
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#define STM32_DMA2_CH7_HANDLER Vector154
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#define STM32_DMA2_CH1_NUMBER 56
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#define STM32_DMA2_CH2_NUMBER 57
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#define STM32_DMA2_CH3_NUMBER 58
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#define STM32_DMA2_CH4_NUMBER 59
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#define STM32_DMA2_CH5_NUMBER 60
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#define STM32_DMA2_CH6_NUMBER 68
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#define STM32_DMA2_CH7_NUMBER 69
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_LINES 39
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#define STM32_EXTI_IMR_MASK 0xFF820000U
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#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U
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#define STM32_EXTI_LINE0_HANDLER Vector58
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#define STM32_EXTI_LINE1_HANDLER Vector5C
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#define STM32_EXTI_LINE2_HANDLER Vector60
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#define STM32_EXTI_LINE3_HANDLER Vector64
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#define STM32_EXTI_LINE4_HANDLER Vector68
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#define STM32_EXTI_LINE5_9_HANDLER Vector9C
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#define STM32_EXTI_LINE10_15_HANDLER VectorE0
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#define STM32_EXTI_LINE1635_38_HANDLER Vector44
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#define STM32_EXTI_LINE18_HANDLER VectorE4
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#define STM32_EXTI_LINE19_HANDLER Vector48
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#define STM32_EXTI_LINE20_HANDLER Vector4C
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#define STM32_EXTI_LINE2122_HANDLER Vector140
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#define STM32_EXTI_LINE0_NUMBER 6
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#define STM32_EXTI_LINE1_NUMBER 7
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#define STM32_EXTI_LINE2_NUMBER 8
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#define STM32_EXTI_LINE3_NUMBER 9
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#define STM32_EXTI_LINE4_NUMBER 10
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#define STM32_EXTI_LINE5_9_NUMBER 23
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#define STM32_EXTI_LINE10_15_NUMBER 40
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#define STM32_EXTI_LINE1635_38_NUMBER 1
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#define STM32_EXTI_LINE18_NUMBER 41
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#define STM32_EXTI_LINE19_NUMBER 2
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#define STM32_EXTI_LINE20_NUMBER 3
|
||||
#define STM32_EXTI_LINE2122_NUMBER 64
|
||||
|
||||
/* GPIO attributes.*/
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOF TRUE
|
||||
#define STM32_HAS_GPIOG TRUE
|
||||
#define STM32_HAS_GPIOH TRUE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
#define STM32_HAS_GPIOJ FALSE
|
||||
#define STM32_HAS_GPIOK FALSE
|
||||
#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
|
||||
RCC_AHB2ENR_GPIOBEN | \
|
||||
RCC_AHB2ENR_GPIOCEN | \
|
||||
RCC_AHB2ENR_GPIODEN | \
|
||||
RCC_AHB2ENR_GPIOEEN | \
|
||||
RCC_AHB2ENR_GPIOFEN | \
|
||||
RCC_AHB2ENR_GPIOGEN | \
|
||||
RCC_AHB2ENR_GPIOHEN)
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C1_EVENT_HANDLER VectorBC
|
||||
#define STM32_I2C1_EVENT_NUMBER 31
|
||||
#define STM32_I2C1_ERROR_HANDLER VectorC0
|
||||
#define STM32_I2C1_ERROR_NUMBER 32
|
||||
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 6))
|
||||
#define STM32_I2C1_RX_DMA_CHN 0x03500000
|
||||
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 7))
|
||||
#define STM32_I2C1_TX_DMA_CHN 0x05300000
|
||||
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_I2C2_EVENT_HANDLER VectorC4
|
||||
#define STM32_I2C2_EVENT_NUMBER 33
|
||||
#define STM32_I2C2_ERROR_HANDLER VectorC8
|
||||
#define STM32_I2C2_ERROR_NUMBER 34
|
||||
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_I2C2_RX_DMA_CHN 0x00030000
|
||||
#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_I2C2_TX_DMA_CHN 0x00003000
|
||||
|
||||
#define STM32_HAS_I2C3 TRUE
|
||||
#define STM32_I2C3_EVENT_HANDLER Vector160
|
||||
#define STM32_I2C3_EVENT_NUMBER 72
|
||||
#define STM32_I2C3_ERROR_HANDLER Vector164
|
||||
#define STM32_I2C3_ERROR_NUMBER 73
|
||||
#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
|
||||
#define STM32_I2C3_RX_DMA_CHN 0x00000300
|
||||
#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
|
||||
#define STM32_I2C3_TX_DMA_CHN 0x00000030
|
||||
|
||||
#define STM32_HAS_I2C4 TRUE
|
||||
#define STM32_I2C4_EVENT_HANDLER Vector18C
|
||||
#define STM32_I2C4_EVENT_NUMBER 83
|
||||
#define STM32_I2C4_ERROR_HANDLER Vector190
|
||||
#define STM32_I2C4_ERROR_NUMBER 84
|
||||
#define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
|
||||
#define STM32_I2C4_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
|
||||
#define STM32_I2C4_TX_DMA_CHN 0x00000000
|
||||
|
||||
/* QUADSPI attributes.*/
|
||||
#define STM32_HAS_QUADSPI1 TRUE
|
||||
#define STM32_QUADSPI1_HANDLER Vector15C
|
||||
#define STM32_QUADSPI1_NUMBER 71
|
||||
#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 7))
|
||||
#define STM32_QUADSPI1_DMA_CHN 0x03050000
|
||||
|
||||
/* RTC attributes.*/
|
||||
#define STM32_HAS_RTC TRUE
|
||||
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
||||
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
||||
#define STM32_RTC_NUM_ALARMS 2
|
||||
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
||||
|
||||
/* SDMMC attributes.*/
|
||||
#define STM32_HAS_SDMMC1 TRUE
|
||||
#define STM32_SDMMC1_HANDLER Vector104
|
||||
#define STM32_SDMMC1_NUMBER 49
|
||||
#define STM32_SDC_SDMMC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 5))
|
||||
#define STM32_SDC_SDMMC1_DMA_CHN 0x00077000
|
||||
|
||||
#define STM32_HAS_SDMMC2 FALSE
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI1_SUPPORTS_I2S FALSE
|
||||
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 3))
|
||||
#define STM32_SPI1_RX_DMA_CHN 0x00000410
|
||||
#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 4))
|
||||
#define STM32_SPI1_TX_DMA_CHN 0x00004100
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI2_SUPPORTS_I2S FALSE
|
||||
#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_SPI2_RX_DMA_CHN 0x00001000
|
||||
#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_SPI2_TX_DMA_CHN 0x00010000
|
||||
|
||||
#define STM32_HAS_SPI3 TRUE
|
||||
#define STM32_SPI3_SUPPORTS_I2S FALSE
|
||||
#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
|
||||
#define STM32_SPI3_RX_DMA_CHN 0x00000003
|
||||
#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
|
||||
#define STM32_SPI3_TX_DMA_CHN 0x00000030
|
||||
|
||||
#define STM32_HAS_SPI4 FALSE
|
||||
#define STM32_HAS_SPI5 FALSE
|
||||
#define STM32_HAS_SPI6 FALSE
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_TIM_MAX_CHANNELS 6
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_TIM1_IS_32BITS FALSE
|
||||
#define STM32_TIM1_CHANNELS 4
|
||||
#define STM32_TIM1_UP_HANDLER VectorA4
|
||||
#define STM32_TIM1_CC_HANDLER VectorAC
|
||||
#define STM32_TIM1_UP_NUMBER 25
|
||||
#define STM32_TIM1_CC_NUMBER 27
|
||||
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_TIM2_IS_32BITS TRUE
|
||||
#define STM32_TIM2_CHANNELS 4
|
||||
#define STM32_TIM2_HANDLER VectorB0
|
||||
#define STM32_TIM2_NUMBER 28
|
||||
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_TIM3_IS_32BITS FALSE
|
||||
#define STM32_TIM3_CHANNELS 4
|
||||
#define STM32_TIM3_HANDLER VectorB4
|
||||
#define STM32_TIM3_NUMBER 29
|
||||
|
||||
#define STM32_HAS_TIM4 TRUE
|
||||
#define STM32_TIM4_IS_32BITS FALSE
|
||||
#define STM32_TIM4_CHANNELS 4
|
||||
#define STM32_TIM4_HANDLER VectorB8
|
||||
#define STM32_TIM4_NUMBER 30
|
||||
|
||||
#define STM32_HAS_TIM5 TRUE
|
||||
#define STM32_TIM5_IS_32BITS TRUE
|
||||
#define STM32_TIM5_CHANNELS 4
|
||||
#define STM32_TIM5_HANDLER Vector108
|
||||
#define STM32_TIM5_NUMBER 50
|
||||
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_TIM6_IS_32BITS FALSE
|
||||
#define STM32_TIM6_CHANNELS 0
|
||||
#define STM32_TIM6_HANDLER Vector118
|
||||
#define STM32_TIM6_NUMBER 54
|
||||
|
||||
#define STM32_HAS_TIM7 TRUE
|
||||
#define STM32_TIM7_IS_32BITS FALSE
|
||||
#define STM32_TIM7_CHANNELS 0
|
||||
#define STM32_TIM7_HANDLER Vector11C
|
||||
#define STM32_TIM7_NUMBER 55
|
||||
|
||||
#define STM32_HAS_TIM8 TRUE
|
||||
#define STM32_TIM8_IS_32BITS FALSE
|
||||
#define STM32_TIM8_CHANNELS 6
|
||||
#define STM32_TIM8_UP_HANDLER VectorF0
|
||||
#define STM32_TIM8_CC_HANDLER VectorF8
|
||||
#define STM32_TIM8_UP_NUMBER 44
|
||||
#define STM32_TIM8_CC_NUMBER 46
|
||||
|
||||
#define STM32_HAS_TIM15 TRUE
|
||||
#define STM32_TIM15_IS_32BITS FALSE
|
||||
#define STM32_TIM15_CHANNELS 2
|
||||
#define STM32_TIM15_HANDLER VectorA0
|
||||
#define STM32_TIM15_NUMBER 24
|
||||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 2
|
||||
#define STM32_TIM16_HANDLER VectorA4
|
||||
#define STM32_TIM16_NUMBER 25
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 2
|
||||
#define STM32_TIM17_HANDLER VectorA8
|
||||
#define STM32_TIM17_NUMBER 26
|
||||
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM18 FALSE
|
||||
#define STM32_HAS_TIM19 FALSE
|
||||
#define STM32_HAS_TIM20 FALSE
|
||||
#define STM32_HAS_TIM21 FALSE
|
||||
#define STM32_HAS_TIM22 FALSE
|
||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_USART1_HANDLER VectorD4
|
||||
#define STM32_USART1_NUMBER 37
|
||||
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 7))
|
||||
#define STM32_USART1_RX_DMA_CHN 0x02020000
|
||||
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 6))
|
||||
#define STM32_USART1_TX_DMA_CHN 0x00202000
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_USART2_HANDLER VectorD8
|
||||
#define STM32_USART2_NUMBER 38
|
||||
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_USART2_RX_DMA_CHN 0x00200000
|
||||
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_USART2_TX_DMA_CHN 0x02000000
|
||||
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_USART3_HANDLER VectorDC
|
||||
#define STM32_USART3_NUMBER 39
|
||||
#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
|
||||
#define STM32_USART3_RX_DMA_CHN 0x00000200
|
||||
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
|
||||
#define STM32_USART3_TX_DMA_CHN 0x00000020
|
||||
|
||||
#define STM32_HAS_UART4 TRUE
|
||||
#define STM32_UART4_HANDLER Vector110
|
||||
#define STM32_UART4_NUMBER 52
|
||||
#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5)
|
||||
#define STM32_UART4_RX_DMA_CHN 0x00020000
|
||||
#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 3)
|
||||
#define STM32_UART4_TX_DMA_CHN 0x00000200
|
||||
|
||||
#define STM32_HAS_UART5 TRUE
|
||||
#define STM32_UART5_HANDLER Vector114
|
||||
#define STM32_UART5_NUMBER 53
|
||||
#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2)
|
||||
#define STM32_UART5_RX_DMA_CHN 0x00000020
|
||||
#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1)
|
||||
#define STM32_UART5_TX_DMA_CHN 0x00000002
|
||||
|
||||
#define STM32_HAS_LPUART1 TRUE
|
||||
#define STM32_LPUART1_HANDLER Vector158
|
||||
#define STM32_LPUART1_NUMBER 70
|
||||
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
#define STM32_HAS_UART7 FALSE
|
||||
#define STM32_HAS_UART8 FALSE
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_OTG_STEPPING 2
|
||||
#define STM32_HAS_OTG1 TRUE
|
||||
#define STM32_OTG1_ENDPOINTS 5
|
||||
#define STM32_OTG1_HANDLER Vector14C
|
||||
#define STM32_OTG1_NUMBER 67
|
||||
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
#define STM32_HAS_USB FALSE
|
||||
|
||||
/* IWDG attributes.*/
|
||||
#define STM32_HAS_IWDG TRUE
|
||||
#define STM32_IWDG_IS_WINDOWED TRUE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D TRUE
|
||||
#define STM32_DMA2D_HANDLER Vector1A8
|
||||
#define STM32_DMA2D_NUMBER 90
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC TRUE
|
||||
|
||||
/* CRC attributes.*/
|
||||
#define STM32_HAS_CRC TRUE
|
||||
#define STM32_CRC_PROGRAMMABLE TRUE
|
||||
|
||||
#endif /* defined(STM32L496xx) */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* STM32_REGISTRY_H */
|
||||
|
|
|
|||
|
|
@ -89,6 +89,7 @@
|
|||
*****************************************************************************
|
||||
|
||||
*** Next ***
|
||||
- NEW: Added STM32L496xx/STM32L4A6xx support.
|
||||
- NEW: Added STM32F030x4 support.
|
||||
- NEW: Added a Managed Flash Storage module to the HAL.
|
||||
- NEW: Modified the STM32 OTGv1 driver to work without pump thread, transfers
|
||||
|
|
|
|||
Loading…
Reference in New Issue