diff --git a/demos/STM32/NIL-STM32G474RE-NUCLEO64/cfg/mcuconf.h b/demos/STM32/NIL-STM32G474RE-NUCLEO64/cfg/mcuconf.h
index c89da06ec..05d4e376f 100644
--- a/demos/STM32/NIL-STM32G474RE-NUCLEO64/cfg/mcuconf.h
+++ b/demos/STM32/NIL-STM32G474RE-NUCLEO64/cfg/mcuconf.h
@@ -47,6 +47,20 @@
 #define STM32_PWR_CR2                       (PWR_CR2_PLS_LEV0)
 #define STM32_PWR_CR3                       (PWR_CR3_EIWF)
 #define STM32_PWR_CR4                       (0U)
+#define STM32_PWR_PUCRA                     (0U)
+#define STM32_PWR_PDCRA                     (0U)
+#define STM32_PWR_PUCRB                     (0U)
+#define STM32_PWR_PDCRB                     (0U)
+#define STM32_PWR_PUCRC                     (0U)
+#define STM32_PWR_PDCRC                     (0U)
+#define STM32_PWR_PUCRD                     (0U)
+#define STM32_PWR_PDCRD                     (0U)
+#define STM32_PWR_PUCRE                     (0U)
+#define STM32_PWR_PDCRE                     (0U)
+#define STM32_PWR_PUCRF                     (0U)
+#define STM32_PWR_PDCRF                     (0U)
+#define STM32_PWR_PUCRG                     (0U)
+#define STM32_PWR_PDCRG                     (0U)
 #define STM32_HSI16_ENABLED                 TRUE
 #define STM32_HSI48_ENABLED                 TRUE
 #define STM32_HSE_ENABLED                   TRUE
diff --git a/demos/STM32/RT-STM32G431RB-NUCLEO64/cfg/mcuconf.h b/demos/STM32/RT-STM32G431RB-NUCLEO64/cfg/mcuconf.h
index 3b84b8bd4..53a0d28c0 100644
--- a/demos/STM32/RT-STM32G431RB-NUCLEO64/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32G431RB-NUCLEO64/cfg/mcuconf.h
@@ -45,6 +45,20 @@
 #define STM32_PWR_CR2                       (PWR_CR2_PLS_LEV0)
 #define STM32_PWR_CR3                       (PWR_CR3_EIWF)
 #define STM32_PWR_CR4                       (0U)
+#define STM32_PWR_PUCRA                     (0U)
+#define STM32_PWR_PDCRA                     (0U)
+#define STM32_PWR_PUCRB                     (0U)
+#define STM32_PWR_PDCRB                     (0U)
+#define STM32_PWR_PUCRC                     (0U)
+#define STM32_PWR_PDCRC                     (0U)
+#define STM32_PWR_PUCRD                     (0U)
+#define STM32_PWR_PDCRD                     (0U)
+#define STM32_PWR_PUCRE                     (0U)
+#define STM32_PWR_PDCRE                     (0U)
+#define STM32_PWR_PUCRF                     (0U)
+#define STM32_PWR_PDCRF                     (0U)
+#define STM32_PWR_PUCRG                     (0U)
+#define STM32_PWR_PDCRG                     (0U)
 #define STM32_HSI16_ENABLED                 TRUE
 #define STM32_HSI48_ENABLED                 TRUE
 #define STM32_HSE_ENABLED                   TRUE
diff --git a/demos/STM32/RT-STM32G474RE-DISCOVERY-DPOW1/cfg/mcuconf.h b/demos/STM32/RT-STM32G474RE-DISCOVERY-DPOW1/cfg/mcuconf.h
index 277146211..119e2f05c 100644
--- a/demos/STM32/RT-STM32G474RE-DISCOVERY-DPOW1/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32G474RE-DISCOVERY-DPOW1/cfg/mcuconf.h
@@ -47,6 +47,20 @@
 #define STM32_PWR_CR2                       (PWR_CR2_PLS_LEV0)
 #define STM32_PWR_CR3                       (PWR_CR3_EIWF)
 #define STM32_PWR_CR4                       (0U)
+#define STM32_PWR_PUCRA                     (0U)
+#define STM32_PWR_PDCRA                     (0U)
+#define STM32_PWR_PUCRB                     (0U)
+#define STM32_PWR_PDCRB                     (0U)
+#define STM32_PWR_PUCRC                     (0U)
+#define STM32_PWR_PDCRC                     (0U)
+#define STM32_PWR_PUCRD                     (0U)
+#define STM32_PWR_PDCRD                     (0U)
+#define STM32_PWR_PUCRE                     (0U)
+#define STM32_PWR_PDCRE                     (0U)
+#define STM32_PWR_PUCRF                     (0U)
+#define STM32_PWR_PDCRF                     (0U)
+#define STM32_PWR_PUCRG                     (0U)
+#define STM32_PWR_PDCRG                     (0U)
 #define STM32_HSI16_ENABLED                 TRUE
 #define STM32_HSI48_ENABLED                 TRUE
 #define STM32_HSE_ENABLED                   FALSE
diff --git a/demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h b/demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h
index 6a58afe91..9ad27a6e5 100644
--- a/demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h
@@ -41,12 +41,26 @@
  * HAL driver system settings.
  */
 #define STM32_NO_INIT                       FALSE
-#define STM32_CLOCK_DYNAMIC                 TRUE
+#define STM32_CLOCK_DYNAMIC                 FALSE
 #define STM32_VOS                           STM32_VOS_RANGE1
 #define STM32_PWR_BOOST                     TRUE
 #define STM32_PWR_CR2                       (PWR_CR2_PLS_LEV0)
 #define STM32_PWR_CR3                       (PWR_CR3_EIWF)
 #define STM32_PWR_CR4                       (0U)
+#define STM32_PWR_PUCRA                     (0U)
+#define STM32_PWR_PDCRA                     (0U)
+#define STM32_PWR_PUCRB                     (0U)
+#define STM32_PWR_PDCRB                     (0U)
+#define STM32_PWR_PUCRC                     (0U)
+#define STM32_PWR_PDCRC                     (0U)
+#define STM32_PWR_PUCRD                     (0U)
+#define STM32_PWR_PDCRD                     (0U)
+#define STM32_PWR_PUCRE                     (0U)
+#define STM32_PWR_PDCRE                     (0U)
+#define STM32_PWR_PUCRF                     (0U)
+#define STM32_PWR_PDCRF                     (0U)
+#define STM32_PWR_PUCRG                     (0U)
+#define STM32_PWR_PDCRG                     (0U)
 #define STM32_HSI16_ENABLED                 TRUE
 #define STM32_HSI48_ENABLED                 TRUE
 #define STM32_HSE_ENABLED                   TRUE
diff --git a/demos/various/RT-TEST-Latency/cfg/stm32g474re_nucleo64/mcuconf.h b/demos/various/RT-TEST-Latency/cfg/stm32g474re_nucleo64/mcuconf.h
index c89da06ec..05d4e376f 100644
--- a/demos/various/RT-TEST-Latency/cfg/stm32g474re_nucleo64/mcuconf.h
+++ b/demos/various/RT-TEST-Latency/cfg/stm32g474re_nucleo64/mcuconf.h
@@ -47,6 +47,20 @@
 #define STM32_PWR_CR2                       (PWR_CR2_PLS_LEV0)
 #define STM32_PWR_CR3                       (PWR_CR3_EIWF)
 #define STM32_PWR_CR4                       (0U)
+#define STM32_PWR_PUCRA                     (0U)
+#define STM32_PWR_PDCRA                     (0U)
+#define STM32_PWR_PUCRB                     (0U)
+#define STM32_PWR_PDCRB                     (0U)
+#define STM32_PWR_PUCRC                     (0U)
+#define STM32_PWR_PDCRC                     (0U)
+#define STM32_PWR_PUCRD                     (0U)
+#define STM32_PWR_PDCRD                     (0U)
+#define STM32_PWR_PUCRE                     (0U)
+#define STM32_PWR_PDCRE                     (0U)
+#define STM32_PWR_PUCRF                     (0U)
+#define STM32_PWR_PDCRF                     (0U)
+#define STM32_PWR_PUCRG                     (0U)
+#define STM32_PWR_PDCRG                     (0U)
 #define STM32_HSI16_ENABLED                 TRUE
 #define STM32_HSI48_ENABLED                 TRUE
 #define STM32_HSE_ENABLED                   TRUE
diff --git a/os/hal/ports/STM32/STM32G4xx/hal_lld.c b/os/hal/ports/STM32/STM32G4xx/hal_lld.c
index bf25d3391..f01520c26 100644
--- a/os/hal/ports/STM32/STM32G4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32G4xx/hal_lld.c
@@ -58,8 +58,6 @@ uint32_t SystemCoreClock = STM32_HCLK;
 const halclkcfg_t hal_clkcfg_reset = {
   .pwr_cr1              = PWR_CR1_VOS_0,
   .pwr_cr2              = 0U,
-  .pwr_cr3              = PWR_CR3_EIWF,
-  .pwr_cr4              = 0U,
   .pwr_cr5              = PWR_CR5_R1MODE,
   .rcc_cr               = RCC_CR_HSIKERON | RCC_CR_HSION,
   .rcc_cfgr             = RCC_CFGR_SW_HSI,
@@ -74,8 +72,6 @@ const halclkcfg_t hal_clkcfg_reset = {
 const halclkcfg_t hal_clkcfg_default = {
   .pwr_cr1              = STM32_VOS_RANGE1 | PWR_CR1_DBP,
   .pwr_cr2              = STM32_PWR_CR2,
-  .pwr_cr3              = STM32_PWR_CR3,
-  .pwr_cr4              = STM32_PWR_CR4,
   .pwr_cr5              = STM32_CR5BITS,
   .rcc_cr               = 0U
 #if STM32_HSI16_ENABLED
@@ -525,8 +521,6 @@ bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) {
   /* Final PWR modes.*/
   PWR->CR1 = ccp->pwr_cr1;
   PWR->CR2 = ccp->pwr_cr2;
-  PWR->CR3 = ccp->pwr_cr3;
-  PWR->CR4 = ccp->pwr_cr4;
   PWR->CR5 = ccp->pwr_cr5;
 
   /* Waiting for the correct regulator state.*/
@@ -622,6 +616,24 @@ void stm32_clock_init(void) {
   /* Backup domain made accessible.*/
   PWR->CR1 |= PWR_CR1_DBP;
 
+  /* Static PWR initializations.*/
+  PWR->CR3   = STM32_PWR_CR3;
+  PWR->CR4   = STM32_PWR_CR4;
+  PWR->PUCRA = STM32_PWR_PUCRA;
+  PWR->PDCRA = STM32_PWR_PDCRA;
+  PWR->PUCRB = STM32_PWR_PUCRB;
+  PWR->PDCRB = STM32_PWR_PDCRB;
+  PWR->PUCRC = STM32_PWR_PUCRC;
+  PWR->PDCRC = STM32_PWR_PDCRC;
+  PWR->PUCRD = STM32_PWR_PUCRD;
+  PWR->PDCRD = STM32_PWR_PDCRD;
+  PWR->PUCRE = STM32_PWR_PUCRE;
+  PWR->PDCRE = STM32_PWR_PDCRE;
+  PWR->PUCRF = STM32_PWR_PUCRF;
+  PWR->PDCRF = STM32_PWR_PDCRF;
+  PWR->PUCRG = STM32_PWR_PUCRG;
+  PWR->PDCRG = STM32_PWR_PDCRG;
+
   /* Backup domain reset.*/
   bd_reset();
 
@@ -675,6 +687,20 @@ void stm32_clock_init(void) {
   PWR->CR3 = STM32_PWR_CR3;
   PWR->CR4 = STM32_PWR_CR4;
   PWR->CR5 = STM32_CR5BITS;
+  PWR->PUCRA = STM32_PWR_PUCRA;
+  PWR->PDCRA = STM32_PWR_PDCRA;
+  PWR->PUCRB = STM32_PWR_PUCRB;
+  PWR->PDCRB = STM32_PWR_PDCRB;
+  PWR->PUCRC = STM32_PWR_PUCRC;
+  PWR->PDCRC = STM32_PWR_PDCRC;
+  PWR->PUCRD = STM32_PWR_PUCRD;
+  PWR->PDCRD = STM32_PWR_PDCRD;
+  PWR->PUCRE = STM32_PWR_PUCRE;
+  PWR->PDCRE = STM32_PWR_PDCRE;
+  PWR->PUCRF = STM32_PWR_PUCRF;
+  PWR->PDCRF = STM32_PWR_PDCRF;
+  PWR->PUCRG = STM32_PWR_PUCRG;
+  PWR->PDCRG = STM32_PWR_PDCRG;
 
   /* Backup domain reset.*/
   bd_reset();
@@ -707,7 +733,7 @@ void stm32_clock_init(void) {
 
   /* Set flash WS's for SYSCLK source.*/
   flash_set_acr(FLASH_ACR_DBG_SWEN | FLASH_ACR_DCEN | FLASH_ACR_ICEN   |
-                FLASH_ACR_PRFTEN   | STM32_FLASHBITS;
+                FLASH_ACR_PRFTEN   | STM32_FLASHBITS);
 
   /* Switching to the configured SYSCLK source if it is different from HSI16.*/
 #if STM32_SW != STM32_SW_HSI16
diff --git a/os/hal/ports/STM32/STM32G4xx/hal_lld.h b/os/hal/ports/STM32/STM32G4xx/hal_lld.h
index 5c4430a8c..f31bef6fd 100644
--- a/os/hal/ports/STM32/STM32G4xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32G4xx/hal_lld.h
@@ -329,6 +329,104 @@
 #define STM32_PWR_CR4                       (0U)
 #endif
 
+/**
+ * @brief   PWR PUCRA register initialization value.
+ */
+#if !defined(STM32_PWR_PUCRA) || defined(__DOXYGEN__)
+#define STM32_PWR_PUCRA                     (0U)
+#endif
+
+/**
+ * @brief   PWR PDCRA register initialization value.
+ */
+#if !defined(STM32_PWR_PDCRA) || defined(__DOXYGEN__)
+#define STM32_PWR_PDCRA                     (0U)
+#endif
+
+/**
+ * @brief   PWR PUCRB register initialization value.
+ */
+#if !defined(STM32_PWR_PUCRB) || defined(__DOXYGEN__)
+#define STM32_PWR_PUCRB                     (0U)
+#endif
+
+/**
+ * @brief   PWR PDCRB register initialization value.
+ */
+#if !defined(STM32_PWR_PDCRB) || defined(__DOXYGEN__)
+#define STM32_PWR_PDCRB                     (0U)
+#endif
+
+/**
+ * @brief   PWR PUCRC register initialization value.
+ */
+#if !defined(STM32_PWR_PUCRC) || defined(__DOXYGEN__)
+#define STM32_PWR_PUCRC                     (0U)
+#endif
+
+/**
+ * @brief   PWR PDCRC register initialization value.
+ */
+#if !defined(STM32_PWR_PDCRC) || defined(__DOXYGEN__)
+#define STM32_PWR_PDCRC                     (0U)
+#endif
+
+/**
+ * @brief   PWR PUCRD register initialization value.
+ */
+#if !defined(STM32_PWR_PUCRD) || defined(__DOXYGEN__)
+#define STM32_PWR_PUCRD                     (0U)
+#endif
+
+/**
+ * @brief   PWR PDCRD register initialization value.
+ */
+#if !defined(STM32_PWR_PDCRD) || defined(__DOXYGEN__)
+#define STM32_PWR_PDCRD                     (0U)
+#endif
+
+/**
+ * @brief   PWR PUCRE register initialization value.
+ */
+#if !defined(STM32_PWR_PUCRE) || defined(__DOXYGEN__)
+#define STM32_PWR_PUCRE                     (0U)
+#endif
+
+/**
+ * @brief   PWR PDCRE register initialization value.
+ */
+#if !defined(STM32_PWR_PDCRE) || defined(__DOXYGEN__)
+#define STM32_PWR_PDCRE                     (0U)
+#endif
+
+/**
+ * @brief   PWR PUCRF register initialization value.
+ */
+#if !defined(STM32_PWR_PUCRF) || defined(__DOXYGEN__)
+#define STM32_PWR_PUCRF                     (0U)
+#endif
+
+/**
+ * @brief   PWR PDCRF register initialization value.
+ */
+#if !defined(STM32_PWR_PDCRF) || defined(__DOXYGEN__)
+#define STM32_PWR_PDCRF                     (0U)
+#endif
+
+/**
+ * @brief   PWR PUCRG register initialization value.
+ */
+#if !defined(STM32_PWR_PUCRG) || defined(__DOXYGEN__)
+#define STM32_PWR_PUCRG                     (0U)
+#endif
+
+/**
+ * @brief   PWR PDCRG register initialization value.
+ */
+#if !defined(STM32_PWR_PDCRG) || defined(__DOXYGEN__)
+#define STM32_PWR_PDCRG                     (0U)
+#endif
+
 /**
  * @brief   Enables or disables the HSI16 clock source.
  */
@@ -1598,8 +1696,6 @@ typedef uint32_t halfreq_t;
 typedef struct {
   uint32_t          pwr_cr1;
   uint32_t          pwr_cr2;
-  uint32_t          pwr_cr3;
-  uint32_t          pwr_cr4;
   uint32_t          pwr_cr5;
   uint32_t          rcc_cr;
   uint32_t          rcc_cfgr;
diff --git a/testhal/STM32/multi/ADC/cfg/stm32g474re_nucleo64/mcuconf.h b/testhal/STM32/multi/ADC/cfg/stm32g474re_nucleo64/mcuconf.h
index e128630f6..748ff2791 100644
--- a/testhal/STM32/multi/ADC/cfg/stm32g474re_nucleo64/mcuconf.h
+++ b/testhal/STM32/multi/ADC/cfg/stm32g474re_nucleo64/mcuconf.h
@@ -47,6 +47,20 @@
 #define STM32_PWR_CR2                       (PWR_CR2_PLS_LEV0)
 #define STM32_PWR_CR3                       (PWR_CR3_EIWF)
 #define STM32_PWR_CR4                       (0U)
+#define STM32_PWR_PUCRA                     (0U)
+#define STM32_PWR_PDCRA                     (0U)
+#define STM32_PWR_PUCRB                     (0U)
+#define STM32_PWR_PDCRB                     (0U)
+#define STM32_PWR_PUCRC                     (0U)
+#define STM32_PWR_PDCRC                     (0U)
+#define STM32_PWR_PUCRD                     (0U)
+#define STM32_PWR_PDCRD                     (0U)
+#define STM32_PWR_PUCRE                     (0U)
+#define STM32_PWR_PDCRE                     (0U)
+#define STM32_PWR_PUCRF                     (0U)
+#define STM32_PWR_PDCRF                     (0U)
+#define STM32_PWR_PUCRG                     (0U)
+#define STM32_PWR_PDCRG                     (0U)
 #define STM32_HSI16_ENABLED                 TRUE
 #define STM32_HSI48_ENABLED                 TRUE
 #define STM32_HSE_ENABLED                   TRUE
diff --git a/testhal/STM32/multi/DAC/cfg/stm32g474re_nucleo64/mcuconf.h b/testhal/STM32/multi/DAC/cfg/stm32g474re_nucleo64/mcuconf.h
index 91d50d3c2..44aca2882 100644
--- a/testhal/STM32/multi/DAC/cfg/stm32g474re_nucleo64/mcuconf.h
+++ b/testhal/STM32/multi/DAC/cfg/stm32g474re_nucleo64/mcuconf.h
@@ -47,6 +47,20 @@
 #define STM32_PWR_CR2                       (PWR_CR2_PLS_LEV0)
 #define STM32_PWR_CR3                       (PWR_CR3_EIWF)
 #define STM32_PWR_CR4                       (0U)
+#define STM32_PWR_PUCRA                     (0U)
+#define STM32_PWR_PDCRA                     (0U)
+#define STM32_PWR_PUCRB                     (0U)
+#define STM32_PWR_PDCRB                     (0U)
+#define STM32_PWR_PUCRC                     (0U)
+#define STM32_PWR_PDCRC                     (0U)
+#define STM32_PWR_PUCRD                     (0U)
+#define STM32_PWR_PDCRD                     (0U)
+#define STM32_PWR_PUCRE                     (0U)
+#define STM32_PWR_PDCRE                     (0U)
+#define STM32_PWR_PUCRF                     (0U)
+#define STM32_PWR_PDCRF                     (0U)
+#define STM32_PWR_PUCRG                     (0U)
+#define STM32_PWR_PDCRG                     (0U)
 #define STM32_HSI16_ENABLED                 TRUE
 #define STM32_HSI48_ENABLED                 TRUE
 #define STM32_HSE_ENABLED                   TRUE
diff --git a/testrt/IRQ_STORM/cfg/stm32g474re_nucleo64/mcuconf.h b/testrt/IRQ_STORM/cfg/stm32g474re_nucleo64/mcuconf.h
index 41bc38db4..2bff5f092 100644
--- a/testrt/IRQ_STORM/cfg/stm32g474re_nucleo64/mcuconf.h
+++ b/testrt/IRQ_STORM/cfg/stm32g474re_nucleo64/mcuconf.h
@@ -47,6 +47,20 @@
 #define STM32_PWR_CR2                       (PWR_CR2_PLS_LEV0)
 #define STM32_PWR_CR3                       (PWR_CR3_EIWF)
 #define STM32_PWR_CR4                       (0U)
+#define STM32_PWR_PUCRA                     (0U)
+#define STM32_PWR_PDCRA                     (0U)
+#define STM32_PWR_PUCRB                     (0U)
+#define STM32_PWR_PDCRB                     (0U)
+#define STM32_PWR_PUCRC                     (0U)
+#define STM32_PWR_PDCRC                     (0U)
+#define STM32_PWR_PUCRD                     (0U)
+#define STM32_PWR_PDCRD                     (0U)
+#define STM32_PWR_PUCRE                     (0U)
+#define STM32_PWR_PDCRE                     (0U)
+#define STM32_PWR_PUCRF                     (0U)
+#define STM32_PWR_PDCRF                     (0U)
+#define STM32_PWR_PUCRG                     (0U)
+#define STM32_PWR_PDCRG                     (0U)
 #define STM32_HSI16_ENABLED                 TRUE
 #define STM32_HSI48_ENABLED                 TRUE
 #define STM32_HSE_ENABLED                   TRUE
diff --git a/testrt/VT_STORM/cfg/stm32g474re_nucleo64/mcuconf.h b/testrt/VT_STORM/cfg/stm32g474re_nucleo64/mcuconf.h
index 41bc38db4..2bff5f092 100644
--- a/testrt/VT_STORM/cfg/stm32g474re_nucleo64/mcuconf.h
+++ b/testrt/VT_STORM/cfg/stm32g474re_nucleo64/mcuconf.h
@@ -47,6 +47,20 @@
 #define STM32_PWR_CR2                       (PWR_CR2_PLS_LEV0)
 #define STM32_PWR_CR3                       (PWR_CR3_EIWF)
 #define STM32_PWR_CR4                       (0U)
+#define STM32_PWR_PUCRA                     (0U)
+#define STM32_PWR_PDCRA                     (0U)
+#define STM32_PWR_PUCRB                     (0U)
+#define STM32_PWR_PDCRB                     (0U)
+#define STM32_PWR_PUCRC                     (0U)
+#define STM32_PWR_PDCRC                     (0U)
+#define STM32_PWR_PUCRD                     (0U)
+#define STM32_PWR_PDCRD                     (0U)
+#define STM32_PWR_PUCRE                     (0U)
+#define STM32_PWR_PDCRE                     (0U)
+#define STM32_PWR_PUCRF                     (0U)
+#define STM32_PWR_PDCRF                     (0U)
+#define STM32_PWR_PUCRG                     (0U)
+#define STM32_PWR_PDCRG                     (0U)
 #define STM32_HSI16_ENABLED                 TRUE
 #define STM32_HSI48_ENABLED                 TRUE
 #define STM32_HSE_ENABLED                   TRUE
diff --git a/tools/ftl/processors/conf/mcuconf_stm32g4x1xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32g4x1xx/mcuconf.h.ftl
index 289e5e7cb..c54b05d4a 100644
--- a/tools/ftl/processors/conf/mcuconf_stm32g4x1xx/mcuconf.h.ftl
+++ b/tools/ftl/processors/conf/mcuconf_stm32g4x1xx/mcuconf.h.ftl
@@ -56,6 +56,20 @@
 #define STM32_PWR_CR2                       ${doc.STM32_PWR_CR2!"(PWR_CR2_PLS_LEV0)"}
 #define STM32_PWR_CR3                       ${doc.STM32_PWR_CR3!"(PWR_CR3_EIWF)"}
 #define STM32_PWR_CR4                       ${doc.STM32_PWR_CR4!"(0U)"}
+#define STM32_PWR_PUCRA                     ${doc.STM32_PWR_PUCRA!"(0U)"}
+#define STM32_PWR_PDCRA                     ${doc.STM32_PWR_PDCRA!"(0U)"}
+#define STM32_PWR_PUCRB                     ${doc.STM32_PWR_PUCRB!"(0U)"}
+#define STM32_PWR_PDCRB                     ${doc.STM32_PWR_PDCRB!"(0U)"}
+#define STM32_PWR_PUCRC                     ${doc.STM32_PWR_PUCRC!"(0U)"}
+#define STM32_PWR_PDCRC                     ${doc.STM32_PWR_PDCRC!"(0U)"}
+#define STM32_PWR_PUCRD                     ${doc.STM32_PWR_PUCRD!"(0U)"}
+#define STM32_PWR_PDCRD                     ${doc.STM32_PWR_PDCRD!"(0U)"}
+#define STM32_PWR_PUCRE                     ${doc.STM32_PWR_PUCRE!"(0U)"}
+#define STM32_PWR_PDCRE                     ${doc.STM32_PWR_PDCRE!"(0U)"}
+#define STM32_PWR_PUCRF                     ${doc.STM32_PWR_PUCRF!"(0U)"}
+#define STM32_PWR_PDCRF                     ${doc.STM32_PWR_PDCRF!"(0U)"}
+#define STM32_PWR_PUCRG                     ${doc.STM32_PWR_PUCRG!"(0U)"}
+#define STM32_PWR_PDCRG                     ${doc.STM32_PWR_PDCRG!"(0U)"}
 #define STM32_HSI16_ENABLED                 ${doc.STM32_HSI16_ENABLED!"TRUE"}
 #define STM32_HSI48_ENABLED                 ${doc.STM32_HSI48_ENABLED!"TRUE"}
 #define STM32_HSE_ENABLED                   ${doc.STM32_HSE_ENABLED!"TRUE"}
diff --git a/tools/ftl/processors/conf/mcuconf_stm32g4x4xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32g4x4xx/mcuconf.h.ftl
index 485ea9db0..4f7c171f4 100644
--- a/tools/ftl/processors/conf/mcuconf_stm32g4x4xx/mcuconf.h.ftl
+++ b/tools/ftl/processors/conf/mcuconf_stm32g4x4xx/mcuconf.h.ftl
@@ -58,6 +58,20 @@
 #define STM32_PWR_CR2                       ${doc.STM32_PWR_CR2!"(PWR_CR2_PLS_LEV0)"}
 #define STM32_PWR_CR3                       ${doc.STM32_PWR_CR3!"(PWR_CR3_EIWF)"}
 #define STM32_PWR_CR4                       ${doc.STM32_PWR_CR4!"(0U)"}
+#define STM32_PWR_PUCRA                     ${doc.STM32_PWR_PUCRA!"(0U)"}
+#define STM32_PWR_PDCRA                     ${doc.STM32_PWR_PDCRA!"(0U)"}
+#define STM32_PWR_PUCRB                     ${doc.STM32_PWR_PUCRB!"(0U)"}
+#define STM32_PWR_PDCRB                     ${doc.STM32_PWR_PDCRB!"(0U)"}
+#define STM32_PWR_PUCRC                     ${doc.STM32_PWR_PUCRC!"(0U)"}
+#define STM32_PWR_PDCRC                     ${doc.STM32_PWR_PDCRC!"(0U)"}
+#define STM32_PWR_PUCRD                     ${doc.STM32_PWR_PUCRD!"(0U)"}
+#define STM32_PWR_PDCRD                     ${doc.STM32_PWR_PDCRD!"(0U)"}
+#define STM32_PWR_PUCRE                     ${doc.STM32_PWR_PUCRE!"(0U)"}
+#define STM32_PWR_PDCRE                     ${doc.STM32_PWR_PDCRE!"(0U)"}
+#define STM32_PWR_PUCRF                     ${doc.STM32_PWR_PUCRF!"(0U)"}
+#define STM32_PWR_PDCRF                     ${doc.STM32_PWR_PDCRF!"(0U)"}
+#define STM32_PWR_PUCRG                     ${doc.STM32_PWR_PUCRG!"(0U)"}
+#define STM32_PWR_PDCRG                     ${doc.STM32_PWR_PDCRG!"(0U)"}
 #define STM32_HSI16_ENABLED                 ${doc.STM32_HSI16_ENABLED!"TRUE"}
 #define STM32_HSI48_ENABLED                 ${doc.STM32_HSI48_ENABLED!"TRUE"}
 #define STM32_HSE_ENABLED                   ${doc.STM32_HSE_ENABLED!"TRUE"}