diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_isr.c b/os/hal/ports/STM32/STM32F4xx/stm32_isr.c index eabc5046a..9a3dce6b9 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_isr.c +++ b/os/hal/ports/STM32/STM32F4xx/stm32_isr.c @@ -15,7 +15,7 @@ */ /** - * @file STM32F4xx/stm32_isr.c + * @file STM32F4xx/stm32_isr.h * @brief STM32F4xx ISR handler code. * * @addtogroup STM32F4xx_ISR @@ -212,236 +212,6 @@ OSAL_IRQ_HANDLER(VectorE0) { #endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */ -#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__) -/** - * @brief TIM1-BRK, TIM9 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorA0) { - - OSAL_IRQ_PROLOGUE(); - -#if HAL_USE_GPT -#if STM32_GPT_USE_TIM9 - gpt_lld_serve_interrupt(&GPTD9); -#endif -#endif -#if HAL_USE_ICU -#if STM32_ICU_USE_TIM9 - icu_lld_serve_interrupt(&ICUD9); -#endif -#endif -#if HAL_USE_PWM -#if STM32_PWM_USE_TIM9 - pwm_lld_serve_interrupt(&PWMD9); -#endif -#endif - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief TIM1-UP, TIM10 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorA4) { - - OSAL_IRQ_PROLOGUE(); - -#if HAL_USE_GPT -#if STM32_GPT_USE_TIM1 - gpt_lld_serve_interrupt(&GPTD1); -#endif -#if STM32_GPT_USE_TIM10 - gpt_lld_serve_interrupt(&GPTD10); -#endif -#endif -#if HAL_USE_ICU -#if STM32_ICU_USE_TIM1 - icu_lld_serve_interrupt(&ICUD1); -#endif -#endif -#if HAL_USE_PWM -#if STM32_PWM_USE_TIM1 - pwm_lld_serve_interrupt(&PWMD1); -#endif -#if STM32_PWM_USE_TIM10 - pwm_lld_serve_interrupt(&PWMD10); -#endif -#endif - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief TIM1-TRG-COM, TIM11 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorA8) { - - OSAL_IRQ_PROLOGUE(); - -#if HAL_USE_GPT -#if STM32_GPT_USE_TIM11 - gpt_lld_serve_interrupt(&GPTD11); -#endif -#endif -#if HAL_USE_ICU - /* Not used by ICU.*/ -#endif -#if HAL_USE_PWM -#if STM32_PWM_USE_TIM11 - pwm_lld_serve_interrupt(&PWMD11); -#endif -#endif - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief TIM1-CC interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorAC) { - - OSAL_IRQ_PROLOGUE(); - -#if HAL_USE_GPT - /* Not used by GPT.*/ -#endif -#if HAL_USE_ICU -#if STM32_ICU_USE_TIM1 - icu_lld_serve_interrupt(&ICUD1); -#endif -#endif -#if HAL_USE_PWM -#if STM32_PWM_USE_TIM1 - pwm_lld_serve_interrupt(&PWMD1); -#endif -#endif - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief TIM8-BRK, TIM12 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorEC) { - - OSAL_IRQ_PROLOGUE(); - -#if HAL_USE_GPT -#if STM32_GPT_USE_TIM12 - gpt_lld_serve_interrupt(&GPTD12); -#endif -#endif -#if HAL_USE_ICU -#if STM32_ICU_USE_TIM12 - icu_lld_serve_interrupt(&ICUD12); -#endif -#endif -#if HAL_USE_PWM -#if STM32_PWM_USE_TIM12 - pwm_lld_serve_interrupt(&PWMD12); -#endif -#endif - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief TIM8-UP, TIM13 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorF0) { - - OSAL_IRQ_PROLOGUE(); - -#if HAL_USE_GPT -#if STM32_GPT_USE_TIM8 - gpt_lld_serve_interrupt(&GPTD8); -#endif -#if STM32_GPT_USE_TIM13 - gpt_lld_serve_interrupt(&GPTD13); -#endif -#endif -#if HAL_USE_ICU -#if STM32_ICU_USE_TIM8 - icu_lld_serve_interrupt(&ICUD8); -#endif -#endif -#if HAL_USE_PWM -#if STM32_PWM_USE_TIM8 - pwm_lld_serve_interrupt(&PWMD8); -#endif -#if STM32_PWM_USE_TIM13 - pwm_lld_serve_interrupt(&PWMD13); -#endif -#endif - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief TIM8-TRG-COM, TIM14 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorF4) { - - OSAL_IRQ_PROLOGUE(); - -#if HAL_USE_GPT -#if STM32_GPT_USE_TIM14 - gpt_lld_serve_interrupt(&GPTD14); -#endif -#endif -#if HAL_USE_ICU - /* Not used by ICU.*/ -#endif -#if HAL_USE_PWM -#if STM32_PWM_USE_TIM14 - pwm_lld_serve_interrupt(&PWMD14); -#endif -#endif - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief TIM8-CC interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorF8) { - - OSAL_IRQ_PROLOGUE(); - -#if HAL_USE_GPT - /* Not used by GPT.*/ -#endif -#if HAL_USE_ICU -#if STM32_ICU_USE_TIM8 - icu_lld_serve_interrupt(&ICUD8); -#endif -#endif -#if HAL_USE_PWM -#if STM32_PWM_USE_TIM8 - pwm_lld_serve_interrupt(&PWMD8); -#endif -#endif - - OSAL_IRQ_EPILOGUE(); -} -#endif /* HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM */ - /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -454,23 +224,13 @@ OSAL_IRQ_HANDLER(VectorF8) { void irqInit(void) { #if HAL_USE_PAL - nvicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY); - nvicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY); - nvicEnableVector(EXTI2_IRQn, STM32_IRQ_EXTI2_PRIORITY); - nvicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY); - nvicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY); - nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY); - nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY); -#endif -#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__) - nvicEnableVector(TIM1_BRK_TIM9_IRQn, STM32_IRQ_TIM1_BRK_TIM9_PRIORITY); - nvicEnableVector(TIM1_UP_TIM10_IRQn, STM32_IRQ_TIM1_UP_TIM10_PRIORITY); - nvicEnableVector(TIM1_TRG_COM_TIM11_IRQn, STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY); - nvicEnableVector(TIM1_CC_IRQn, STM32_IRQ_TIM1_CC_PRIORITY); - nvicEnableVector(TIM8_BRK_TIM12_IRQn, STM32_IRQ_TIM8_BRK_TIM12_PRIORITY); - nvicEnableVector(TIM8_UP_TIM13_IRQn, STM32_IRQ_TIM8_UP_TIM13_PRIORITY); - nvicEnableVector(TIM8_TRG_COM_TIM14_IRQn, STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY); - nvicEnableVector(TIM8_CC_IRQn, STM32_IRQ_TIM8_CC_PRIORITY); + nvicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY); + nvicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY); + nvicEnableVector(EXTI2_IRQn, STM32_IRQ_EXTI2_PRIORITY); + nvicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY); + nvicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY); + nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY); + nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY); #endif } @@ -490,16 +250,6 @@ void irqDeinit(void) { nvicDisableVector(EXTI9_5_IRQn); nvicDisableVector(EXTI15_10_IRQn); #endif -#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__) - nvicDisableVector(TIM1_BRK_TIM9_IRQn); - nvicDisableVector(TIM1_UP_TIM10_IRQn); - nvicDisableVector(TIM1_TRG_COM_TIM11_IRQn); - nvicDisableVector(TIM1_CC_IRQn); - nvicDisableVector(TIM8_BRK_TIM12_IRQn); - nvicDisableVector(TIM8_UP_TIM13_IRQn); - nvicDisableVector(TIM8_TRG_COM_TIM14_IRQn); - nvicDisableVector(TIM8_CC_IRQn); -#endif } /** @} */ diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_isr.h b/os/hal/ports/STM32/STM32F4xx/stm32_isr.h index 941917800..483c3fedc 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_isr.h @@ -33,14 +33,157 @@ * @name ISR names and numbers remapping * @{ */ -#define STM32_TIM1_SUPPRESS_ISR -#define STM32_TIM9_SUPPRESS_ISR -#define STM32_TIM10_SUPPRESS_ISR -#define STM32_TIM11_SUPPRESS_ISR -#define STM32_TIM8_SUPPRESS_ISR -#define STM32_TIM12_SUPPRESS_ISR -#define STM32_TIM13_SUPPRESS_ISR -#define STM32_TIM14_SUPPRESS_ISR +/* + * CAN units. + */ +#define STM32_CAN1_TX_HANDLER Vector8C +#define STM32_CAN1_RX0_HANDLER Vector90 +#define STM32_CAN1_RX1_HANDLER Vector94 +#define STM32_CAN1_SCE_HANDLER Vector98 +#define STM32_CAN2_TX_HANDLER Vector13C +#define STM32_CAN2_RX0_HANDLER Vector140 +#define STM32_CAN2_RX1_HANDLER Vector144 +#define STM32_CAN2_SCE_HANDLER Vector148 + +#define STM32_CAN1_TX_NUMBER 19 +#define STM32_CAN1_RX0_NUMBER 20 +#define STM32_CAN1_RX1_NUMBER 21 +#define STM32_CAN1_SCE_NUMBER 22 +#define STM32_CAN2_TX_NUMBER 63 +#define STM32_CAN2_RX0_NUMBER 64 +#define STM32_CAN2_RX1_NUMBER 65 +#define STM32_CAN2_SCE_NUMBER 66 + +/* + * I2C units. + */ +#define STM32_I2C1_EVENT_HANDLER VectorBC +#define STM32_I2C1_ERROR_HANDLER VectorC0 +#define STM32_I2C1_EVENT_NUMBER 31 +#define STM32_I2C1_ERROR_NUMBER 32 + +#define STM32_I2C2_EVENT_HANDLER VectorC4 +#define STM32_I2C2_ERROR_HANDLER VectorC8 +#define STM32_I2C2_EVENT_NUMBER 33 +#define STM32_I2C2_ERROR_NUMBER 34 + +#define STM32_I2C3_EVENT_HANDLER Vector160 +#define STM32_I2C3_ERROR_HANDLER Vector164 +#define STM32_I2C3_EVENT_NUMBER 72 +#define STM32_I2C3_ERROR_NUMBER 73 + +/* + * OTG units. + */ +#define STM32_OTG1_HANDLER Vector14C +#define STM32_OTG2_HANDLER Vector174 +#define STM32_OTG2_EP1OUT_HANDLER Vector168 +#define STM32_OTG2_EP1IN_HANDLER Vector16C + +#define STM32_OTG1_NUMBER 67 +#define STM32_OTG2_NUMBER 77 +#define STM32_OTG2_EP1OUT_NUMBER 74 +#define STM32_OTG2_EP1IN_NUMBER 75 + +/* + * SDIO unit. + */ +#define STM32_SDIO_HANDLER Vector104 + +#define STM32_SDIO_NUMBER 49 + +/* + * TIM units. + */ +#define STM32_TIM1_UP_HANDLER VectorA4 +#define STM32_TIM1_CC_HANDLER VectorAC +#define STM32_TIM2_HANDLER VectorB0 +#define STM32_TIM3_HANDLER VectorB4 +#define STM32_TIM4_HANDLER VectorB8 +#define STM32_TIM5_HANDLER Vector108 +#define STM32_TIM6_HANDLER Vector118 +#define STM32_TIM7_HANDLER Vector11C +#define STM32_TIM8_UP_HANDLER VectorF0 +#define STM32_TIM8_CC_HANDLER VectorF8 +#define STM32_TIM9_HANDLER VectorA0 +#define STM32_TIM10_HANDLER VectorA4 /* Note: same as STM32_TIM1_UP */ +#define STM32_TIM11_HANDLER VectorA8 +#define STM32_TIM12_HANDLER VectorEC +#define STM32_TIM13_HANDLER VectorF0 /* Note: same as STM32_TIM8_UP */ +#define STM32_TIM14_HANDLER VectorF4 + +#define STM32_TIM1_UP_NUMBER 25 +#define STM32_TIM1_CC_NUMBER 27 +#define STM32_TIM2_NUMBER 28 +#define STM32_TIM3_NUMBER 29 +#define STM32_TIM4_NUMBER 30 +#define STM32_TIM5_NUMBER 50 +#define STM32_TIM6_NUMBER 54 +#define STM32_TIM7_NUMBER 55 +#define STM32_TIM8_UP_NUMBER 44 +#define STM32_TIM8_CC_NUMBER 46 +#define STM32_TIM9_NUMBER 24 +#define STM32_TIM10_NUMBER 25 /* Note: same as STM32_TIM1_UP */ +#define STM32_TIM11_NUMBER 26 +#define STM32_TIM12_NUMBER 43 +#define STM32_TIM13_NUMBER 44 /* Note: same as STM32_TIM8_UP */ +#define STM32_TIM14_NUMBER 45 + +/* + * LPTIM units. + */ +#define STM32_LPTIM1_HANDLER Vector1C4 + +#define STM32_LPTIM1_NUMBER 97 +/* + * USART units. + */ +#define STM32_USART1_HANDLER VectorD4 +#define STM32_USART2_HANDLER VectorD8 +#define STM32_USART3_HANDLER VectorDC +#define STM32_UART4_HANDLER Vector110 +#define STM32_UART5_HANDLER Vector114 +#define STM32_USART6_HANDLER Vector15C +#define STM32_UART7_HANDLER Vector188 +#define STM32_UART8_HANDLER Vector18C + +#define STM32_USART1_NUMBER 37 +#define STM32_USART2_NUMBER 38 +#define STM32_USART3_NUMBER 39 +#define STM32_UART4_NUMBER 52 +#define STM32_UART5_NUMBER 53 +#define STM32_USART6_NUMBER 71 +#define STM32_UART7_NUMBER 82 +#define STM32_UART8_NUMBER 83 + +/* + * Ethernet + */ +#define ETH_IRQHandler Vector134 + +/* + * FSMC + */ +#define STM32_FSMC_HANDLER Vector100 + +#define STM32_FSMC_NUMBER 48 + +/* + * LTDC + */ +#define STM32_LTDC_EV_HANDLER Vector1A0 +#define STM32_LTDC_ER_HANDLER Vector1A4 + +#define STM32_LTDC_EV_NUMBER 88 +#define STM32_LTDC_ER_NUMBER 89 + +/* + * DMA2D + */ +#define STM32_DMA2D_HANDLER Vector1A8 + +#define STM32_DMA2D_NUMBER 90 + /** @} */ /*===========================================================================*/ @@ -99,139 +242,12 @@ #if !defined(STM32_IRQ_EXTI10_15_PRIORITY) || defined(__DOXYGEN__) #define STM32_IRQ_EXTI10_15_PRIORITY 6 #endif - -/** - * @brief EXTI16 interrupt priority level setting. - */ -#if !defined(STM32_IRQ_EXTI16_PRIORITY) || defined(__DOXYGEN__) -#define STM32_IRQ_EXTI16_PRIORITY 6 -#endif - -/** - * @brief EXTI17 interrupt priority level setting. - */ -#if !defined(STM32_IRQ_EXTI17_PRIORITY) || defined(__DOXYGEN__) -#define STM32_IRQ_EXTI17_PRIORITY 6 -#endif - -/** - * @brief EXTI18 interrupt priority level setting. - */ -#if !defined(STM32_IRQ_EXTI18_PRIORITY) || defined(__DOXYGEN__) -#define STM32_IRQ_EXTI18_PRIORITY 6 -#endif - -/** - * @brief EXTI21 interrupt priority level setting. - */ -#if !defined(STM32_IRQ_EXTI21_PRIORITY) || defined(__DOXYGEN__) -#define STM32_IRQ_EXTI21_PRIORITY 6 -#endif - -/** - * @brief EXTI22 interrupt priority level setting. - */ -#if !defined(STM32_IRQ_EXTI22_PRIORITY) || defined(__DOXYGEN__) -#define STM32_IRQ_EXTI22_PRIORITY 6 -#endif - -/** - * @brief EXTI23 interrupt priority level setting. - */ -#if !defined(STM32_IRQ_EXTI23_PRIORITY) || defined(__DOXYGEN__) -#define STM32_IRQ_EXTI23_PRIORITY 6 -#endif /** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ -/* IRQ priority checks.*/ -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI0_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI0_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI1_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI1_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI2_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI2_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI3_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI3_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI4_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI4_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI5_9_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI5_9_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI10_15_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI10_15_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI16_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI16_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI17_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI17_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI18_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI18_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI21_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI21_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI22_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI22_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI23_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI23_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_BRK_TIM9_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_BRK_TIM9_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_UP_TIM10_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_UP_TIM10_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_CC_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_CC_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_BRK_TIM12_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_BRK_TIM12_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_UP_TIM13_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_UP_TIM13_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_TRGCO_TIM14_PRIORITY" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_CC_PRIORITY) -#error "Invalid IRQ priority assigned to STM32_IRQ_TIM8_CC_PRIORITY" -#endif - /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index 2e640eeab..8d754c690 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -160,27 +160,8 @@ /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE -#define STM32_CAN1_TX_HANDLER Vector8C -#define STM32_CAN1_RX0_HANDLER Vector90 -#define STM32_CAN1_RX1_HANDLER Vector94 -#define STM32_CAN1_SCE_HANDLER Vector98 -#define STM32_CAN1_TX_NUMBER 19 -#define STM32_CAN1_RX0_NUMBER 20 -#define STM32_CAN1_RX1_NUMBER 21 -#define STM32_CAN1_SCE_NUMBER 22 - #define STM32_HAS_CAN2 TRUE -#define STM32_CAN2_TX_HANDLER Vector13C -#define STM32_CAN2_RX0_HANDLER Vector140 -#define STM32_CAN2_RX1_HANDLER Vector144 -#define STM32_CAN2_SCE_HANDLER Vector148 -#define STM32_CAN2_TX_NUMBER 63 -#define STM32_CAN2_RX0_NUMBER 64 -#define STM32_CAN2_RX1_NUMBER 65 -#define STM32_CAN2_SCE_NUMBER 66 - #define STM32_HAS_CAN3 FALSE - #define STM32_CAN_MAX_FILTERS 28 /* DAC attributes.*/ @@ -272,10 +253,6 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_EVENT_HANDLER VectorBC -#define STM32_I2C1_ERROR_HANDLER VectorC0 -#define STM32_I2C1_EVENT_NUMBER 31 -#define STM32_I2C1_ERROR_NUMBER 32 #define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ STM32_DMA_STREAM_ID_MSK(1, 5)) #define STM32_I2C1_RX_DMA_CHN 0x00100001 @@ -284,10 +261,6 @@ #define STM32_I2C1_TX_DMA_CHN 0x11000000 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_EVENT_HANDLER VectorC4 -#define STM32_I2C2_ERROR_HANDLER VectorC8 -#define STM32_I2C2_EVENT_NUMBER 33 -#define STM32_I2C2_ERROR_NUMBER 34 #define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ STM32_DMA_STREAM_ID_MSK(1, 3)) #define STM32_I2C2_RX_DMA_CHN 0x00007700 @@ -295,10 +268,6 @@ #define STM32_I2C2_TX_DMA_CHN 0x70000000 #define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_EVENT_HANDLER Vector160 -#define STM32_I2C3_ERROR_HANDLER Vector164 -#define STM32_I2C3_EVENT_NUMBER 72 -#define STM32_I2C3_ERROR_NUMBER 73 #define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_I2C3_RX_DMA_CHN 0x00000300 #define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) @@ -315,16 +284,12 @@ /* SDIO attributes.*/ #define STM32_HAS_SDIO TRUE -#define STM32_SDIO_HANDLER Vector104 -#define STM32_SDIO_NUMBER 49 #define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ STM32_DMA_STREAM_ID_MSK(2, 6)) #define STM32_SDC_SDIO_DMA_CHN 0x04004000 /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_EVENT_HANDLER VectorCC -#define STM32_SPI1_EVENT_NUMBER 35 #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) @@ -334,8 +299,6 @@ #define STM32_SPI1_TX_DMA_CHN 0x00303000 #define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_EVENT_HANDLER VectorD0 -#define STM32_SPI2_EVENT_NUMBER 36 #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) @@ -344,8 +307,6 @@ #define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_EVENT_HANDLER Vector10C -#define STM32_SPI3_EVENT_NUMBER 51 #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ @@ -356,8 +317,6 @@ #define STM32_SPI3_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI4 TRUE -#define STM32_SPI4_EVENT_HANDLER Vector190 -#define STM32_SPI4_EVENT_NUMBER 84 #define STM32_SPI4_SUPPORTS_I2S FALSE #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ STM32_DMA_STREAM_ID_MSK(2, 3)) @@ -367,8 +326,6 @@ #define STM32_SPI4_TX_DMA_CHN 0x00050040 #define STM32_HAS_SPI5 TRUE -#define STM32_SPI5_EVENT_HANDLER Vector194 -#define STM32_SPI5_EVENT_NUMBER 85 #define STM32_SPI5_SUPPORTS_I2S FALSE #define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ STM32_DMA_STREAM_ID_MSK(2, 5)) @@ -378,8 +335,6 @@ #define STM32_SPI5_TX_DMA_CHN 0x07020000 #define STM32_HAS_SPI6 TRUE -#define STM32_SPI6_EVENT_HANDLER Vector198 -#define STM32_SPI6_EVENT_NUMBER 86 #define STM32_SPI6_SUPPORTS_I2S FALSE #define STM32_SPI6_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 6) #define STM32_SPI6_RX_DMA_CHN 0x01000000 @@ -392,90 +347,58 @@ #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 4 -#define STM32_TIM1_UP_HANDLER VectorA4 -#define STM32_TIM1_CC_HANDLER VectorAC -#define STM32_TIM1_UP_NUMBER 25 -#define STM32_TIM1_CC_NUMBER 27 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 -#define STM32_TIM2_HANDLER VectorB0 -#define STM32_TIM2_NUMBER 28 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 -#define STM32_TIM3_HANDLER VectorB4 -#define STM32_TIM3_NUMBER 29 #define STM32_HAS_TIM4 TRUE #define STM32_TIM4_IS_32BITS FALSE #define STM32_TIM4_CHANNELS 4 -#define STM32_TIM4_HANDLER VectorB8 -#define STM32_TIM4_NUMBER 30 #define STM32_HAS_TIM5 TRUE #define STM32_TIM5_IS_32BITS TRUE #define STM32_TIM5_CHANNELS 4 -#define STM32_TIM5_HANDLER Vector108 -#define STM32_TIM5_NUMBER 50 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 -#define STM32_TIM6_HANDLER Vector118 -#define STM32_TIM6_NUMBER 54 #define STM32_HAS_TIM7 TRUE #define STM32_TIM7_IS_32BITS FALSE #define STM32_TIM7_CHANNELS 0 -#define STM32_TIM7_HANDLER Vector11C -#define STM32_TIM7_NUMBER 55 #define STM32_HAS_TIM8 TRUE #define STM32_TIM8_IS_32BITS FALSE #define STM32_TIM8_CHANNELS 4 -#define STM32_TIM8_UP_HANDLER VectorF0 -#define STM32_TIM8_CC_HANDLER VectorF8 -#define STM32_TIM8_UP_NUMBER 44 -#define STM32_TIM8_CC_NUMBER 46 #define STM32_HAS_TIM9 TRUE #define STM32_TIM9_IS_32BITS FALSE #define STM32_TIM9_CHANNELS 2 -#define STM32_TIM9_HANDLER VectorA0 -#define STM32_TIM9_NUMBER 24 #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE #define STM32_TIM10_CHANNELS 1 -#define STM32_TIM10_HANDLER VectorA4 -#define STM32_TIM10_NUMBER 25 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE #define STM32_TIM11_CHANNELS 1 -#define STM32_TIM11_HANDLER VectorA8 -#define STM32_TIM11_NUMBER 26 #define STM32_HAS_TIM12 TRUE #define STM32_TIM12_IS_32BITS FALSE #define STM32_TIM12_CHANNELS 2 -#define STM32_TIM12_HANDLER VectorEC -#define STM32_TIM12_NUMBER 43 #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE #define STM32_TIM13_CHANNELS 1 -#define STM32_TIM13_HANDLER VectorF0 -#define STM32_TIM13_NUMBER 44 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE #define STM32_TIM14_CHANNELS 1 -#define STM32_TIM14_HANDLER VectorF4 -#define STM32_TIM14_NUMBER 45 #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE @@ -488,8 +411,6 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_USART1_HANDLER VectorD4 -#define STM32_USART1_NUMBER 37 #define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ STM32_DMA_STREAM_ID_MSK(2, 5)) #define STM32_USART1_RX_DMA_CHN 0x00400400 @@ -497,16 +418,12 @@ #define STM32_USART1_TX_DMA_CHN 0x40000000 #define STM32_HAS_USART2 TRUE -#define STM32_USART2_HANDLER VectorD8 -#define STM32_USART2_NUMBER 38 #define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) #define STM32_USART2_RX_DMA_CHN 0x00400000 #define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) #define STM32_USART2_TX_DMA_CHN 0x04000000 #define STM32_HAS_USART3 TRUE -#define STM32_USART3_HANDLER VectorDC -#define STM32_USART3_NUMBER 39 #define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) #define STM32_USART3_RX_DMA_CHN 0x00000040 #define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ @@ -514,24 +431,18 @@ #define STM32_USART3_TX_DMA_CHN 0x00074000 #define STM32_HAS_UART4 TRUE -#define STM32_UART4_HANDLER Vector110 -#define STM32_UART4_NUMBER 52 #define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_UART4_RX_DMA_CHN 0x00000400 #define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) #define STM32_UART4_TX_DMA_CHN 0x00040000 #define STM32_HAS_UART5 TRUE -#define STM32_UART5_HANDLER Vector114 -#define STM32_UART5_NUMBER 53 #define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) #define STM32_UART5_RX_DMA_CHN 0x00000004 #define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) #define STM32_UART5_TX_DMA_CHN 0x40000000 #define STM32_HAS_USART6 TRUE -#define STM32_USART6_HANDLER Vector15C -#define STM32_USART6_NUMBER 71 #define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) #define STM32_USART6_RX_DMA_CHN 0x00000550 @@ -540,16 +451,12 @@ #define STM32_USART6_TX_DMA_CHN 0x55000000 #define STM32_HAS_UART7 TRUE -#define STM32_UART7_HANDLER Vector188 -#define STM32_UART7_NUMBER 82 #define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_UART7_RX_DMA_CHN 0x00004000 #define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) #define STM32_UART7_TX_DMA_CHN 0x00000050 #define STM32_HAS_UART8 TRUE -#define STM32_UART8_HANDLER Vector18C -#define STM32_UART8_NUMBER 83 #define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) #define STM32_UART8_RX_DMA_CHN 0x05000000 #define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) @@ -559,17 +466,8 @@ /* USB attributes.*/ #define STM32_OTG_STEPPING 2 #define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_HANDLER Vector14C -#define STM32_OTG1_NUMBER 67 #define STM32_OTG1_ENDPOINTS 5 - #define STM32_HAS_OTG2 TRUE -#define STM32_OTG2_HANDLER Vector174 -#define STM32_OTG2_EP1OUT_HANDLER Vector168 -#define STM32_OTG2_EP1IN_HANDLER Vector16C -#define STM32_OTG2_NUMBER 77 -#define STM32_OTG2_EP1OUT_NUMBER 74 -#define STM32_OTG2_EP1IN_NUMBER 75 #define STM32_OTG2_ENDPOINTS 7 #define STM32_HAS_USB FALSE @@ -580,15 +478,9 @@ /* LTDC attributes.*/ #define STM32_HAS_LTDC TRUE -#define STM32_LTDC_EV_HANDLER Vector1A0 -#define STM32_LTDC_ER_HANDLER Vector1A4 -#define STM32_LTDC_EV_NUMBER 88 -#define STM32_LTDC_ER_NUMBER 89 /* DMA2D attributes.*/ #define STM32_HAS_DMA2D TRUE -#define STM32_DMA2D_HANDLER Vector1A8 -#define STM32_DMA2D_NUMBER 90 /* FSMC attributes.*/ #define STM32_HAS_FSMC TRUE @@ -600,11 +492,6 @@ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE FALSE -/* DCMI attributes.*/ -#define STM32_HAS_DCMI TRUE -#define STM32_DCMI_HANDLER Vector178 -#define STM32_DCMI_NUMBER 78 - #endif /* defined(STM32F469_479xx) */ /*===========================================================================*/ @@ -651,27 +538,8 @@ /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE -#define STM32_CAN1_TX_HANDLER Vector8C -#define STM32_CAN1_RX0_HANDLER Vector90 -#define STM32_CAN1_RX1_HANDLER Vector94 -#define STM32_CAN1_SCE_HANDLER Vector98 -#define STM32_CAN1_TX_NUMBER 19 -#define STM32_CAN1_RX0_NUMBER 20 -#define STM32_CAN1_RX1_NUMBER 21 -#define STM32_CAN1_SCE_NUMBER 22 - #define STM32_HAS_CAN2 TRUE -#define STM32_CAN2_TX_HANDLER Vector13C -#define STM32_CAN2_RX0_HANDLER Vector140 -#define STM32_CAN2_RX1_HANDLER Vector144 -#define STM32_CAN2_SCE_HANDLER Vector148 -#define STM32_CAN2_TX_NUMBER 63 -#define STM32_CAN2_RX0_NUMBER 64 -#define STM32_CAN2_RX1_NUMBER 65 -#define STM32_CAN2_SCE_NUMBER 66 - #define STM32_HAS_CAN3 FALSE - #define STM32_CAN_MAX_FILTERS 28 /* DAC attributes.*/ @@ -758,10 +626,6 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_EVENT_HANDLER VectorBC -#define STM32_I2C1_ERROR_HANDLER VectorC0 -#define STM32_I2C1_EVENT_NUMBER 31 -#define STM32_I2C1_ERROR_NUMBER 32 #define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ STM32_DMA_STREAM_ID_MSK(1, 5)) #define STM32_I2C1_RX_DMA_CHN 0x00100001 @@ -770,10 +634,6 @@ #define STM32_I2C1_TX_DMA_CHN 0x11000000 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_EVENT_HANDLER VectorC4 -#define STM32_I2C2_ERROR_HANDLER VectorC8 -#define STM32_I2C2_EVENT_NUMBER 33 -#define STM32_I2C2_ERROR_NUMBER 34 #define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ STM32_DMA_STREAM_ID_MSK(1, 3)) #define STM32_I2C2_RX_DMA_CHN 0x00007700 @@ -781,10 +641,6 @@ #define STM32_I2C2_TX_DMA_CHN 0x70000000 #define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_EVENT_HANDLER Vector160 -#define STM32_I2C3_ERROR_HANDLER Vector164 -#define STM32_I2C3_EVENT_NUMBER 72 -#define STM32_I2C3_ERROR_NUMBER 73 #define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_I2C3_RX_DMA_CHN 0x00000300 #define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) @@ -801,16 +657,12 @@ /* SDIO attributes.*/ #define STM32_HAS_SDIO TRUE -#define STM32_SDIO_HANDLER Vector104 -#define STM32_SDIO_NUMBER 49 #define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ STM32_DMA_STREAM_ID_MSK(2, 6)) #define STM32_SDC_SDIO_DMA_CHN 0x04004000 /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_EVENT_HANDLER VectorCC -#define STM32_SPI1_EVENT_NUMBER 35 #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) @@ -820,8 +672,6 @@ #define STM32_SPI1_TX_DMA_CHN 0x00303000 #define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_EVENT_HANDLER VectorD0 -#define STM32_SPI2_EVENT_NUMBER 36 #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) @@ -830,8 +680,6 @@ #define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_EVENT_HANDLER Vector10C -#define STM32_SPI3_EVENT_NUMBER 51 #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ @@ -842,8 +690,6 @@ #define STM32_SPI3_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI4 TRUE -#define STM32_SPI4_EVENT_HANDLER Vector190 -#define STM32_SPI4_EVENT_NUMBER 84 #define STM32_SPI4_SUPPORTS_I2S FALSE #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ STM32_DMA_STREAM_ID_MSK(2, 3)) @@ -861,90 +707,58 @@ #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 4 -#define STM32_TIM1_UP_HANDLER VectorA4 -#define STM32_TIM1_CC_HANDLER VectorAC -#define STM32_TIM1_UP_NUMBER 25 -#define STM32_TIM1_CC_NUMBER 27 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 -#define STM32_TIM2_HANDLER VectorB0 -#define STM32_TIM2_NUMBER 28 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 -#define STM32_TIM3_HANDLER VectorB4 -#define STM32_TIM3_NUMBER 29 #define STM32_HAS_TIM4 TRUE #define STM32_TIM4_IS_32BITS FALSE #define STM32_TIM4_CHANNELS 4 -#define STM32_TIM4_HANDLER VectorB8 -#define STM32_TIM4_NUMBER 30 #define STM32_HAS_TIM5 TRUE #define STM32_TIM5_IS_32BITS TRUE #define STM32_TIM5_CHANNELS 4 -#define STM32_TIM5_HANDLER Vector108 -#define STM32_TIM5_NUMBER 50 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 -#define STM32_TIM6_HANDLER Vector118 -#define STM32_TIM6_NUMBER 54 #define STM32_HAS_TIM7 TRUE #define STM32_TIM7_IS_32BITS FALSE #define STM32_TIM7_CHANNELS 0 -#define STM32_TIM7_HANDLER Vector11C -#define STM32_TIM7_NUMBER 55 #define STM32_HAS_TIM8 TRUE #define STM32_TIM8_IS_32BITS FALSE #define STM32_TIM8_CHANNELS 4 -#define STM32_TIM8_UP_HANDLER VectorF0 -#define STM32_TIM8_CC_HANDLER VectorF8 -#define STM32_TIM8_UP_NUMBER 44 -#define STM32_TIM8_CC_NUMBER 46 #define STM32_HAS_TIM9 TRUE #define STM32_TIM9_IS_32BITS FALSE #define STM32_TIM9_CHANNELS 2 -#define STM32_TIM9_HANDLER VectorA0 -#define STM32_TIM9_NUMBER 24 #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE #define STM32_TIM10_CHANNELS 1 -#define STM32_TIM10_HANDLER VectorA4 -#define STM32_TIM10_NUMBER 25 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE #define STM32_TIM11_CHANNELS 1 -#define STM32_TIM11_HANDLER VectorA8 -#define STM32_TIM11_NUMBER 26 #define STM32_HAS_TIM12 TRUE #define STM32_TIM12_IS_32BITS FALSE #define STM32_TIM12_CHANNELS 2 -#define STM32_TIM12_HANDLER VectorEC -#define STM32_TIM12_NUMBER 43 #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE #define STM32_TIM13_CHANNELS 1 -#define STM32_TIM13_HANDLER VectorF0 -#define STM32_TIM13_NUMBER 44 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE #define STM32_TIM14_CHANNELS 1 -#define STM32_TIM14_HANDLER VectorF4 -#define STM32_TIM14_NUMBER 45 #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE @@ -957,8 +771,6 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_USART1_HANDLER VectorD4 -#define STM32_USART1_NUMBER 37 #define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ STM32_DMA_STREAM_ID_MSK(2, 5)) #define STM32_USART1_RX_DMA_CHN 0x00400400 @@ -966,16 +778,12 @@ #define STM32_USART1_TX_DMA_CHN 0x40000000 #define STM32_HAS_USART2 TRUE -#define STM32_USART2_HANDLER VectorD8 -#define STM32_USART2_NUMBER 38 #define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) #define STM32_USART2_RX_DMA_CHN 0x00400000 #define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) #define STM32_USART2_TX_DMA_CHN 0x04000000 #define STM32_HAS_USART3 TRUE -#define STM32_USART3_HANDLER VectorDC -#define STM32_USART3_NUMBER 39 #define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) #define STM32_USART3_RX_DMA_CHN 0x00000040 #define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ @@ -983,24 +791,18 @@ #define STM32_USART3_TX_DMA_CHN 0x00074000 #define STM32_HAS_UART4 TRUE -#define STM32_UART4_HANDLER Vector110 -#define STM32_UART4_NUMBER 52 #define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_UART4_RX_DMA_CHN 0x00000400 #define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) #define STM32_UART4_TX_DMA_CHN 0x00040000 #define STM32_HAS_UART5 TRUE -#define STM32_UART5_HANDLER Vector114 -#define STM32_UART5_NUMBER 53 #define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) #define STM32_UART5_RX_DMA_CHN 0x00000004 #define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) #define STM32_UART5_TX_DMA_CHN 0x40000000 #define STM32_HAS_USART6 TRUE -#define STM32_USART6_HANDLER Vector15C -#define STM32_USART6_NUMBER 71 #define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) #define STM32_USART6_RX_DMA_CHN 0x00000550 @@ -1015,16 +817,8 @@ /* USB attributes.*/ #define STM32_OTG_STEPPING 2 #define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_HANDLER Vector14C -#define STM32_OTG1_NUMBER 67 #define STM32_OTG1_ENDPOINTS 5 #define STM32_HAS_OTG2 TRUE -#define STM32_OTG2_HANDLER Vector174 -#define STM32_OTG2_EP1OUT_HANDLER Vector168 -#define STM32_OTG2_EP1IN_HANDLER Vector16C -#define STM32_OTG2_NUMBER 77 -#define STM32_OTG2_EP1OUT_NUMBER 74 -#define STM32_OTG2_EP1IN_NUMBER 75 #define STM32_OTG2_ENDPOINTS 7 #define STM32_HAS_USB FALSE @@ -1034,10 +828,10 @@ #define STM32_IWDG_IS_WINDOWED FALSE /* LTDC attributes.*/ -#define STM32_HAS_LTDC FALSE +#define STM32_HAS_LTDC TRUE /* DMA2D attributes.*/ -#define STM32_HAS_DMA2D FALSE +#define STM32_HAS_DMA2D TRUE /* FSMC attributes.*/ #define STM32_HAS_FSMC TRUE @@ -1049,11 +843,6 @@ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE FALSE -/* DCMI attributes.*/ -#define STM32_HAS_DCMI TRUE -#define STM32_DCMI_HANDLER Vector178 -#define STM32_DCMI_NUMBER 78 - #endif /* defined(STM32F446xx) */ /*===========================================================================*/ @@ -1102,27 +891,8 @@ /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE -#define STM32_CAN1_TX_HANDLER Vector8C -#define STM32_CAN1_RX0_HANDLER Vector90 -#define STM32_CAN1_RX1_HANDLER Vector94 -#define STM32_CAN1_SCE_HANDLER Vector98 -#define STM32_CAN1_TX_NUMBER 19 -#define STM32_CAN1_RX0_NUMBER 20 -#define STM32_CAN1_RX1_NUMBER 21 -#define STM32_CAN1_SCE_NUMBER 22 - #define STM32_HAS_CAN2 TRUE -#define STM32_CAN2_TX_HANDLER Vector13C -#define STM32_CAN2_RX0_HANDLER Vector140 -#define STM32_CAN2_RX1_HANDLER Vector144 -#define STM32_CAN2_SCE_HANDLER Vector148 -#define STM32_CAN2_TX_NUMBER 63 -#define STM32_CAN2_RX0_NUMBER 64 -#define STM32_CAN2_RX1_NUMBER 65 -#define STM32_CAN2_SCE_NUMBER 66 - #define STM32_HAS_CAN3 FALSE - #define STM32_CAN_MAX_FILTERS 28 /* DAC attributes.*/ @@ -1211,10 +981,6 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_EVENT_HANDLER VectorBC -#define STM32_I2C1_ERROR_HANDLER VectorC0 -#define STM32_I2C1_EVENT_NUMBER 31 -#define STM32_I2C1_ERROR_NUMBER 32 #define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ STM32_DMA_STREAM_ID_MSK(1, 5)) #define STM32_I2C1_RX_DMA_CHN 0x00100001 @@ -1223,10 +989,6 @@ #define STM32_I2C1_TX_DMA_CHN 0x11000000 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_EVENT_HANDLER VectorC4 -#define STM32_I2C2_ERROR_HANDLER VectorC8 -#define STM32_I2C2_EVENT_NUMBER 33 -#define STM32_I2C2_ERROR_NUMBER 34 #define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ STM32_DMA_STREAM_ID_MSK(1, 3)) #define STM32_I2C2_RX_DMA_CHN 0x00007700 @@ -1234,10 +996,6 @@ #define STM32_I2C2_TX_DMA_CHN 0x70000000 #define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_EVENT_HANDLER Vector160 -#define STM32_I2C3_ERROR_HANDLER Vector164 -#define STM32_I2C3_EVENT_NUMBER 72 -#define STM32_I2C3_ERROR_NUMBER 73 #define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_I2C3_RX_DMA_CHN 0x00000300 #define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) @@ -1250,16 +1008,12 @@ /* SDIO attributes.*/ #define STM32_HAS_SDIO TRUE -#define STM32_SDIO_HANDLER Vector104 -#define STM32_SDIO_NUMBER 49 #define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ STM32_DMA_STREAM_ID_MSK(2, 6)) #define STM32_SDC_SDIO_DMA_CHN 0x04004000 /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_EVENT_HANDLER VectorCC -#define STM32_SPI1_EVENT_NUMBER 35 #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) @@ -1269,8 +1023,6 @@ #define STM32_SPI1_TX_DMA_CHN 0x00303000 #define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_EVENT_HANDLER VectorD0 -#define STM32_SPI2_EVENT_NUMBER 36 #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) @@ -1279,8 +1031,6 @@ #define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_EVENT_HANDLER Vector10C -#define STM32_SPI3_EVENT_NUMBER 51 #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ @@ -1291,8 +1041,6 @@ #define STM32_SPI3_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI4 TRUE -#define STM32_SPI4_EVENT_HANDLER Vector190 -#define STM32_SPI4_EVENT_NUMBER 84 #define STM32_SPI4_SUPPORTS_I2S FALSE #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ STM32_DMA_STREAM_ID_MSK(2, 3)) @@ -1302,19 +1050,15 @@ #define STM32_SPI4_TX_DMA_CHN 0x00050040 #define STM32_HAS_SPI5 TRUE -#define STM32_SPI5_EVENT_HANDLER Vector194 -#define STM32_SPI5_EVENT_NUMBER 85 #define STM32_SPI5_SUPPORTS_I2S FALSE -#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ +#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \ STM32_DMA_STREAM_ID_MSK(2, 5)) #define STM32_SPI5_RX_DMA_CHN 0x00702000 -#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\ +#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) | \ STM32_DMA_STREAM_ID_MSK(2, 6)) #define STM32_SPI5_TX_DMA_CHN 0x07020000 #define STM32_HAS_SPI6 TRUE -#define STM32_SPI6_EVENT_HANDLER Vector198 -#define STM32_SPI6_EVENT_NUMBER 86 #define STM32_SPI6_SUPPORTS_I2S FALSE #define STM32_SPI6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6)) #define STM32_SPI6_RX_DMA_CHN 0x01000000 @@ -1327,90 +1071,58 @@ #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 4 -#define STM32_TIM1_UP_HANDLER VectorA4 -#define STM32_TIM1_CC_HANDLER VectorAC -#define STM32_TIM1_UP_NUMBER 25 -#define STM32_TIM1_CC_NUMBER 27 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 -#define STM32_TIM2_HANDLER VectorB0 -#define STM32_TIM2_NUMBER 28 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 -#define STM32_TIM3_HANDLER VectorB4 -#define STM32_TIM3_NUMBER 29 #define STM32_HAS_TIM4 TRUE #define STM32_TIM4_IS_32BITS FALSE #define STM32_TIM4_CHANNELS 4 -#define STM32_TIM4_HANDLER VectorB8 -#define STM32_TIM4_NUMBER 30 #define STM32_HAS_TIM5 TRUE #define STM32_TIM5_IS_32BITS TRUE #define STM32_TIM5_CHANNELS 4 -#define STM32_TIM5_HANDLER Vector108 -#define STM32_TIM5_NUMBER 50 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 -#define STM32_TIM6_HANDLER Vector118 -#define STM32_TIM6_NUMBER 54 #define STM32_HAS_TIM7 TRUE #define STM32_TIM7_IS_32BITS FALSE #define STM32_TIM7_CHANNELS 0 -#define STM32_TIM7_HANDLER Vector11C -#define STM32_TIM7_NUMBER 55 #define STM32_HAS_TIM8 TRUE #define STM32_TIM8_IS_32BITS FALSE #define STM32_TIM8_CHANNELS 4 -#define STM32_TIM8_UP_HANDLER VectorF0 -#define STM32_TIM8_CC_HANDLER VectorF8 -#define STM32_TIM8_UP_NUMBER 44 -#define STM32_TIM8_CC_NUMBER 46 #define STM32_HAS_TIM9 TRUE #define STM32_TIM9_IS_32BITS FALSE #define STM32_TIM9_CHANNELS 2 -#define STM32_TIM9_HANDLER VectorA0 -#define STM32_TIM9_NUMBER 24 #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE #define STM32_TIM10_CHANNELS 1 -#define STM32_TIM10_HANDLER VectorA4 -#define STM32_TIM10_NUMBER 25 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE #define STM32_TIM11_CHANNELS 1 -#define STM32_TIM11_HANDLER VectorA8 -#define STM32_TIM11_NUMBER 26 #define STM32_HAS_TIM12 TRUE #define STM32_TIM12_IS_32BITS FALSE #define STM32_TIM12_CHANNELS 2 -#define STM32_TIM12_HANDLER VectorEC -#define STM32_TIM12_NUMBER 43 #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE #define STM32_TIM13_CHANNELS 1 -#define STM32_TIM13_HANDLER VectorF0 -#define STM32_TIM13_NUMBER 44 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE #define STM32_TIM14_CHANNELS 1 -#define STM32_TIM14_HANDLER VectorF4 -#define STM32_TIM14_NUMBER 45 #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE @@ -1423,8 +1135,6 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_USART1_HANDLER VectorD4 -#define STM32_USART1_NUMBER 37 #define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ STM32_DMA_STREAM_ID_MSK(2, 5)) #define STM32_USART1_RX_DMA_CHN 0x00400400 @@ -1432,16 +1142,12 @@ #define STM32_USART1_TX_DMA_CHN 0x40000000 #define STM32_HAS_USART2 TRUE -#define STM32_USART2_HANDLER VectorD8 -#define STM32_USART2_NUMBER 38 #define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) #define STM32_USART2_RX_DMA_CHN 0x00400000 #define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) #define STM32_USART2_TX_DMA_CHN 0x04000000 #define STM32_HAS_USART3 TRUE -#define STM32_USART3_HANDLER VectorDC -#define STM32_USART3_NUMBER 39 #define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) #define STM32_USART3_RX_DMA_CHN 0x00000040 #define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ @@ -1449,24 +1155,18 @@ #define STM32_USART3_TX_DMA_CHN 0x00074000 #define STM32_HAS_UART4 TRUE -#define STM32_UART4_HANDLER Vector110 -#define STM32_UART4_NUMBER 52 #define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_UART4_RX_DMA_CHN 0x00000400 #define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) #define STM32_UART4_TX_DMA_CHN 0x00040000 #define STM32_HAS_UART5 TRUE -#define STM32_UART5_HANDLER Vector114 -#define STM32_UART5_NUMBER 53 #define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) #define STM32_UART5_RX_DMA_CHN 0x00000004 #define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) #define STM32_UART5_TX_DMA_CHN 0x40000000 #define STM32_HAS_USART6 TRUE -#define STM32_USART6_HANDLER Vector15C -#define STM32_USART6_NUMBER 71 #define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) #define STM32_USART6_RX_DMA_CHN 0x00000550 @@ -1475,16 +1175,12 @@ #define STM32_USART6_TX_DMA_CHN 0x55000000 #define STM32_HAS_UART7 TRUE -#define STM32_UART7_HANDLER Vector188 -#define STM32_UART7_NUMBER 82 #define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_UART7_RX_DMA_CHN 0x00005000 #define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) #define STM32_UART7_TX_DMA_CHN 0x00000050 #define STM32_HAS_UART8 TRUE -#define STM32_UART8_HANDLER Vector18C -#define STM32_UART8_NUMBER 83 #define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) #define STM32_UART8_RX_DMA_CHN 0x05000000 #define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) @@ -1495,17 +1191,8 @@ /* USB attributes.*/ #define STM32_OTG_STEPPING 1 #define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_HANDLER Vector14C -#define STM32_OTG1_NUMBER 67 #define STM32_OTG1_ENDPOINTS 3 - #define STM32_HAS_OTG2 TRUE -#define STM32_OTG2_HANDLER Vector174 -#define STM32_OTG2_EP1OUT_HANDLER Vector168 -#define STM32_OTG2_EP1IN_HANDLER Vector16C -#define STM32_OTG2_NUMBER 77 -#define STM32_OTG2_EP1OUT_NUMBER 74 -#define STM32_OTG2_EP1IN_NUMBER 75 #define STM32_OTG2_ENDPOINTS 5 #define STM32_HAS_USB FALSE @@ -1516,15 +1203,9 @@ /* LTDC attributes.*/ #define STM32_HAS_LTDC TRUE -#define STM32_LTDC_EV_HANDLER Vector1A0 -#define STM32_LTDC_ER_HANDLER Vector1A4 -#define STM32_LTDC_EV_NUMBER 88 -#define STM32_LTDC_ER_NUMBER 89 /* DMA2D attributes.*/ #define STM32_HAS_DMA2D TRUE -#define STM32_DMA2D_HANDLER Vector1A8 -#define STM32_DMA2D_NUMBER 90 /* FSMC attributes.*/ #define STM32_HAS_FSMC TRUE @@ -1536,9 +1217,6 @@ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE FALSE -/* DCMI attributes.*/ -#define STM32_HAS_DCMI FALSE - #endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */ /*===========================================================================*/ @@ -1577,37 +1255,9 @@ /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE -#define STM32_CAN1_TX_HANDLER Vector8C -#define STM32_CAN1_RX0_HANDLER Vector90 -#define STM32_CAN1_RX1_HANDLER Vector94 -#define STM32_CAN1_SCE_HANDLER Vector98 -#define STM32_CAN1_TX_NUMBER 19 -#define STM32_CAN1_RX0_NUMBER 20 -#define STM32_CAN1_RX1_NUMBER 21 -#define STM32_CAN1_SCE_NUMBER 22 - #define STM32_HAS_CAN2 TRUE -#define STM32_CAN2_TX_HANDLER Vector13C -#define STM32_CAN2_RX0_HANDLER Vector140 -#define STM32_CAN2_RX1_HANDLER Vector144 -#define STM32_CAN2_SCE_HANDLER Vector148 -#define STM32_CAN2_TX_NUMBER 63 -#define STM32_CAN2_RX0_NUMBER 64 -#define STM32_CAN2_RX1_NUMBER 65 -#define STM32_CAN2_SCE_NUMBER 66 - #define STM32_HAS_CAN3 TRUE -#define STM32_CAN3_TX_HANDLER Vector168 -#define STM32_CAN3_RX0_HANDLER Vector16C -#define STM32_CAN3_RX1_HANDLER Vector170 -#define STM32_CAN3_SCE_HANDLER Vector174 -#define STM32_CAN3_TX_NUMBER 74 -#define STM32_CAN3_RX0_NUMBER 75 -#define STM32_CAN3_RX1_NUMBER 76 -#define STM32_CAN3_SCE_NUMBER 77 - #define STM32_CAN_MAX_FILTERS 28 -#define STM32_CAN3_MAX_FILTERS 14 /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 TRUE @@ -1692,10 +1342,6 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_EVENT_HANDLER VectorBC -#define STM32_I2C1_ERROR_HANDLER VectorC0 -#define STM32_I2C1_EVENT_NUMBER 31 -#define STM32_I2C1_ERROR_NUMBER 32 #define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ STM32_DMA_STREAM_ID_MSK(1, 5)) #define STM32_I2C1_RX_DMA_CHN 0x00100001 @@ -1704,10 +1350,6 @@ #define STM32_I2C1_TX_DMA_CHN 0x11000000 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_EVENT_HANDLER VectorC4 -#define STM32_I2C2_ERROR_HANDLER VectorC8 -#define STM32_I2C2_EVENT_NUMBER 33 -#define STM32_I2C2_ERROR_NUMBER 34 #define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ STM32_DMA_STREAM_ID_MSK(1, 3)) #define STM32_I2C2_RX_DMA_CHN 0x00007700 @@ -1715,10 +1357,6 @@ #define STM32_I2C2_TX_DMA_CHN 0x70000000 #define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_EVENT_HANDLER Vector160 -#define STM32_I2C3_ERROR_HANDLER Vector164 -#define STM32_I2C3_EVENT_NUMBER 72 -#define STM32_I2C3_ERROR_NUMBER 73 #define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ STM32_DMA_STREAM_ID_MSK(1, 2)) #define STM32_I2C3_RX_DMA_CHN 0x00000310 @@ -1726,18 +1364,13 @@ STM32_DMA_STREAM_ID_MSK(1, 5)) #define STM32_I2C3_TX_DMA_CHN 0x00630000 -#define STM32_HAS_I2C4 FALSE - -/* FMPI2C attributes.*/ -#define STM32_HAS_FMPI2C TRUE -#define STM32_FMPI2C_EVENT_HANDLER Vector1BC -#define STM32_FMPI2C_ERROR_HANDLER Vector1C0 -#define STM32_FMPI2C_EVENT_NUMBER 95 -#define STM32_FMPI2C_ERROR_NUMBER 96 -#define STM32_FMPI2C_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_FMPI2C_RX_DMA_CHN 0x00001000 -#define STM32_FMPI2C_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) -#define STM32_FMPI2C_TX_DMA_CHN 0x00000020 +#define STM32_HAS_I2C4 TRUE +#define STM32_I2C4_SUPPORTS_FMP TRUE +#define STM32_HAS_I2C4 TRUE +#define STM32_I2C4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_I2C4_RX_DMA_CHN 0x00001000 +#define STM32_I2C4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) +#define STM32_I2C4_TX_DMA_CHN 0x00000020 /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 TRUE @@ -1748,16 +1381,12 @@ /* SDIO attributes.*/ #define STM32_HAS_SDIO TRUE -#define STM32_SDIO_HANDLER Vector104 -#define STM32_SDIO_NUMBER 49 #define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ STM32_DMA_STREAM_ID_MSK(2, 6)) #define STM32_SDC_SDIO_DMA_CHN 0x04004000 /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_EVENT_HANDLER VectorCC -#define STM32_SPI1_EVENT_NUMBER 35 #define STM32_SPI1_SUPPORTS_I2S TRUE #define STM32_SPI1_I2S_FULLDUPLEX FALSE #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ @@ -1769,8 +1398,6 @@ #define STM32_SPI1_TX_DMA_CHN 0x00303200 #define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_EVENT_HANDLER VectorD0 -#define STM32_SPI2_EVENT_NUMBER 36 #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) @@ -1779,8 +1406,6 @@ #define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_EVENT_HANDLER Vector10C -#define STM32_SPI3_EVENT_NUMBER 51 #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ @@ -1791,8 +1416,6 @@ #define STM32_SPI3_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI4 TRUE -#define STM32_SPI4_EVENT_HANDLER Vector190 -#define STM32_SPI4_EVENT_NUMBER 84 #define STM32_SPI4_SUPPORTS_I2S TRUE #define STM32_SPI4_I2S_FULLDUPLEX FALSE #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ @@ -1804,8 +1427,6 @@ #define STM32_SPI4_TX_DMA_CHN 0x00050040 #define STM32_HAS_SPI5 TRUE -#define STM32_SPI5_EVENT_HANDLER Vector194 -#define STM32_SPI5_EVENT_NUMBER 85 #define STM32_SPI5_SUPPORTS_I2S TRUE #define STM32_SPI5_I2S_FULLDUPLEX FALSE #define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ @@ -1824,90 +1445,58 @@ #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 4 -#define STM32_TIM1_UP_HANDLER VectorA4 -#define STM32_TIM1_CC_HANDLER VectorAC -#define STM32_TIM1_UP_NUMBER 25 -#define STM32_TIM1_CC_NUMBER 27 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 -#define STM32_TIM2_HANDLER VectorB0 -#define STM32_TIM2_NUMBER 28 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 -#define STM32_TIM3_HANDLER VectorB4 -#define STM32_TIM3_NUMBER 29 #define STM32_HAS_TIM4 TRUE #define STM32_TIM4_IS_32BITS FALSE #define STM32_TIM4_CHANNELS 4 -#define STM32_TIM4_HANDLER VectorB8 -#define STM32_TIM4_NUMBER 30 #define STM32_HAS_TIM5 TRUE #define STM32_TIM5_IS_32BITS TRUE #define STM32_TIM5_CHANNELS 4 -#define STM32_TIM5_HANDLER Vector108 -#define STM32_TIM5_NUMBER 50 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 -#define STM32_TIM6_HANDLER Vector118 -#define STM32_TIM6_NUMBER 54 #define STM32_HAS_TIM7 TRUE #define STM32_TIM7_IS_32BITS FALSE #define STM32_TIM7_CHANNELS 0 -#define STM32_TIM7_HANDLER Vector11C -#define STM32_TIM7_NUMBER 55 #define STM32_HAS_TIM8 TRUE #define STM32_TIM8_IS_32BITS FALSE #define STM32_TIM8_CHANNELS 4 -#define STM32_TIM8_UP_HANDLER VectorF0 -#define STM32_TIM8_CC_HANDLER VectorF8 -#define STM32_TIM8_UP_NUMBER 44 -#define STM32_TIM8_CC_NUMBER 46 #define STM32_HAS_TIM9 TRUE #define STM32_TIM9_IS_32BITS FALSE #define STM32_TIM9_CHANNELS 2 -#define STM32_TIM9_HANDLER VectorA0 -#define STM32_TIM9_NUMBER 24 #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE #define STM32_TIM10_CHANNELS 1 -#define STM32_TIM10_HANDLER VectorA4 -#define STM32_TIM10_NUMBER 25 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE #define STM32_TIM11_CHANNELS 1 -#define STM32_TIM11_HANDLER VectorA8 -#define STM32_TIM11_NUMBER 26 #define STM32_HAS_TIM12 TRUE #define STM32_TIM12_IS_32BITS FALSE #define STM32_TIM12_CHANNELS 2 -#define STM32_TIM12_HANDLER VectorEC -#define STM32_TIM12_NUMBER 43 #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE #define STM32_TIM13_CHANNELS 1 -#define STM32_TIM13_HANDLER VectorF0 -#define STM32_TIM13_NUMBER 44 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE #define STM32_TIM14_CHANNELS 1 -#define STM32_TIM14_HANDLER VectorF4 -#define STM32_TIM14_NUMBER 45 #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE @@ -1922,26 +1511,19 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_USART1_HANDLER VectorD4 -#define STM32_USART1_NUMBER 37 #define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ STM32_DMA_STREAM_ID_MSK(2, 5)) #define STM32_USART1_RX_DMA_CHN 0x00400400 #define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) #define STM32_USART1_TX_DMA_CHN 0x40000000 - #define STM32_HAS_USART2 TRUE -#define STM32_USART2_HANDLER VectorD8 -#define STM32_USART2_NUMBER 38 #define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) #define STM32_USART2_RX_DMA_CHN 0x00400000 #define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) #define STM32_USART2_TX_DMA_CHN 0x04000000 #define STM32_HAS_USART3 TRUE -#define STM32_USART3_HANDLER VectorDC -#define STM32_USART3_NUMBER 39 #define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) #define STM32_USART3_RX_DMA_CHN 0x00000040 #define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ @@ -1949,24 +1531,18 @@ #define STM32_USART3_TX_DMA_CHN 0x00074000 #define STM32_HAS_UART4 TRUE -#define STM32_UART4_HANDLER Vector110 -#define STM32_UART4_NUMBER 52 #define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_UART4_RX_DMA_CHN 0x00000400 #define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) #define STM32_UART4_TX_DMA_CHN 0x00040000 #define STM32_HAS_UART5 TRUE -#define STM32_UART5_HANDLER Vector114 -#define STM32_UART5_NUMBER 53 #define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) #define STM32_UART5_RX_DMA_CHN 0x00000004 #define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) #define STM32_UART5_TX_DMA_CHN 0x40000000 #define STM32_HAS_USART6 TRUE -#define STM32_USART6_HANDLER Vector15C -#define STM32_USART6_NUMBER 71 #define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) #define STM32_USART6_RX_DMA_CHN 0x00000550 @@ -1975,32 +1551,24 @@ #define STM32_USART6_TX_DMA_CHN 0x55000000 #define STM32_HAS_UART7 TRUE -#define STM32_UART7_HANDLER Vector188 -#define STM32_UART7_NUMBER 82 #define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_UART7_RX_DMA_CHN 0x00005000 #define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) #define STM32_UART7_TX_DMA_CHN 0x00000050 #define STM32_HAS_UART8 TRUE -#define STM32_UART8_HANDLER Vector18C -#define STM32_UART8_NUMBER 83 #define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) #define STM32_UART8_RX_DMA_CHN 0x05000000 #define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) #define STM32_UART8_TX_DMA_CHN 0x00000005 #define STM32_HAS_UART9 TRUE -#define STM32_UART9_HANDLER Vector1A0 -#define STM32_UART9_NUMBER 88 #define STM32_UART9_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) #define STM32_UART9_RX_DMA_CHN 0x00000000 #define STM32_UART9_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 0) #define STM32_UART9_TX_DMA_CHN 0x00000001 #define STM32_HAS_UART10 TRUE -#define STM32_UART10_HANDLER Vector1A4 -#define STM32_UART10_NUMBER 89 #define STM32_UART10_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 3) #define STM32_UART10_RX_DMA_CHN 0x00009000 #define STM32_UART10_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5) @@ -2011,8 +1579,6 @@ /* USB attributes.*/ #define STM32_OTG_STEPPING 2 #define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_HANDLER Vector14C -#define STM32_OTG1_NUMBER 67 #define STM32_OTG1_ENDPOINTS 5 #define STM32_HAS_OTG2 FALSE @@ -2029,18 +1595,12 @@ #define STM32_HAS_DMA2D FALSE /* FSMC attributes.*/ -#define STM32_HAS_FSMC TRUE -#define STM32_FSMC_IS_FMC FALSE -#define STM32_FSMC_HANDLER Vector100 -#define STM32_FSMC_NUMBER 48 +#define STM32_HAS_FSMC FALSE /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE FALSE -/* DCMI attributes.*/ -#define STM32_HAS_DCMI FALSE - #endif /* defined(STM32F413xx) */ /*===========================================================================*/ @@ -2079,27 +1639,8 @@ /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE -#define STM32_CAN1_TX_HANDLER Vector8C -#define STM32_CAN1_RX0_HANDLER Vector90 -#define STM32_CAN1_RX1_HANDLER Vector94 -#define STM32_CAN1_SCE_HANDLER Vector98 -#define STM32_CAN1_TX_NUMBER 19 -#define STM32_CAN1_RX0_NUMBER 20 -#define STM32_CAN1_RX1_NUMBER 21 -#define STM32_CAN1_SCE_NUMBER 22 - #define STM32_HAS_CAN2 TRUE -#define STM32_CAN2_TX_HANDLER Vector13C -#define STM32_CAN2_RX0_HANDLER Vector140 -#define STM32_CAN2_RX1_HANDLER Vector144 -#define STM32_CAN2_SCE_HANDLER Vector148 -#define STM32_CAN2_TX_NUMBER 63 -#define STM32_CAN2_RX0_NUMBER 64 -#define STM32_CAN2_RX1_NUMBER 65 -#define STM32_CAN2_SCE_NUMBER 66 - #define STM32_HAS_CAN3 FALSE - #define STM32_CAN_MAX_FILTERS 28 /* DAC attributes.*/ @@ -2179,10 +1720,6 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_EVENT_HANDLER VectorBC -#define STM32_I2C1_ERROR_HANDLER VectorC0 -#define STM32_I2C1_EVENT_NUMBER 31 -#define STM32_I2C1_ERROR_NUMBER 32 #define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ STM32_DMA_STREAM_ID_MSK(1, 5)) #define STM32_I2C1_RX_DMA_CHN 0x00100001 @@ -2191,10 +1728,6 @@ #define STM32_I2C1_TX_DMA_CHN 0x11000000 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_EVENT_HANDLER VectorC4 -#define STM32_I2C2_ERROR_HANDLER VectorC8 -#define STM32_I2C2_EVENT_NUMBER 33 -#define STM32_I2C2_ERROR_NUMBER 34 #define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ STM32_DMA_STREAM_ID_MSK(1, 3)) #define STM32_I2C2_RX_DMA_CHN 0x00007700 @@ -2202,10 +1735,6 @@ #define STM32_I2C2_TX_DMA_CHN 0x70000000 #define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_EVENT_HANDLER Vector160 -#define STM32_I2C3_ERROR_HANDLER Vector164 -#define STM32_I2C3_EVENT_NUMBER 72 -#define STM32_I2C3_ERROR_NUMBER 73 #define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_I2C3_RX_DMA_CHN 0x00000300 #define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) @@ -2222,16 +1751,12 @@ /* SDIO attributes.*/ #define STM32_HAS_SDIO TRUE -#define STM32_SDIO_HANDLER Vector104 -#define STM32_SDIO_NUMBER 49 #define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ STM32_DMA_STREAM_ID_MSK(2, 6)) #define STM32_SDC_SDIO_DMA_CHN 0x04004000 /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_EVENT_HANDLER VectorCC -#define STM32_SPI1_EVENT_NUMBER 35 #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) @@ -2241,8 +1766,6 @@ #define STM32_SPI1_TX_DMA_CHN 0x00303000 #define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_EVENT_HANDLER VectorD0 -#define STM32_SPI2_EVENT_NUMBER 36 #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) @@ -2251,8 +1774,6 @@ #define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_EVENT_HANDLER Vector10C -#define STM32_SPI3_EVENT_NUMBER 51 #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ @@ -2263,8 +1784,6 @@ #define STM32_SPI3_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI4 TRUE -#define STM32_SPI4_EVENT_HANDLER Vector190 -#define STM32_SPI4_EVENT_NUMBER 84 #define STM32_SPI4_SUPPORTS_I2S FALSE #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ STM32_DMA_STREAM_ID_MSK(2, 3) |\ @@ -2275,8 +1794,6 @@ #define STM32_SPI4_TX_DMA_CHN 0x00050040 #define STM32_HAS_SPI5 TRUE -#define STM32_SPI5_EVENT_HANDLER Vector194 -#define STM32_SPI5_EVENT_NUMBER 85 #define STM32_SPI5_SUPPORTS_I2S FALSE #define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ STM32_DMA_STREAM_ID_MSK(2, 5)) @@ -2294,90 +1811,54 @@ #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 4 -#define STM32_TIM1_UP_HANDLER VectorA4 -#define STM32_TIM1_CC_HANDLER VectorAC -#define STM32_TIM1_UP_NUMBER 25 -#define STM32_TIM1_CC_NUMBER 27 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 -#define STM32_TIM2_HANDLER VectorB0 -#define STM32_TIM2_NUMBER 28 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 -#define STM32_TIM3_HANDLER VectorB4 -#define STM32_TIM3_NUMBER 29 #define STM32_HAS_TIM4 TRUE #define STM32_TIM4_IS_32BITS FALSE #define STM32_TIM4_CHANNELS 4 -#define STM32_TIM4_HANDLER VectorB8 -#define STM32_TIM4_NUMBER 30 #define STM32_HAS_TIM5 TRUE #define STM32_TIM5_IS_32BITS TRUE #define STM32_TIM5_CHANNELS 4 -#define STM32_TIM5_HANDLER Vector108 -#define STM32_TIM5_NUMBER 50 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 -#define STM32_TIM6_HANDLER Vector118 -#define STM32_TIM6_NUMBER 54 #define STM32_HAS_TIM7 TRUE #define STM32_TIM7_IS_32BITS FALSE #define STM32_TIM7_CHANNELS 0 -#define STM32_TIM7_HANDLER Vector11C -#define STM32_TIM7_NUMBER 55 - -#define STM32_HAS_TIM8 TRUE -#define STM32_TIM8_IS_32BITS FALSE -#define STM32_TIM8_CHANNELS 4 -#define STM32_TIM8_UP_HANDLER VectorF0 -#define STM32_TIM8_CC_HANDLER VectorF8 -#define STM32_TIM8_UP_NUMBER 44 -#define STM32_TIM8_CC_NUMBER 46 #define STM32_HAS_TIM9 TRUE #define STM32_TIM9_IS_32BITS FALSE #define STM32_TIM9_CHANNELS 2 -#define STM32_TIM9_HANDLER VectorA0 -#define STM32_TIM9_NUMBER 24 #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE #define STM32_TIM10_CHANNELS 1 -#define STM32_TIM10_HANDLER VectorA4 -#define STM32_TIM10_NUMBER 25 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE #define STM32_TIM11_CHANNELS 1 -#define STM32_TIM11_HANDLER VectorA8 -#define STM32_TIM11_NUMBER 26 #define STM32_HAS_TIM12 TRUE #define STM32_TIM12_IS_32BITS FALSE #define STM32_TIM12_CHANNELS 2 -#define STM32_TIM12_HANDLER VectorEC -#define STM32_TIM12_NUMBER 43 #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE #define STM32_TIM13_CHANNELS 1 -#define STM32_TIM13_HANDLER VectorF0 -#define STM32_TIM13_NUMBER 44 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE #define STM32_TIM14_CHANNELS 1 -#define STM32_TIM14_HANDLER VectorF4 -#define STM32_TIM14_NUMBER 45 #define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM15 FALSE @@ -2391,8 +1872,6 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_USART1_HANDLER VectorD4 -#define STM32_USART1_NUMBER 37 #define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ STM32_DMA_STREAM_ID_MSK(2, 5)) #define STM32_USART1_RX_DMA_CHN 0x00400400 @@ -2400,16 +1879,12 @@ #define STM32_USART1_TX_DMA_CHN 0x40000000 #define STM32_HAS_USART2 TRUE -#define STM32_USART2_HANDLER VectorD8 -#define STM32_USART2_NUMBER 38 #define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) #define STM32_USART2_RX_DMA_CHN 0x00400000 #define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) #define STM32_USART2_TX_DMA_CHN 0x04000000 #define STM32_HAS_USART3 TRUE -#define STM32_USART3_HANDLER VectorDC -#define STM32_USART3_NUMBER 39 #define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) #define STM32_USART3_RX_DMA_CHN 0x00000040 #define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ @@ -2417,8 +1892,6 @@ #define STM32_USART3_TX_DMA_CHN 0x00074000 #define STM32_HAS_USART6 TRUE -#define STM32_USART6_HANDLER Vector15C -#define STM32_USART6_NUMBER 71 #define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) #define STM32_USART6_RX_DMA_CHN 0x00000550 @@ -2435,8 +1908,6 @@ /* USB attributes.*/ #define STM32_OTG_STEPPING 2 #define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_HANDLER Vector14C -#define STM32_OTG1_NUMBER 67 #define STM32_OTG1_ENDPOINTS 5 #define STM32_HAS_OTG2 FALSE @@ -2453,18 +1924,12 @@ #define STM32_HAS_DMA2D FALSE /* FSMC attributes.*/ -#define STM32_HAS_FSMC TRUE -#define STM32_FSMC_IS_FMC FALSE -#define STM32_FSMC_HANDLER Vector100 -#define STM32_FSMC_NUMBER 48 +#define STM32_HAS_FSMC FALSE /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE FALSE -/* DCMI attributes.*/ -#define STM32_HAS_DCMI FALSE - #endif /* defined(STM32F412xx) */ /*===========================================================================*/ @@ -2581,10 +2046,6 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_EVENT_HANDLER VectorBC -#define STM32_I2C1_ERROR_HANDLER VectorC0 -#define STM32_I2C1_EVENT_NUMBER 31 -#define STM32_I2C1_ERROR_NUMBER 32 #define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ STM32_DMA_STREAM_ID_MSK(1, 5)) #define STM32_I2C1_RX_DMA_CHN 0x00100001 @@ -2594,10 +2055,6 @@ #define STM32_I2C1_TX_DMA_CHN 0x11000000 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_EVENT_HANDLER VectorC4 -#define STM32_I2C2_ERROR_HANDLER VectorC8 -#define STM32_I2C2_EVENT_NUMBER 33 -#define STM32_I2C2_ERROR_NUMBER 34 #define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ STM32_DMA_STREAM_ID_MSK(1, 3)) #define STM32_I2C2_RX_DMA_CHN 0x00007700 @@ -2605,10 +2062,6 @@ #define STM32_I2C2_TX_DMA_CHN 0x70000000 #define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_EVENT_HANDLER Vector160 -#define STM32_I2C3_ERROR_HANDLER Vector164 -#define STM32_I2C3_EVENT_NUMBER 72 -#define STM32_I2C3_ERROR_NUMBER 73 #define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ + STM32_DMA_STREAM_ID_MSK(1, 2)) #define STM32_I2C3_RX_DMA_CHN 0x00000310 @@ -2623,16 +2076,12 @@ /* SDIO attributes.*/ #define STM32_HAS_SDIO TRUE -#define STM32_SDIO_HANDLER Vector104 -#define STM32_SDIO_NUMBER 49 #define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ STM32_DMA_STREAM_ID_MSK(2, 6)) #define STM32_SDC_SDIO_DMA_CHN 0x04004000 /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_EVENT_HANDLER VectorCC -#define STM32_SPI1_EVENT_NUMBER 35 #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) @@ -2642,8 +2091,6 @@ #define STM32_SPI1_TX_DMA_CHN 0x00303000 #define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_EVENT_HANDLER VectorD0 -#define STM32_SPI2_EVENT_NUMBER 36 #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) @@ -2652,8 +2099,6 @@ #define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_EVENT_HANDLER Vector10C -#define STM32_SPI3_EVENT_NUMBER 51 #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ @@ -2664,8 +2109,6 @@ #define STM32_SPI3_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI4 TRUE -#define STM32_SPI4_EVENT_HANDLER Vector190 -#define STM32_SPI4_EVENT_NUMBER 84 #define STM32_SPI4_SUPPORTS_I2S FALSE #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ STM32_DMA_STREAM_ID_MSK(2, 3)) @@ -2675,8 +2118,6 @@ #define STM32_SPI4_TX_DMA_CHN 0x00050040 #define STM32_HAS_SPI5 TRUE -#define STM32_SPI5_EVENT_HANDLER Vector194 -#define STM32_SPI5_EVENT_NUMBER 85 #define STM32_SPI5_SUPPORTS_I2S FALSE #define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ STM32_DMA_STREAM_ID_MSK(2, 5)) @@ -2693,52 +2134,34 @@ #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 4 -#define STM32_TIM1_UP_HANDLER VectorA4 -#define STM32_TIM1_CC_HANDLER VectorAC -#define STM32_TIM1_UP_NUMBER 25 -#define STM32_TIM1_CC_NUMBER 27 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 -#define STM32_TIM2_HANDLER VectorB0 -#define STM32_TIM2_NUMBER 28 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 -#define STM32_TIM3_HANDLER VectorB4 -#define STM32_TIM3_NUMBER 29 #define STM32_HAS_TIM4 TRUE #define STM32_TIM4_IS_32BITS FALSE #define STM32_TIM4_CHANNELS 4 -#define STM32_TIM4_HANDLER VectorB8 -#define STM32_TIM4_NUMBER 30 #define STM32_HAS_TIM5 TRUE #define STM32_TIM5_IS_32BITS TRUE #define STM32_TIM5_CHANNELS 4 -#define STM32_TIM5_HANDLER Vector108 -#define STM32_TIM5_NUMBER 50 #define STM32_HAS_TIM9 TRUE #define STM32_TIM9_IS_32BITS FALSE #define STM32_TIM9_CHANNELS 2 -#define STM32_TIM9_HANDLER VectorA0 -#define STM32_TIM9_NUMBER 24 #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE #define STM32_TIM10_CHANNELS 1 -#define STM32_TIM10_HANDLER VectorA4 -#define STM32_TIM10_NUMBER 25 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE #define STM32_TIM11_CHANNELS 1 -#define STM32_TIM11_HANDLER VectorA8 -#define STM32_TIM11_NUMBER 26 #define STM32_HAS_TIM6 FALSE #define STM32_HAS_TIM7 FALSE @@ -2757,8 +2180,6 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_USART1_HANDLER VectorD4 -#define STM32_USART1_NUMBER 37 #define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ STM32_DMA_STREAM_ID_MSK(2, 5)) #define STM32_USART1_RX_DMA_CHN 0x00400400 @@ -2766,8 +2187,6 @@ #define STM32_USART1_TX_DMA_CHN 0x40000000 #define STM32_HAS_USART2 TRUE -#define STM32_USART2_HANDLER VectorD8 -#define STM32_USART2_NUMBER 38 #define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) #define STM32_USART2_RX_DMA_CHN 0x00400000 #define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) @@ -2778,8 +2197,6 @@ #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 TRUE -#define STM32_USART6_HANDLER Vector15C -#define STM32_USART6_NUMBER 71 #define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) #define STM32_USART6_RX_DMA_CHN 0x00000550 @@ -2794,8 +2211,6 @@ /* USB attributes.*/ #define STM32_OTG_STEPPING 1 #define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_HANDLER Vector14C -#define STM32_OTG1_NUMBER 67 #define STM32_OTG1_ENDPOINTS 3 #define STM32_HAS_OTG2 FALSE @@ -2818,9 +2233,6 @@ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE FALSE -/* DCMI attributes.*/ -#define STM32_HAS_DCMI FALSE - #endif /* defined(STM32F411xx) */ /*===========================================================================*/ @@ -2940,10 +2352,6 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_EVENT_HANDLER VectorBC -#define STM32_I2C1_ERROR_HANDLER VectorC0 -#define STM32_I2C1_EVENT_NUMBER 31 -#define STM32_I2C1_ERROR_NUMBER 32 #define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ STM32_DMA_STREAM_ID_MSK(1, 5)) #define STM32_I2C1_RX_DMA_CHN 0x00100001 @@ -2952,10 +2360,6 @@ #define STM32_I2C1_TX_DMA_CHN 0x11000000 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_EVENT_HANDLER VectorC4 -#define STM32_I2C2_ERROR_HANDLER VectorC8 -#define STM32_I2C2_EVENT_NUMBER 33 -#define STM32_I2C2_ERROR_NUMBER 34 #define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ STM32_DMA_STREAM_ID_MSK(1, 3)) #define STM32_I2C2_RX_DMA_CHN 0x00007700 @@ -2964,14 +2368,10 @@ #define STM32_HAS_I2C3 FALSE -#define STM32_HAS_I2C4 TRUE -#define STM32_I2C4_EVENT_HANDLER Vector1C0 -#define STM32_I2C4_EVENT_NUMBER 95 -#define STM32_I2C4_ERROR_HANDLER Vector1C4 -#define STM32_I2C4_ERROR_NUMBER 96 +#define STM32_HAS_I2C4 FALSE #define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0)) |\ STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_I2C4_RX_DMA_CHN 0x00001007 +#define STM32_I2C4_RX_DMA_CHN 0x00002007 #define STM32_I2C4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) |\ STM32_DMA_STREAM_ID_MSK(1, 1)) #define STM32_I2C4_TX_DMA_CHN 0x00040020 @@ -2984,8 +2384,6 @@ /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SDIO_HANDLER Vector104 -#define STM32_SDIO_NUMBER 49 #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) @@ -2995,8 +2393,6 @@ #define STM32_SPI1_TX_DMA_CHN 0x00003200 #define STM32_HAS_SPI2 TRUE -#define STM32_SPI1_EVENT_HANDLER VectorCC -#define STM32_SPI1_EVENT_NUMBER 35 #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) @@ -3005,8 +2401,6 @@ #define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI5 TRUE -#define STM32_SPI5_EVENT_HANDLER Vector194 -#define STM32_SPI5_EVENT_NUMBER 85 #define STM32_SPI5_SUPPORTS_I2S TRUE #define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ STM32_DMA_STREAM_ID_MSK(2, 5)) @@ -3025,34 +2419,22 @@ #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 4 -#define STM32_TIM1_UP_HANDLER VectorA4 -#define STM32_TIM1_CC_HANDLER VectorAC -#define STM32_TIM1_UP_NUMBER 25 -#define STM32_TIM1_CC_NUMBER 27 #define STM32_HAS_TIM5 TRUE #define STM32_TIM5_IS_32BITS TRUE #define STM32_TIM5_CHANNELS 4 -#define STM32_TIM5_HANDLER Vector108 -#define STM32_TIM5_NUMBER 50 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 -#define STM32_TIM6_HANDLER Vector118 -#define STM32_TIM6_NUMBER 54 #define STM32_HAS_TIM9 TRUE #define STM32_TIM9_IS_32BITS FALSE #define STM32_TIM9_CHANNELS 2 -#define STM32_TIM9_HANDLER VectorA0 -#define STM32_TIM9_NUMBER 24 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE #define STM32_TIM11_CHANNELS 1 -#define STM32_TIM11_HANDLER VectorA8 -#define STM32_TIM11_NUMBER 26 #define STM32_HAS_TIM2 FALSE #define STM32_HAS_TIM3 FALSE @@ -3074,8 +2456,6 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_USART1_HANDLER VectorD4 -#define STM32_USART1_NUMBER 37 #define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ STM32_DMA_STREAM_ID_MSK(2, 5)) #define STM32_USART1_RX_DMA_CHN 0x00400400 @@ -3083,8 +2463,6 @@ #define STM32_USART1_TX_DMA_CHN 0x40000000 #define STM32_HAS_USART2 TRUE -#define STM32_USART2_HANDLER VectorD8 -#define STM32_USART2_NUMBER 38 #define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ STM32_DMA_STREAM_ID_MSK(1, 7)) #define STM32_USART2_RX_DMA_CHN 0x60400000 @@ -3096,8 +2474,6 @@ #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 TRUE -#define STM32_USART6_HANDLER Vector15C -#define STM32_USART6_NUMBER 71 #define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) #define STM32_USART6_RX_DMA_CHN 0x00000550 @@ -3131,9 +2507,6 @@ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE FALSE -/* DCMI attributes.*/ -#define STM32_HAS_DCMI FALSE - #endif /* defined(STM32F410xx) */ /*===========================================================================*/ @@ -3183,27 +2556,8 @@ /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE -#define STM32_CAN1_TX_HANDLER Vector8C -#define STM32_CAN1_RX0_HANDLER Vector90 -#define STM32_CAN1_RX1_HANDLER Vector94 -#define STM32_CAN1_SCE_HANDLER Vector98 -#define STM32_CAN1_TX_NUMBER 19 -#define STM32_CAN1_RX0_NUMBER 20 -#define STM32_CAN1_RX1_NUMBER 21 -#define STM32_CAN1_SCE_NUMBER 22 - #define STM32_HAS_CAN2 TRUE -#define STM32_CAN2_TX_HANDLER Vector13C -#define STM32_CAN2_RX0_HANDLER Vector140 -#define STM32_CAN2_RX1_HANDLER Vector144 -#define STM32_CAN2_SCE_HANDLER Vector148 -#define STM32_CAN2_TX_NUMBER 63 -#define STM32_CAN2_RX0_NUMBER 64 -#define STM32_CAN2_RX1_NUMBER 65 -#define STM32_CAN2_SCE_NUMBER 66 - #define STM32_HAS_CAN3 FALSE - #define STM32_CAN_MAX_FILTERS 28 /* DAC attributes.*/ @@ -3297,10 +2651,6 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_EVENT_HANDLER VectorBC -#define STM32_I2C1_ERROR_HANDLER VectorC0 -#define STM32_I2C1_EVENT_NUMBER 31 -#define STM32_I2C1_ERROR_NUMBER 32 #define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ STM32_DMA_STREAM_ID_MSK(1, 5)) #define STM32_I2C1_RX_DMA_CHN 0x00100001 @@ -3309,10 +2659,6 @@ #define STM32_I2C1_TX_DMA_CHN 0x11000000 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_EVENT_HANDLER VectorC4 -#define STM32_I2C2_ERROR_HANDLER VectorC8 -#define STM32_I2C2_EVENT_NUMBER 33 -#define STM32_I2C2_ERROR_NUMBER 34 #define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ STM32_DMA_STREAM_ID_MSK(1, 3)) #define STM32_I2C2_RX_DMA_CHN 0x00007700 @@ -3320,10 +2666,6 @@ #define STM32_I2C2_TX_DMA_CHN 0x70000000 #define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_EVENT_HANDLER Vector160 -#define STM32_I2C3_ERROR_HANDLER Vector164 -#define STM32_I2C3_EVENT_NUMBER 72 -#define STM32_I2C3_ERROR_NUMBER 73 #define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_I2C3_RX_DMA_CHN 0x00000300 #define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) @@ -3336,16 +2678,12 @@ /* SDIO attributes.*/ #define STM32_HAS_SDIO TRUE -#define STM32_SDIO_HANDLER Vector104 -#define STM32_SDIO_NUMBER 49 #define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ STM32_DMA_STREAM_ID_MSK(2, 6)) #define STM32_SDC_SDIO_DMA_CHN 0x04004000 /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_EVENT_HANDLER VectorCC -#define STM32_SPI1_EVENT_NUMBER 35 #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) @@ -3355,8 +2693,6 @@ #define STM32_SPI1_TX_DMA_CHN 0x00303000 #define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_EVENT_HANDLER VectorD0 -#define STM32_SPI2_EVENT_NUMBER 36 #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) @@ -3365,8 +2701,6 @@ #define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_EVENT_HANDLER Vector10C -#define STM32_SPI3_EVENT_NUMBER 51 #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ @@ -3386,90 +2720,58 @@ #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 4 -#define STM32_TIM1_UP_HANDLER VectorA4 -#define STM32_TIM1_CC_HANDLER VectorAC -#define STM32_TIM1_UP_NUMBER 25 -#define STM32_TIM1_CC_NUMBER 27 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 -#define STM32_TIM2_HANDLER VectorB0 -#define STM32_TIM2_NUMBER 28 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 -#define STM32_TIM3_HANDLER VectorB4 -#define STM32_TIM3_NUMBER 29 #define STM32_HAS_TIM4 TRUE #define STM32_TIM4_IS_32BITS FALSE #define STM32_TIM4_CHANNELS 4 -#define STM32_TIM4_HANDLER VectorB8 -#define STM32_TIM4_NUMBER 30 #define STM32_HAS_TIM5 TRUE #define STM32_TIM5_IS_32BITS TRUE #define STM32_TIM5_CHANNELS 4 -#define STM32_TIM5_HANDLER Vector108 -#define STM32_TIM5_NUMBER 50 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 -#define STM32_TIM6_HANDLER Vector118 -#define STM32_TIM6_NUMBER 54 #define STM32_HAS_TIM7 TRUE #define STM32_TIM7_IS_32BITS FALSE #define STM32_TIM7_CHANNELS 0 -#define STM32_TIM7_HANDLER Vector11C -#define STM32_TIM7_NUMBER 55 #define STM32_HAS_TIM8 TRUE #define STM32_TIM8_IS_32BITS FALSE -#define STM32_TIM8_CHANNELS 4 -#define STM32_TIM8_UP_HANDLER VectorF0 -#define STM32_TIM8_CC_HANDLER VectorF8 -#define STM32_TIM8_UP_NUMBER 44 -#define STM32_TIM8_CC_NUMBER 46 +#define STM32_TIM8_CHANNELS 6 #define STM32_HAS_TIM9 TRUE #define STM32_TIM9_IS_32BITS FALSE #define STM32_TIM9_CHANNELS 2 -#define STM32_TIM9_HANDLER VectorA0 -#define STM32_TIM9_NUMBER 24 #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE #define STM32_TIM10_CHANNELS 1 -#define STM32_TIM10_HANDLER VectorA4 -#define STM32_TIM10_NUMBER 25 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE #define STM32_TIM11_CHANNELS 1 -#define STM32_TIM11_HANDLER VectorA8 -#define STM32_TIM11_NUMBER 26 #define STM32_HAS_TIM12 TRUE #define STM32_TIM12_IS_32BITS FALSE #define STM32_TIM12_CHANNELS 2 -#define STM32_TIM12_HANDLER VectorEC -#define STM32_TIM12_NUMBER 43 #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE #define STM32_TIM13_CHANNELS 1 -#define STM32_TIM13_HANDLER VectorF0 -#define STM32_TIM13_NUMBER 44 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE #define STM32_TIM14_CHANNELS 1 -#define STM32_TIM14_HANDLER VectorF4 -#define STM32_TIM14_NUMBER 45 #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE @@ -3482,8 +2784,6 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_USART1_HANDLER VectorD4 -#define STM32_USART1_NUMBER 37 #define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ STM32_DMA_STREAM_ID_MSK(2, 5)) #define STM32_USART1_RX_DMA_CHN 0x00400400 @@ -3491,16 +2791,12 @@ #define STM32_USART1_TX_DMA_CHN 0x40000000 #define STM32_HAS_USART2 TRUE -#define STM32_USART2_HANDLER VectorD8 -#define STM32_USART2_NUMBER 38 #define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) #define STM32_USART2_RX_DMA_CHN 0x00400000 #define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) #define STM32_USART2_TX_DMA_CHN 0x04000000 #define STM32_HAS_USART3 TRUE -#define STM32_USART3_HANDLER VectorDC -#define STM32_USART3_NUMBER 39 #define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) #define STM32_USART3_RX_DMA_CHN 0x00000040 #define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ @@ -3508,24 +2804,18 @@ #define STM32_USART3_TX_DMA_CHN 0x00074000 #define STM32_HAS_UART4 TRUE -#define STM32_UART4_HANDLER Vector110 -#define STM32_UART4_NUMBER 52 #define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_UART4_RX_DMA_CHN 0x00000400 #define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) #define STM32_UART4_TX_DMA_CHN 0x00040000 #define STM32_HAS_UART5 TRUE -#define STM32_UART5_HANDLER Vector114 -#define STM32_UART5_NUMBER 53 #define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) #define STM32_UART5_RX_DMA_CHN 0x00000004 #define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) #define STM32_UART5_TX_DMA_CHN 0x40000000 #define STM32_HAS_USART6 TRUE -#define STM32_USART6_HANDLER Vector15C -#define STM32_USART6_NUMBER 71 #define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) #define STM32_USART6_RX_DMA_CHN 0x00000550 @@ -3540,16 +2830,8 @@ /* USB attributes.*/ #define STM32_OTG_STEPPING 1 #define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_HANDLER Vector14C -#define STM32_OTG1_NUMBER 67 #define STM32_OTG1_ENDPOINTS 3 #define STM32_HAS_OTG2 TRUE -#define STM32_OTG2_HANDLER Vector174 -#define STM32_OTG2_EP1OUT_HANDLER Vector168 -#define STM32_OTG2_EP1IN_HANDLER Vector16C -#define STM32_OTG2_NUMBER 77 -#define STM32_OTG2_EP1OUT_NUMBER 74 -#define STM32_OTG2_EP1IN_NUMBER 75 #define STM32_OTG2_ENDPOINTS 5 #define STM32_HAS_USB FALSE @@ -3567,16 +2849,11 @@ /* FSMC attributes.*/ #define STM32_HAS_FSMC TRUE #define STM32_FSMC_IS_FMC FALSE -#define STM32_FSMC_HANDLER Vector100 -#define STM32_FSMC_NUMBER 48 /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE FALSE -/* DCMI attributes.*/ -#define STM32_HAS_DCMI FALSE - #endif /* defined(STM32F40_41xxx) || defined(STM32F2XX) */ /*===========================================================================*/ @@ -3623,27 +2900,8 @@ /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE -#define STM32_CAN1_TX_HANDLER Vector8C -#define STM32_CAN1_RX0_HANDLER Vector90 -#define STM32_CAN1_RX1_HANDLER Vector94 -#define STM32_CAN1_SCE_HANDLER Vector98 -#define STM32_CAN1_TX_NUMBER 19 -#define STM32_CAN1_RX0_NUMBER 20 -#define STM32_CAN1_RX1_NUMBER 21 -#define STM32_CAN1_SCE_NUMBER 22 - #define STM32_HAS_CAN2 TRUE -#define STM32_CAN2_TX_HANDLER Vector13C -#define STM32_CAN2_RX0_HANDLER Vector140 -#define STM32_CAN2_RX1_HANDLER Vector144 -#define STM32_CAN2_SCE_HANDLER Vector148 -#define STM32_CAN2_TX_NUMBER 63 -#define STM32_CAN2_RX0_NUMBER 64 -#define STM32_CAN2_RX1_NUMBER 65 -#define STM32_CAN2_SCE_NUMBER 66 - #define STM32_HAS_CAN3 FALSE - #define STM32_CAN_MAX_FILTERS 28 /* DAC attributes.*/ @@ -3720,10 +2978,6 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_EVENT_HANDLER VectorBC -#define STM32_I2C1_ERROR_HANDLER VectorC0 -#define STM32_I2C1_EVENT_NUMBER 31 -#define STM32_I2C1_ERROR_NUMBER 32 #define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ STM32_DMA_STREAM_ID_MSK(1, 5)) #define STM32_I2C1_RX_DMA_CHN 0x00100001 @@ -3732,10 +2986,6 @@ #define STM32_I2C1_TX_DMA_CHN 0x11000000 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_EVENT_HANDLER VectorC4 -#define STM32_I2C2_ERROR_HANDLER VectorC8 -#define STM32_I2C2_EVENT_NUMBER 33 -#define STM32_I2C2_ERROR_NUMBER 34 #define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ STM32_DMA_STREAM_ID_MSK(1, 3)) #define STM32_I2C2_RX_DMA_CHN 0x00007700 @@ -3743,10 +2993,6 @@ #define STM32_I2C2_TX_DMA_CHN 0x70000000 #define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_EVENT_HANDLER Vector160 -#define STM32_I2C3_ERROR_HANDLER Vector164 -#define STM32_I2C3_EVENT_NUMBER 72 -#define STM32_I2C3_ERROR_NUMBER 73 #define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_I2C3_RX_DMA_CHN 0x00000300 #define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) @@ -3759,16 +3005,12 @@ /* SDIO attributes.*/ #define STM32_HAS_SDIO TRUE -#define STM32_SDIO_HANDLER Vector104 -#define STM32_SDIO_NUMBER 49 #define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ STM32_DMA_STREAM_ID_MSK(2, 6)) #define STM32_SDC_SDIO_DMA_CHN 0x04004000 /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_EVENT_HANDLER VectorCC -#define STM32_SPI1_EVENT_NUMBER 35 #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) @@ -3778,8 +3020,6 @@ #define STM32_SPI1_TX_DMA_CHN 0x00303000 #define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_EVENT_HANDLER VectorD0 -#define STM32_SPI2_EVENT_NUMBER 36 #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) @@ -3788,8 +3028,6 @@ #define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_EVENT_HANDLER Vector10C -#define STM32_SPI3_EVENT_NUMBER 51 #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ @@ -3800,8 +3038,6 @@ #define STM32_SPI3_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI4 TRUE -#define STM32_SPI4_EVENT_HANDLER Vector190 -#define STM32_SPI4_EVENT_NUMBER 84 #define STM32_SPI4_SUPPORTS_I2S FALSE #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ STM32_DMA_STREAM_ID_MSK(2, 3)) @@ -3896,8 +3132,6 @@ /* USB attributes.*/ #define STM32_OTG_STEPPING 1 #define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_HANDLER Vector14C -#define STM32_OTG1_NUMBER 67 #define STM32_OTG1_ENDPOINTS 3 #define STM32_HAS_OTG2 FALSE @@ -3920,9 +3154,6 @@ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE FALSE -/* DCMI attributes.*/ -#define STM32_HAS_DCMI FALSE - #endif /* defined(STM32F401xx) */ /** @} */