diff --git a/demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/mcuconf.h b/demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/mcuconf.h
index 29e736380..1915123e1 100644
--- a/demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/mcuconf.h
@@ -146,10 +146,10 @@
  * SERIAL driver system settings.
  */
 #define STM32_SERIAL_USE_USART1             FALSE
-#define STM32_SERIAL_USE_USART2             FALSE
+#define STM32_SERIAL_USE_USART2             TRUE
 #define STM32_SERIAL_USE_USART3             FALSE
 #define STM32_SERIAL_USE_UART4              FALSE
-#define STM32_SERIAL_USE_LPUART1            TRUE
+#define STM32_SERIAL_USE_LPUART1            FALSE
 #define STM32_SERIAL_USART1_PRIORITY        3
 #define STM32_SERIAL_USART2_PRIORITY        3
 #define STM32_SERIAL_USART3_PRIORITY        3
diff --git a/demos/STM32/RT-STM32G071RB-NUCLEO64/main.c b/demos/STM32/RT-STM32G071RB-NUCLEO64/main.c
index 13ae31604..9a0a413c3 100644
--- a/demos/STM32/RT-STM32G071RB-NUCLEO64/main.c
+++ b/demos/STM32/RT-STM32G071RB-NUCLEO64/main.c
@@ -53,7 +53,7 @@ int main(void) {
   /*
    * Activates the serial driver 2 using the driver default configuration.
    */
-  sdStart(&LPSD1, NULL);
+  sdStart(&SD2, NULL);
 
   /*
    * Creates the blinker thread.
@@ -66,8 +66,8 @@ int main(void) {
    */
   while (true) {
    if (!palReadLine(LINE_BUTTON)) {
-      test_execute((BaseSequentialStream *)&LPSD1, &rt_test_suite);
-      test_execute((BaseSequentialStream *)&LPSD1, &oslib_test_suite);
+      test_execute((BaseSequentialStream *)&SD2, &rt_test_suite);
+      test_execute((BaseSequentialStream *)&SD2, &oslib_test_suite);
     }
     chThdSleepMilliseconds(500);
  }
diff --git a/os/hal/boards/ST_NUCLEO64_G071RB/board.c b/os/hal/boards/ST_NUCLEO64_G071RB/board.c
index fbea4c400..11eee2a80 100644
--- a/os/hal/boards/ST_NUCLEO64_G071RB/board.c
+++ b/os/hal/boards/ST_NUCLEO64_G071RB/board.c
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -259,7 +259,7 @@ bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
 
 /**
  * @brief   Board-specific initialization code.
- * @note    You can add your board-specific code here.
+ * @note    Add your board-specific code, if any.
  */
 void boardInit(void) {
 
diff --git a/os/hal/boards/ST_NUCLEO64_G071RB/board.h b/os/hal/boards/ST_NUCLEO64_G071RB/board.h
index b561f350c..d8dc9322c 100644
--- a/os/hal/boards/ST_NUCLEO64_G071RB/board.h
+++ b/os/hal/boards/ST_NUCLEO64_G071RB/board.h
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -49,8 +49,6 @@
 #define STM32_HSECLK                8000000U
 #endif
 
-#define STM32_HSE_BYPASS
-
 /*
  * MCU type as defined in the ST header.
  */
@@ -79,7 +77,7 @@
 #define GPIOB_PIN0                  0U
 #define GPIOB_PIN1                  1U
 #define GPIOB_PIN2                  2U
-#define GPIOB_SWO                   3U
+#define GPIOB_PIN3                  3U
 #define GPIOB_PIN4                  4U
 #define GPIOB_PIN5                  5U
 #define GPIOB_PIN6                  6U
@@ -152,7 +150,6 @@
 #define LINE_LED_GREEN              PAL_LINE(GPIOA, 5U)
 #define LINE_SWDIO                  PAL_LINE(GPIOA, 13U)
 #define LINE_SWCLK                  PAL_LINE(GPIOA, 14U)
-#define LINE_SWO                    PAL_LINE(GPIOB, 3U)
 #define LINE_BUTTON                 PAL_LINE(GPIOC, 13U)
 #define LINE_OSC32_IN               PAL_LINE(GPIOC, 14U)
 #define LINE_OSC32_OUT              PAL_LINE(GPIOC, 15U)
@@ -320,7 +317,7 @@
  * PB0  - PIN0                      (input pullup).
  * PB1  - PIN1                      (input pullup).
  * PB2  - PIN2                      (input pullup).
- * PB3  - SWO                       (alternate 0).
+ * PB3  - PIN3                      (input pullup).
  * PB4  - PIN4                      (input pullup).
  * PB5  - PIN5                      (input pullup).
  * PB6  - PIN6                      (input pullup).
@@ -337,7 +334,7 @@
 #define VAL_GPIOB_MODER             (PIN_MODE_INPUT(GPIOB_PIN0) |           \
                                      PIN_MODE_INPUT(GPIOB_PIN1) |           \
                                      PIN_MODE_INPUT(GPIOB_PIN2) |           \
-                                     PIN_MODE_ALTERNATE(GPIOB_SWO) |        \
+                                     PIN_MODE_INPUT(GPIOB_PIN3) |           \
                                      PIN_MODE_INPUT(GPIOB_PIN4) |           \
                                      PIN_MODE_INPUT(GPIOB_PIN5) |           \
                                      PIN_MODE_INPUT(GPIOB_PIN6) |           \
@@ -353,7 +350,7 @@
 #define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) |       \
                                      PIN_OTYPE_PUSHPULL(GPIOB_PIN1) |       \
                                      PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \
-                                     PIN_OTYPE_PUSHPULL(GPIOB_SWO) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN3) |       \
                                      PIN_OTYPE_PUSHPULL(GPIOB_PIN4) |       \
                                      PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |       \
                                      PIN_OTYPE_PUSHPULL(GPIOB_PIN6) |       \
@@ -369,7 +366,7 @@
 #define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_HIGH(GPIOB_PIN0) |          \
                                      PIN_OSPEED_HIGH(GPIOB_PIN1) |          \
                                      PIN_OSPEED_HIGH(GPIOB_PIN2) |          \
-                                     PIN_OSPEED_HIGH(GPIOB_SWO) |           \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN3) |          \
                                      PIN_OSPEED_HIGH(GPIOB_PIN4) |          \
                                      PIN_OSPEED_HIGH(GPIOB_PIN5) |          \
                                      PIN_OSPEED_HIGH(GPIOB_PIN6) |          \
@@ -385,7 +382,7 @@
 #define VAL_GPIOB_PUPDR             (PIN_PUPDR_PULLUP(GPIOB_PIN0) |         \
                                      PIN_PUPDR_PULLUP(GPIOB_PIN1) |         \
                                      PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \
-                                     PIN_PUPDR_PULLUP(GPIOB_SWO) |          \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN3) |         \
                                      PIN_PUPDR_PULLUP(GPIOB_PIN4) |         \
                                      PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \
                                      PIN_PUPDR_PULLUP(GPIOB_PIN6) |         \
@@ -401,7 +398,7 @@
 #define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_PIN0) |             \
                                      PIN_ODR_HIGH(GPIOB_PIN1) |             \
                                      PIN_ODR_HIGH(GPIOB_PIN2) |             \
-                                     PIN_ODR_HIGH(GPIOB_SWO) |              \
+                                     PIN_ODR_HIGH(GPIOB_PIN3) |             \
                                      PIN_ODR_HIGH(GPIOB_PIN4) |             \
                                      PIN_ODR_HIGH(GPIOB_PIN5) |             \
                                      PIN_ODR_HIGH(GPIOB_PIN6) |             \
@@ -417,7 +414,7 @@
 #define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_PIN0, 0U) |          \
                                      PIN_AFIO_AF(GPIOB_PIN1, 0U) |          \
                                      PIN_AFIO_AF(GPIOB_PIN2, 0U) |          \
-                                     PIN_AFIO_AF(GPIOB_SWO, 0U) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN3, 0U) |          \
                                      PIN_AFIO_AF(GPIOB_PIN4, 0U) |          \
                                      PIN_AFIO_AF(GPIOB_PIN5, 0U) |          \
                                      PIN_AFIO_AF(GPIOB_PIN6, 0U) |          \
diff --git a/os/hal/boards/ST_NUCLEO64_G071RB/cfg/board.chcfg b/os/hal/boards/ST_NUCLEO64_G071RB/cfg/board.chcfg
index 2f719ace9..a57acffe3 100644
--- a/os/hal/boards/ST_NUCLEO64_G071RB/cfg/board.chcfg
+++ b/os/hal/boards/ST_NUCLEO64_G071RB/cfg/board.chcfg
@@ -12,7 +12,7 @@
   <board_id>ST_NUCLEO64_G071RB</board_id>
   <board_functions></board_functions>
   <subtype>STM32G071xB</subtype>
-  <clocks HSEFrequency="8000000" HSEBypass="true" LSEFrequency="32768"
+  <clocks HSEFrequency="8000000" HSEBypass="false" LSEFrequency="32768"
   	LSEBypass="false" LSEDrive="3 High Drive (default)" />
   <ports>
     <GPIOA>
@@ -171,12 +171,12 @@
         Mode="Input"
         Alternate="0" />
       <pin3
-        ID="SWO"
+        ID=""
         Type="PushPull"
         Level="High"
         Speed="Maximum"
         Resistor="PullUp"
-        Mode="Alternate"
+        Mode="Input"
         Alternate="0" />
       <pin4
         ID=""
diff --git a/os/hal/boards/ST_NUCLEO64_G071RB/cfg/board.fmpp b/os/hal/boards/ST_NUCLEO64_G071RB/cfg/board.fmpp
index b3ba947fb..b24df35d0 100644
--- a/os/hal/boards/ST_NUCLEO64_G071RB/cfg/board.fmpp
+++ b/os/hal/boards/ST_NUCLEO64_G071RB/cfg/board.fmpp
@@ -1,4 +1,4 @@
-sourceRoot: ../../../../../tools/ftl/processors/boards/stm32l0xx/templates
+sourceRoot: ../../../../../tools/ftl/processors/boards/stm32g0xx/templates
 outputRoot: ..
 dataRoot: .
 
diff --git a/os/hal/ports/STM32/STM32G0xx/hal_lld.h b/os/hal/ports/STM32/STM32G0xx/hal_lld.h
index 5eac26b9c..9b88e423c 100644
--- a/os/hal/ports/STM32/STM32G0xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32G0xx/hal_lld.h
@@ -154,8 +154,8 @@
 #define STM32_HPRE_DIV256       STM32_HPRE_FIELD(14U)
 #define STM32_HPRE_DIV512       STM32_HPRE_FIELD(15U)
 
-#define STM32_PPRE_MASK         (7U << 12U) /**< PPRE field mask.           */
-#define STM32_PPRE_FIELD(n)     (7U << 12U) /**< PPRE field value.          */
+#define STM32_PPRE_MASK         (7U << 12U)  /**< PPRE field mask.          */
+#define STM32_PPRE_FIELD(n)     ((n) << 12U) /**< PPRE field value.         */
 #define STM32_PPRE_DIV1         STM32_PPRE_FIELD(0U)
 #define STM32_PPRE_DIV2         STM32_PPRE_FIELD(4U)
 #define STM32_PPRE_DIV4         STM32_PPRE_FIELD(5U)
@@ -167,7 +167,7 @@
 #define STM32_MCOSEL_SYSCLK     (1U << 24U) /**< SYSCLK on MCO pin.         */
 #define STM32_MCOSEL_HSI16      (3U << 24U) /**< HSI16 clock on MCO pin.    */
 #define STM32_MCOSEL_HSE        (4U << 24U) /**< HSE clock on MCO pin.      */
-#define STM32_MCOSEL_PLLRCLK    (5U << 24U) /**< PLLR clock on MCO pin.      */
+#define STM32_MCOSEL_PLLRCLK    (5U << 24U) /**< PLLR clock on MCO pin.     */
 #define STM32_MCOSEL_LSI        (6U << 24U) /**< LSI clock on MCO pin.      */
 #define STM32_MCOSEL_LSE        (7U << 24U) /**< LSE clock on MCO pin.      */
 
@@ -379,7 +379,7 @@
 
 /**
  * @brief   PLLM divider value.
- * @note    The allowed values are 1..16.
+ * @note    The allowed values are 1..8.
  * @note    The default value is calculated for a 64MHz system clock from
  *          the internal 16MHz HSI clock.
  */
@@ -665,7 +665,7 @@
 /**
  * @brief   Minimum VCO clock frequency at current voltage setting.
  */
-#define STM32_PLLVCO_MIN            96000000
+#define STM32_PLLVCO_MIN            64000000
 
 /**
  * @brief   Maximum PLL-P output clock frequency.
@@ -722,8 +722,8 @@
 
 #elif STM32_VOS == STM32_VOS_RANGE2
 #define STM32_SYSCLK_MAX            16000000
-#define STM32_HSECLK_MAX            26000000
-#define STM32_HSECLK_BYP_MAX        26000000
+#define STM32_HSECLK_MAX            16000000
+#define STM32_HSECLK_BYP_MAX        16000000
 #define STM32_HSECLK_MIN            4000000
 #define STM32_HSECLK_BYP_MIN        8000000
 #define STM32_LSECLK_MAX            32768
@@ -736,7 +736,7 @@
 #define STM32_PLLVCO_MIN            96000000
 #define STM32_PLLP_MAX              40000000
 #define STM32_PLLP_MIN              3090000
-#define STM32_PLLQ_MAX              33000000
+#define STM32_PLLQ_MAX              32000000
 #define STM32_PLLQ_MIN              12000000
 #define STM32_PLLR_MAX              16000000
 #define STM32_PLLR_MIN              12000000
@@ -909,21 +909,21 @@
  * @brief   STM32_HSIDIV field.
  */
 #if (STM32_HSIDIV_VALUE == 1) || defined(__DOXYGEN__)
-#define STM32_HSIDIV                (0U << 11U)
+#define STM32_HSIDIV                STM32_HSIDIV_1
 #elif STM32_HSIDIV_VALUE == 2
-#define STM32_HSIDIV                (1U << 11U)
+#define STM32_HSIDIV                STM32_HSIDIV_2
 #elif STM32_HSIDIV_VALUE == 4
-#define STM32_HSIDIV                (2U << 11U)
+#define STM32_HSIDIV                STM32_HSIDIV_4
 #elif STM32_HSIDIV_VALUE == 8
-#define STM32_HSIDIV                (3U << 11U)
+#define STM32_HSIDIV                STM32_HSIDIV_8
 #elif STM32_HSIDIV_VALUE == 16
-#define STM32_HSIDIV                (4U << 11U)
+#define STM32_HSIDIV                STM32_HSIDIV_16
 #elif STM32_HSIDIV_VALUE == 32
-#define STM32_HSIDIV                (5U << 11U)
+#define STM32_HSIDIV                STM32_HSIDIV_32
 #elif STM32_HSIDIV_VALUE == 64
-#define STM32_HSIDIV                (6U << 11U)
+#define STM32_HSIDIV                STM32_HSIDIV_64
 #elif STM32_HSIDIV_VALUE == 128
-#define STM32_HSIDIV                (7U << 11U)
+#define STM32_HSIDIV                STM32_HSIDIV_128
 #else
 #error "invalid STM32_HSIDIV_VALUE value specified"
 #endif