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ChibiOS
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Renamed some DAC identifiers for consistency. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7947 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2015-05-03 13:06:37 +00:00
parent f180c606d8
commit f713242deb
4 changed files with 58 additions and 52 deletions
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38
os/hal/ports/STM32/LLD/DACv1/dac_lld.c
View File

@ -36,19 +36,19 @@
#endif
#define DAC1_CH1_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_DAC1_CH1_DMA_STREAM, \
STM32_DMA_GETCHANNEL(STM32_DAC_DAC1_CH1_DMA_STREAM, \
STM32_DAC1_CH1_DMA_CHN)
#define DAC1_CH2_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_DAC1_CH2_DMA_STREAM, \
STM32_DMA_GETCHANNEL(STM32_DAC_DAC1_CH2_DMA_STREAM, \
STM32_DAC1_CH2_DMA_CHN)
#define DAC2_CH1_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_DAC2_CH1_DMA_STREAM, \
STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH1_DMA_STREAM, \
STM32_DAC2_CH1_DMA_CHN)
#define DAC2_CH2_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_DAC2_CH2_DMA_STREAM, \
STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH2_DMA_STREAM, \
STM32_DAC2_CH2_DMA_CHN)
#define CHANNEL_DATA_OFFSET 12U
@ -87,13 +87,13 @@ static const dacparams_t dma1_ch1_params = {
dataoffset: 0U,
regshift: 0U,
regmask: 0xFFFF0000U,
dma: STM32_DMA_STREAM(STM32_DAC1_CH1_DMA_STREAM),
dma: STM32_DMA_STREAM(STM32_DAC_DAC1_CH1_DMA_STREAM),
dmamode: STM32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC1_CH1_DMA_PRIORITY) |
STM32_DMA_CR_PL(STM32_DAC_DAC1_CH1_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
dmairqprio: STM32_DAC1_CH1_IRQ_PRIORITY
dmairqprio: STM32_DAC_DAC1_CH1_IRQ_PRIORITY
};
#endif
@ -103,13 +103,13 @@ static const dacparams_t dma1_ch2_params = {
dataoffset: CHANNEL_DATA_OFFSET,
regshift: 16U,
regmask: 0x0000FFFFU,
dma: STM32_DMA_STREAM(STM32_DAC1_CH2_DMA_STREAM),
dma: STM32_DMA_STREAM(STM32_DAC_DAC1_CH2_DMA_STREAM),
dmamode: STM32_DMA_CR_CHSEL(DAC1_CH2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC1_CH2_DMA_PRIORITY) |
STM32_DMA_CR_PL(STM32_DAC_DAC1_CH2_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
dmairqprio: STM32_DAC1_CH2_IRQ_PRIORITY
dmairqprio: STM32_DAC_DAC1_CH2_IRQ_PRIORITY
};
#endif
@ -119,13 +119,13 @@ static const dacparams_t dma2_ch1_params = {
dataoffset: 0U,
regshift: 0U,
regmask: 0xFFFF0000U,
dma: STM32_DMA_STREAM(STM32_DAC2_CH1_DMA_STREAM),
dma: STM32_DMA_STREAM(STM32_DAC_DAC2_CH1_DMA_STREAM),
dmamode: STM32_DMA_CR_CHSEL(DAC2_CH1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC2_CH1_DMA_PRIORITY) |
STM32_DMA_CR_PL(STM32_DAC_DAC2_CH1_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
dmairqprio: STM32_DAC2_CH1_IRQ_PRIORITY
dmairqprio: STM32_DAC_DAC2_CH1_IRQ_PRIORITY
};
#endif
@ -135,13 +135,13 @@ static const dacparams_t dma1_ch2_params = {
dataoffset: CHANNEL_DATA_OFFSET,
regshift: 16U,
regmask: 0x0000FFFFU,
dma: STM32_DMA_STREAM(STM32_DAC2_CH2_DMA_STREAM),
dma: STM32_DMA_STREAM(STM32_DAC_DAC2_CH2_DMA_STREAM),
dmamode: STM32_DMA_CR_CHSEL(DAC2_CH2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC2_CH2_DMA_PRIORITY) |
STM32_DMA_CR_PL(STM32_DAC_DAC2_CH2_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
dmairqprio: STM32_DAC2_CH2_IRQ_PRIORITY
dmairqprio: STM32_DAC_DAC2_CH2_IRQ_PRIORITY
};
#endif
@ -315,7 +315,9 @@ void dac_lld_put_channel(DACDriver *dacp,
switch (dacp->config->datamode) {
case DAC_DHRM_12BIT_RIGHT:
#if STM32_DAC_DUAL_MODE
case DAC_DHRM_12BIT_RIGHT_DUAL:
#endif
if (channel == 0U) {
dacp->params->dac->DHR12R1 = (uint32_t)sample;
}
@ -324,7 +326,9 @@ void dac_lld_put_channel(DACDriver *dacp,
}
break;
case DAC_DHRM_12BIT_LEFT:
#if STM32_DAC_DUAL_MODE
case DAC_DHRM_12BIT_LEFT_DUAL:
#endif
if (channel == 0U) {
dacp->params->dac->DHR12L1 = (uint32_t)sample;
}
@ -333,7 +337,9 @@ void dac_lld_put_channel(DACDriver *dacp,
}
break;
case DAC_DHRM_8BIT_RIGHT:
#if STM32_DAC_DUAL_MODE
case DAC_DHRM_8BIT_RIGHT_DUAL:
#endif
if (channel == 0U) {
dacp->params->dac->DHR8R1 = (uint32_t)sample;
}

48
os/hal/ports/STM32/LLD/DACv1/dac_lld.h
View File

@ -98,57 +98,57 @@
/**
* @brief DAC1 CH1 interrupt priority level setting.
*/
#if !defined(STM32_DAC1_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC1_CH1_IRQ_PRIORITY 10
#if !defined(STM32_DAC_DAC1_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#endif
/**
* @brief DAC1 CH2 interrupt priority level setting.
*/
#if !defined(STM32_DAC1_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC1_CH2_IRQ_PRIORITY 10
#if !defined(STM32_DAC_DAC1_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#endif
/**
* @brief DAC2 CH1 interrupt priority level setting.
*/
#if !defined(STM32_DAC2_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC2_CH1_IRQ_PRIORITY 10
#if !defined(STM32_DAC_DAC2_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC2_CH1_IRQ_PRIORITY 10
#endif
/**
* @brief DAC2 CH2 interrupt priority level setting.
*/
#if !defined(STM32_DAC2_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC2_CH2_IRQ_PRIORITY 10
#if !defined(STM32_DAC_DAC2_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC2_CH2_IRQ_PRIORITY 10
#endif
/**
* @brief DAC1 CH1 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_DAC1_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC1_CH1_DMA_PRIORITY 2
#if !defined(STM32_DAC_DAC1_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#endif
/**
* @brief DAC1 CH2 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_DAC1_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC1_CH2_DMA_PRIORITY 2
#if !defined(STM32_DAC_DAC1_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#endif
/**
* @brief DAC2 CH1 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_DAC2_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC2_CH1_DMA_PRIORITY 2
#if !defined(STM32_DAC_DAC2_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC2_CH1_DMA_PRIORITY 2
#endif
/**
* @brief DAC2 CH2 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_DAC2_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC2_CH2_DMA_PRIORITY 2
#if !defined(STM32_DAC_DAC2_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC2_CH2_DMA_PRIORITY 2
#endif
/*===========================================================================*/
@ -184,40 +184,40 @@
reassign streams to different channels.*/
#if STM32_ADVANCED_DMA
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if STM32_DAC_USE_DAC1_CH1 && !defined(STM32_DAC1_CH1_DMA_STREAM)
#if STM32_DAC_USE_DAC1_CH1 && !defined(STM32_DAC_DAC1_CH1_DMA_STREAM)
#error "DAC1 CH1 DMA stream not defined"
#endif
#if STM32_DAC_USE_DAC1_CH2 && !defined(STM32_DAC1_CH2_DMA_STREAM)
#if STM32_DAC_USE_DAC1_CH2 && !defined(STM32_DAC_DAC1_CH2_DMA_STREAM)
#error "DAC1 CH2 DMA stream not defined"
#endif
#if STM32_DAC_USE_DAC2_CH1 && !defined(STM32_DAC2_CH1_DMA_STREAM)
#if STM32_DAC_USE_DAC2_CH1 && !defined(STM32_DAC_DAC2_CH1_DMA_STREAM)
#error "DAC2 CH1 DMA stream not defined"
#endif
#if STM32_DAC_USE_DAC2_CH2 && !defined(STM32_DAC2_CH2_DMA_STREAM)
#if STM32_DAC_USE_DAC2_CH2 && !defined(STM32_DAC_DAC2_CH2_DMA_STREAM)
#error "DAC2 CH2 DMA stream not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/
#if STM32_DAC_USE_DAC1_CH1 && \
!STM32_DMA_IS_VALID_ID(STM32_DAC1_CH1_DMA_STREAM, STM32_DAC1_CH1_DMA_MSK)
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC1_CH1_DMA_STREAM, STM32_DAC1_CH1_DMA_MSK)
#error "invalid DMA stream associated to DAC1 CH1"
#endif
#if STM32_DAC_USE_DAC1_CH2 && \
!STM32_DMA_IS_VALID_ID(STM32_DAC1_CH2_DMA_STREAM, STM32_DAC1_CH2_DMA_MSK)
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC1_CH2_DMA_STREAM, STM32_DAC1_CH2_DMA_MSK)
#error "invalid DMA stream associated to DAC1 CH2"
#endif
#if STM32_DAC_USE_DAC2_CH1 && \
!STM32_DMA_IS_VALID_ID(STM32_DAC2_CH1_DMA_STREAM, STM32_DAC2_CH1_DMA_MSK)
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC2_CH1_DMA_STREAM, STM32_DAC2_CH1_DMA_MSK)
#error "invalid DMA stream associated to DAC2 CH1"
#endif
#if STM32_DAC_USE_DAC2_CH2 && \
!STM32_DMA_IS_VALID_ID(STM32_DAC2_CH2_DMA_STREAM, STM32_DAC2_CH2_DMA_MSK)
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC2_CH2_DMA_STREAM, STM32_DAC2_CH2_DMA_MSK)
#error "invalid DMA stream associated to DAC2 CH2"
#endif
#endif /* STM32_ADVANCED_DMA */

12
testhal/STM32/STM32F4xx/DAC/mcuconf.h
View File

@ -96,12 +96,12 @@
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 TRUE
#define STM32_DAC_USE_DAC1_CH2 TRUE
#define STM32_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
/*
* EXT driver system settings.

12
testhal/STM32/STM32F4xx/DAC_DUAL/mcuconf.h
View File

@ -96,12 +96,12 @@
#define STM32_DAC_DUAL_MODE TRUE
#define STM32_DAC_USE_DAC1_CH1 TRUE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
/*
* EXT driver system settings.