Renamed some DAC identifiers for consistency.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7947 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -36,19 +36,19 @@
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#endif
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#define DAC1_CH1_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_DAC1_CH1_DMA_STREAM, \
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STM32_DMA_GETCHANNEL(STM32_DAC_DAC1_CH1_DMA_STREAM, \
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STM32_DAC1_CH1_DMA_CHN)
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#define DAC1_CH2_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_DAC1_CH2_DMA_STREAM, \
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STM32_DMA_GETCHANNEL(STM32_DAC_DAC1_CH2_DMA_STREAM, \
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STM32_DAC1_CH2_DMA_CHN)
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#define DAC2_CH1_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_DAC2_CH1_DMA_STREAM, \
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STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH1_DMA_STREAM, \
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STM32_DAC2_CH1_DMA_CHN)
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#define DAC2_CH2_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_DAC2_CH2_DMA_STREAM, \
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STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH2_DMA_STREAM, \
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STM32_DAC2_CH2_DMA_CHN)
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#define CHANNEL_DATA_OFFSET 12U
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@ -87,13 +87,13 @@ static const dacparams_t dma1_ch1_params = {
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dataoffset: 0U,
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regshift: 0U,
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regmask: 0xFFFF0000U,
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dma: STM32_DMA_STREAM(STM32_DAC1_CH1_DMA_STREAM),
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dma: STM32_DMA_STREAM(STM32_DAC_DAC1_CH1_DMA_STREAM),
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dmamode: STM32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC1_CH1_DMA_PRIORITY) |
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STM32_DMA_CR_PL(STM32_DAC_DAC1_CH1_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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dmairqprio: STM32_DAC1_CH1_IRQ_PRIORITY
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dmairqprio: STM32_DAC_DAC1_CH1_IRQ_PRIORITY
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};
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#endif
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@ -103,13 +103,13 @@ static const dacparams_t dma1_ch2_params = {
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dataoffset: CHANNEL_DATA_OFFSET,
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regshift: 16U,
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regmask: 0x0000FFFFU,
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dma: STM32_DMA_STREAM(STM32_DAC1_CH2_DMA_STREAM),
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dma: STM32_DMA_STREAM(STM32_DAC_DAC1_CH2_DMA_STREAM),
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dmamode: STM32_DMA_CR_CHSEL(DAC1_CH2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC1_CH2_DMA_PRIORITY) |
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STM32_DMA_CR_PL(STM32_DAC_DAC1_CH2_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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dmairqprio: STM32_DAC1_CH2_IRQ_PRIORITY
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dmairqprio: STM32_DAC_DAC1_CH2_IRQ_PRIORITY
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};
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#endif
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@ -119,13 +119,13 @@ static const dacparams_t dma2_ch1_params = {
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dataoffset: 0U,
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regshift: 0U,
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regmask: 0xFFFF0000U,
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dma: STM32_DMA_STREAM(STM32_DAC2_CH1_DMA_STREAM),
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dma: STM32_DMA_STREAM(STM32_DAC_DAC2_CH1_DMA_STREAM),
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dmamode: STM32_DMA_CR_CHSEL(DAC2_CH1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC2_CH1_DMA_PRIORITY) |
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STM32_DMA_CR_PL(STM32_DAC_DAC2_CH1_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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dmairqprio: STM32_DAC2_CH1_IRQ_PRIORITY
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dmairqprio: STM32_DAC_DAC2_CH1_IRQ_PRIORITY
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};
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#endif
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@ -135,13 +135,13 @@ static const dacparams_t dma1_ch2_params = {
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dataoffset: CHANNEL_DATA_OFFSET,
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regshift: 16U,
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regmask: 0x0000FFFFU,
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dma: STM32_DMA_STREAM(STM32_DAC2_CH2_DMA_STREAM),
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dma: STM32_DMA_STREAM(STM32_DAC_DAC2_CH2_DMA_STREAM),
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dmamode: STM32_DMA_CR_CHSEL(DAC2_CH2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC2_CH2_DMA_PRIORITY) |
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STM32_DMA_CR_PL(STM32_DAC_DAC2_CH2_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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dmairqprio: STM32_DAC2_CH2_IRQ_PRIORITY
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dmairqprio: STM32_DAC_DAC2_CH2_IRQ_PRIORITY
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};
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#endif
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@ -315,7 +315,9 @@ void dac_lld_put_channel(DACDriver *dacp,
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switch (dacp->config->datamode) {
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case DAC_DHRM_12BIT_RIGHT:
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#if STM32_DAC_DUAL_MODE
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case DAC_DHRM_12BIT_RIGHT_DUAL:
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#endif
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if (channel == 0U) {
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dacp->params->dac->DHR12R1 = (uint32_t)sample;
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}
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@ -324,7 +326,9 @@ void dac_lld_put_channel(DACDriver *dacp,
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}
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break;
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case DAC_DHRM_12BIT_LEFT:
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#if STM32_DAC_DUAL_MODE
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case DAC_DHRM_12BIT_LEFT_DUAL:
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#endif
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if (channel == 0U) {
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dacp->params->dac->DHR12L1 = (uint32_t)sample;
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}
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@ -333,7 +337,9 @@ void dac_lld_put_channel(DACDriver *dacp,
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}
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break;
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case DAC_DHRM_8BIT_RIGHT:
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#if STM32_DAC_DUAL_MODE
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case DAC_DHRM_8BIT_RIGHT_DUAL:
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#endif
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if (channel == 0U) {
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dacp->params->dac->DHR8R1 = (uint32_t)sample;
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}
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@ -98,57 +98,57 @@
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/**
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* @brief DAC1 CH1 interrupt priority level setting.
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*/
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#if !defined(STM32_DAC1_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC1_CH1_IRQ_PRIORITY 10
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#if !defined(STM32_DAC_DAC1_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
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#endif
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/**
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* @brief DAC1 CH2 interrupt priority level setting.
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*/
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#if !defined(STM32_DAC1_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC1_CH2_IRQ_PRIORITY 10
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#if !defined(STM32_DAC_DAC1_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
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#endif
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/**
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* @brief DAC2 CH1 interrupt priority level setting.
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*/
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#if !defined(STM32_DAC2_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC2_CH1_IRQ_PRIORITY 10
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#if !defined(STM32_DAC_DAC2_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC_DAC2_CH1_IRQ_PRIORITY 10
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#endif
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/**
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* @brief DAC2 CH2 interrupt priority level setting.
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*/
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#if !defined(STM32_DAC2_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC2_CH2_IRQ_PRIORITY 10
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#if !defined(STM32_DAC_DAC2_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC_DAC2_CH2_IRQ_PRIORITY 10
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#endif
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/**
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* @brief DAC1 CH1 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_DAC1_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC1_CH1_DMA_PRIORITY 2
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#if !defined(STM32_DAC_DAC1_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
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#endif
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/**
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* @brief DAC1 CH2 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_DAC1_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC1_CH2_DMA_PRIORITY 2
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#if !defined(STM32_DAC_DAC1_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
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#endif
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/**
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* @brief DAC2 CH1 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_DAC2_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC2_CH1_DMA_PRIORITY 2
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#if !defined(STM32_DAC_DAC2_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC_DAC2_CH1_DMA_PRIORITY 2
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#endif
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/**
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* @brief DAC2 CH2 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_DAC2_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC2_CH2_DMA_PRIORITY 2
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#if !defined(STM32_DAC_DAC2_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC_DAC2_CH2_DMA_PRIORITY 2
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#endif
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/*===========================================================================*/
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@ -184,40 +184,40 @@
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reassign streams to different channels.*/
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#if STM32_ADVANCED_DMA
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/* Check on the presence of the DMA streams settings in mcuconf.h.*/
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#if STM32_DAC_USE_DAC1_CH1 && !defined(STM32_DAC1_CH1_DMA_STREAM)
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#if STM32_DAC_USE_DAC1_CH1 && !defined(STM32_DAC_DAC1_CH1_DMA_STREAM)
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#error "DAC1 CH1 DMA stream not defined"
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#endif
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#if STM32_DAC_USE_DAC1_CH2 && !defined(STM32_DAC1_CH2_DMA_STREAM)
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#if STM32_DAC_USE_DAC1_CH2 && !defined(STM32_DAC_DAC1_CH2_DMA_STREAM)
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#error "DAC1 CH2 DMA stream not defined"
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#endif
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#if STM32_DAC_USE_DAC2_CH1 && !defined(STM32_DAC2_CH1_DMA_STREAM)
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#if STM32_DAC_USE_DAC2_CH1 && !defined(STM32_DAC_DAC2_CH1_DMA_STREAM)
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#error "DAC2 CH1 DMA stream not defined"
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#endif
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#if STM32_DAC_USE_DAC2_CH2 && !defined(STM32_DAC2_CH2_DMA_STREAM)
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#if STM32_DAC_USE_DAC2_CH2 && !defined(STM32_DAC_DAC2_CH2_DMA_STREAM)
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#error "DAC2 CH2 DMA stream not defined"
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#endif
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/* Check on the validity of the assigned DMA channels.*/
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#if STM32_DAC_USE_DAC1_CH1 && \
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!STM32_DMA_IS_VALID_ID(STM32_DAC1_CH1_DMA_STREAM, STM32_DAC1_CH1_DMA_MSK)
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!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC1_CH1_DMA_STREAM, STM32_DAC1_CH1_DMA_MSK)
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#error "invalid DMA stream associated to DAC1 CH1"
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#endif
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#if STM32_DAC_USE_DAC1_CH2 && \
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!STM32_DMA_IS_VALID_ID(STM32_DAC1_CH2_DMA_STREAM, STM32_DAC1_CH2_DMA_MSK)
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!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC1_CH2_DMA_STREAM, STM32_DAC1_CH2_DMA_MSK)
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#error "invalid DMA stream associated to DAC1 CH2"
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#endif
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#if STM32_DAC_USE_DAC2_CH1 && \
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!STM32_DMA_IS_VALID_ID(STM32_DAC2_CH1_DMA_STREAM, STM32_DAC2_CH1_DMA_MSK)
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!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC2_CH1_DMA_STREAM, STM32_DAC2_CH1_DMA_MSK)
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#error "invalid DMA stream associated to DAC2 CH1"
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#endif
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#if STM32_DAC_USE_DAC2_CH2 && \
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!STM32_DMA_IS_VALID_ID(STM32_DAC2_CH2_DMA_STREAM, STM32_DAC2_CH2_DMA_MSK)
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!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC2_CH2_DMA_STREAM, STM32_DAC2_CH2_DMA_MSK)
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#error "invalid DMA stream associated to DAC2 CH2"
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#endif
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#endif /* STM32_ADVANCED_DMA */
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@ -96,12 +96,12 @@
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#define STM32_DAC_DUAL_MODE FALSE
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#define STM32_DAC_USE_DAC1_CH1 TRUE
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#define STM32_DAC_USE_DAC1_CH2 TRUE
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#define STM32_DAC1_CH1_IRQ_PRIORITY 10
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#define STM32_DAC1_CH2_IRQ_PRIORITY 10
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#define STM32_DAC1_CH1_DMA_PRIORITY 2
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#define STM32_DAC1_CH2_DMA_PRIORITY 2
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#define STM32_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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/*
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* EXT driver system settings.
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@ -96,12 +96,12 @@
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#define STM32_DAC_DUAL_MODE TRUE
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#define STM32_DAC_USE_DAC1_CH1 TRUE
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#define STM32_DAC_USE_DAC1_CH2 FALSE
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#define STM32_DAC1_CH1_IRQ_PRIORITY 10
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#define STM32_DAC1_CH2_IRQ_PRIORITY 10
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#define STM32_DAC1_CH1_DMA_PRIORITY 2
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#define STM32_DAC1_CH2_DMA_PRIORITY 2
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#define STM32_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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/*
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* EXT driver system settings.
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