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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5817 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2013-06-06 14:11:29 +00:00
parent 22445d8fd2
commit f85a97a786
4 changed files with 35 additions and 5 deletions
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2
boards/ST_EVB_SPC564A/board.h
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@ -18,7 +18,7 @@
#define _BOARD_H_ #define _BOARD_H_
/* /*
* Setup for a generic SPC563Mxx proto board. * Setup for a generic SPC564Axx proto board.
*/ */
/* /*

16
os/hal/platforms/SPC564Axx/hal_lld.c
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@ -60,6 +60,7 @@ void hal_lld_init(void) {
/* The DMA priority is placed above the CPU priority in order to not /* The DMA priority is placed above the CPU priority in order to not
starve I/O activities while the CPU is executing tight loops (FLASH starve I/O activities while the CPU is executing tight loops (FLASH
and SRAM slave ports only).*/ and SRAM slave ports only).*/
#if !defined(_SPC564A70_)
XBAR.MPR0.R = 0x34000021; /* Flash slave port priorities: XBAR.MPR0.R = 0x34000021; /* Flash slave port priorities:
eDMA (4): 0 (highest) eDMA (4): 0 (highest)
Core Instructions (0): 1 Core Instructions (0): 1
@ -72,6 +73,18 @@ void hal_lld_init(void) {
Core Data (1): 2 Core Data (1): 2
EBI (7): 3 EBI (7): 3
FlexRay (6): 4 */ FlexRay (6): 4 */
#else /* defined(_SPC564A70_) */
XBAR.MPR0.R = 0x03000021; /* Flash slave port priorities:
eDMA (4): 0 (highest)
Core Instructions (0): 1
Core Data (1): 2
Flexray (6): 3 */
XBAR.MPR2.R = 0x03000021; /* SRAM slave port priorities:
eDMA (4): 0 (highest)
Core Instructions (0): 1
Core Data (1): 2
FlexRay (6): 3 */
#endif /* defined(_SPC564A70_) */
/* Decrementer timer initialized for system tick use, note, it is /* Decrementer timer initialized for system tick use, note, it is
initialized here because in the OSAL layer the system clock frequency initialized here because in the OSAL layer the system clock frequency
@ -109,8 +122,11 @@ void spc_clock_init(void) {
ECSM.MUDCR.R = SPC5_RAM_WS; ECSM.MUDCR.R = SPC5_RAM_WS;
FLASH_A.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS; FLASH_A.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
FLASH_A.BIUCR2.R = 0; FLASH_A.BIUCR2.R = 0;
#if !defined(_SPC564A70_)
/* The second controller is only present in Andorra 3M or 4M.*/
FLASH_B.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS; FLASH_B.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
FLASH_B.BIUCR2.R = 0; FLASH_B.BIUCR2.R = 0;
#endif /* !defined(_SPC564A70_) */
#if !SPC5_NO_INIT #if !SPC5_NO_INIT
/* PLL activation.*/ /* PLL activation.*/

20
os/hal/platforms/SPC564Axx/spc564a_registry.h
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@ -22,8 +22,22 @@
* @{ * @{
*/ */
#ifndef _SPC563M_REGISTRY_H_ #ifndef _SPC564A_REGISTRY_H_
#define _SPC563M_REGISTRY_H_ #define _SPC564A_REGISTRY_H_
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if defined(_SPC564A70B4_) || defined(_SPC564A70L7_)
#define _SPC564A70_
#elif defined(_SPC564A74B4_) || defined(_SPC564A74L7_)
#define _SPC564A74_
#elif defined(_SPC564A80B4_) || defined(_SPC564A80L7_)
#define _SPC564A80_
#else
#error "SPC564Axx platform not defined"
#endif
/*===========================================================================*/ /*===========================================================================*/
/* Platform capabilities. */ /* Platform capabilities. */
@ -152,6 +166,6 @@
#define SPC5_EMIOS_DISABLE_CLOCK() #define SPC5_EMIOS_DISABLE_CLOCK()
/** @} */ /** @} */
#endif /* _SPC563M_REGISTRY_H_ */ #endif /* _SPC564A_REGISTRY_H_ */
/** @} */ /** @} */

2
testhal/SPC564Axx/SPI/Makefile
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@ -147,7 +147,7 @@ DLIBS =
# #
# List all user C define here, like -D_DEBUG=1 # List all user C define here, like -D_DEBUG=1
UDEFS = UDEFS = -D_SPC564A70L7_
# Define ASM defines here # Define ASM defines here
UADEFS = UADEFS =