diff --git a/os/common/ext/Artery/AT32F4xx/at32f435xx.h b/os/common/ext/Artery/AT32F4xx/at32f435xx.h index 521cbd313..3a6c1cc72 100644 --- a/os/common/ext/Artery/AT32F4xx/at32f435xx.h +++ b/os/common/ext/Artery/AT32F4xx/at32f435xx.h @@ -11442,104 +11442,13 @@ typedef struct #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk #define RCC_SSCGR_SSCGEN_Pos (31U) #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */ -#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk - -/******************** Bit definition for RCC_PLLI2SCFGR register ************/ -#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U) -#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */ -#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk -#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */ -#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */ -#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */ -#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */ -#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */ -#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */ -#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */ -#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */ -#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */ - -#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U) -#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */ -#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk -#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */ -#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */ -#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */ -#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */ -#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U) -#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */ -#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk -#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */ -#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */ -#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for RCC_PLLSAICFGR register ************/ -#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U) -#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */ -#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk -#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */ -#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */ -#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */ -#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */ -#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */ -#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */ -#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */ -#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */ -#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */ - - -#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U) -#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */ -#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk -#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */ -#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */ -#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */ -#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */ - -#define RCC_PLLSAICFGR_PLLSAIR_Pos (28U) -#define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */ -#define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk -#define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */ -#define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */ -#define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for RCC_DCKCFGR register ***************/ -#define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U) -#define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */ -#define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk -#define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */ -#define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */ -#define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */ -#define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */ -#define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */ - -#define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U) -#define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */ -#define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk -#define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */ -#define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */ -#define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */ -#define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */ -#define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */ -#define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U) -#define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */ -#define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk -#define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */ -#define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */ - -#define RCC_DCKCFGR_SAI1ASRC_Pos (20U) -#define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */ -#define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk -#define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */ -#define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */ -#define RCC_DCKCFGR_SAI1BSRC_Pos (22U) -#define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */ -#define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk -#define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */ -#define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */ -#define RCC_DCKCFGR_TIMPRE_Pos (24U) -#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */ -#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk +#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk +/******************** Bit definition for RCC_MISC2 register *****************/ +#define RCC_MISC2_AUTO_STEP_EN_Pos (4U) +#define RCC_MISC2_AUTO_STEP_EN_Msk (0x3U << RCC_MISC2_AUTO_STEP_EN_Pos) +#define RCC_MISC2_AUTO_STEP_EN RCC_MISC2_AUTO_STEP_EN_Msk +#define RCC_MISC2_AUTO_STEP_DIS (0x0) /******************************************************************************/ /* */ @@ -17019,8 +16928,6 @@ typedef struct * @brief Specific devices reset values definitions */ #define RCC_PLLCFGR_RST_VALUE 0x24003010U -#define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U -#define RCC_PLLSAICFGR_RST_VALUE 0x24003000U #define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/ #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */ diff --git a/os/hal/ports/AT32/AT32F4xx/hal_lld.c b/os/hal/ports/AT32/AT32F4xx/hal_lld.c index 840bd913c..b7dcc4a24 100644 --- a/os/hal/ports/AT32/AT32F4xx/hal_lld.c +++ b/os/hal/ports/AT32/AT32F4xx/hal_lld.c @@ -210,101 +210,35 @@ void stm32_clock_init(void) { RCC->PLLCFGR = STM32_PLLSRC | STM32_PLLP | STM32_PLLN | STM32_PLLM; RCC->CR |= RCC_CR_PLLON; -/* Artery */ -#if 0 - /* Synchronization with voltage regulator stabilization.*/ -#if defined(STM32F4XX) - while ((PWR->CSR & PWR_CSR_VOSRDY) == 0) - ; /* Waits until power regulator is stable. */ - -#if STM32_OVERDRIVE_REQUIRED - /* Overdrive activation performed after activating the PLL in order to save - time as recommended in RM in "Entering Over-drive mode" paragraph.*/ - PWR->CR |= PWR_CR_ODEN; - while (!(PWR->CSR & PWR_CSR_ODRDY)) - ; - PWR->CR |= PWR_CR_ODSWEN; - while (!(PWR->CSR & PWR_CSR_ODSWRDY)) - ; -#endif /* STM32_OVERDRIVE_REQUIRED */ -#endif /* defined(STM32F4XX) */ -#endif - /* Waiting for PLL lock.*/ while (!(RCC->CR & RCC_CR_PLLRDY)) ; #endif /* STM32_ACTIVATE_PLL */ /* Other clock-related settings (dividers, MCO etc).*/ -#if !defined(STM32F413xx) - RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL | - STM32_I2SSRC | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | + RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | + STM32_MCO1PRE | STM32_MCO1SEL | + STM32_RTCPRE | + STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; -#else - RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL | - STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | - STM32_HPRE; -#endif - -#if STM32_HAS_RCC_DCKCFGR - /* DCKCFGR register initialization, note, must take care of the _OFF - pseudo settings.*/ - { - uint32_t dckcfgr = 0; -#if STM32_SAI2SEL != STM32_SAI2SEL_OFF - dckcfgr |= STM32_SAI2SEL; -#endif -#if STM32_SAI1SEL != STM32_SAI1SEL_OFF - dckcfgr |= STM32_SAI1SEL; -#endif -#if (STM32_ACTIVATE_PLLSAI == TRUE) && \ - (STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF) - dckcfgr |= STM32_PLLSAIDIVR; -#endif -#if defined(STM32F469xx) || defined(STM32F479xx) - /* Special case, in those devices STM32_CK48MSEL is located in the - DCKCFGR register.*/ - dckcfgr |= STM32_CK48MSEL; -#endif -#if !defined(STM32F413xx) - RCC->DCKCFGR = dckcfgr | - STM32_TIMPRE | STM32_PLLSAIDIVQ | STM32_PLLI2SDIVQ; -#else - RCC->DCKCFGR = dckcfgr | - STM32_TIMPRE | STM32_PLLDIVR | STM32_PLLI2SDIVR; -#endif - } -#endif - -#if STM32_HAS_RCC_DCKCFGR2 - /* DCKCFGR2 register initialization.*/ - RCC->DCKCFGR2 = STM32_CK48MSEL; -#endif #if 0 /* Flash setup.*/ -#if !defined(STM32_REMOVE_REVISION_A_FIX) - /* Some old revisions of F4x MCUs randomly crashes with compiler - optimizations enabled AND flash caches enabled. */ - if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241)) - FLASH->ACR = FLASH_ACR_PRFTEN | STM32_FLASHBITS; - else - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | - FLASH_ACR_DCEN | STM32_FLASHBITS; -#else - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | - FLASH_ACR_DCEN | STM32_FLASHBITS; -#endif - while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != - (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) { - } #endif /* Switching to the configured clock source if it is different from HSI.*/ #if (STM32_SW != STM32_SW_HSI) + + /* enable auto step mode */ + RCC->MISC2 |= RCC_MISC2_AUTO_STEP_EN; + RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) ; + + /* disable auto step mode */ + RCC->MISC2 &= ~RCC_MISC2_AUTO_STEP_EN; + #endif #endif /* STM32_NO_INIT */ diff --git a/os/hal/ports/AT32/AT32F4xx/hal_lld.h b/os/hal/ports/AT32/AT32F4xx/hal_lld.h index fac6478de..b9ccaf2f4 100644 --- a/os/hal/ports/AT32/AT32F4xx/hal_lld.h +++ b/os/hal/ports/AT32/AT32F4xx/hal_lld.h @@ -237,31 +237,6 @@ #endif #endif /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */ -/** - * @brief Flash settings. - */ -#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__) -#define STM32_FLASHBITS 0x00000000 -#elif STM32_HCLK <= STM32_1WS_THRESHOLD -#define STM32_FLASHBITS 0x00000001 -#elif STM32_HCLK <= STM32_2WS_THRESHOLD -#define STM32_FLASHBITS 0x00000002 -#elif STM32_HCLK <= STM32_3WS_THRESHOLD -#define STM32_FLASHBITS 0x00000003 -#elif STM32_HCLK <= STM32_4WS_THRESHOLD -#define STM32_FLASHBITS 0x00000004 -#elif STM32_HCLK <= STM32_5WS_THRESHOLD -#define STM32_FLASHBITS 0x00000005 -#elif STM32_HCLK <= STM32_6WS_THRESHOLD -#define STM32_FLASHBITS 0x00000006 -#elif STM32_HCLK <= STM32_7WS_THRESHOLD -#define STM32_FLASHBITS 0x00000007 -#elif STM32_HCLK <= STM32_8WS_THRESHOLD -#define STM32_FLASHBITS 0x00000008 -#else -#error "invalid frequency at specified VDD level" -#endif - /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ diff --git a/os/hal/ports/AT32/AT32F4xx/hal_lld_type1.h b/os/hal/ports/AT32/AT32F4xx/hal_lld_type1.h index 907e945bc..245d56dee 100644 --- a/os/hal/ports/AT32/AT32F4xx/hal_lld_type1.h +++ b/os/hal/ports/AT32/AT32F4xx/hal_lld_type1.h @@ -139,30 +139,15 @@ */ #define STM32_PLLOUT_MIN 16000000 -/** - * @brief Maximum PLLI2S output clock frequency. - */ -#define STM32_PLLI2SOUT_MAX 216000000 - -/** - * @brief Maximum PLLSAI output clock frequency. - */ -#define STM32_PLLSAIOUT_MAX 216000000 - /** * @brief Maximum APB1 clock frequency. */ -#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX / 4) +#define STM32_PCLK1_MAX 144000000 /** * @brief Maximum APB2 clock frequency. */ -#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2) - -/** - * @brief Maximum SPI/I2S clock frequency. - */ -#define STM32_SPII2S_MAX 45000000 +#define STM32_PCLK2_MAX 144000000 #endif /** @} */ @@ -248,10 +233,6 @@ #define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */ #define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */ -#define STM32_I2SSRC_MASK (1 << 23) /**< I2CSRC mask. */ -#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */ -#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */ - #define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */ #define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */ #define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */ @@ -675,7 +656,7 @@ * @brief APB1 prescaler value. */ #if !defined(STM32_PPRE1) || defined(__DOXYGEN__) -#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE1 STM32_PPRE1_DIV2 #endif /**