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Refactor L4+ EFL sizing 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12920 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
cinsights 2019-07-20 13:35:48 +00:00
parent 81e586a948
commit f936eb20e3
2 changed files with 789 additions and 783 deletions
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42
os/hal/ports/STM32/STM32L4xx+/hal_efl_lld.c
View File

@ -65,12 +65,11 @@ static const flash_descriptor_t efl_lld_size1[STM32_FLASH_NUMBER_OF_BANKS] = {
FLASH_ATTR_ECC_CAPABLE | FLASH_ATTR_ECC_CAPABLE |
FLASH_ATTR_ECC_ZERO_LINE_CAPABLE, FLASH_ATTR_ECC_ZERO_LINE_CAPABLE,
.page_size = STM32_FLASH_LINE_SIZE, .page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH_SECTORS_PER_BANK, .sectors_count = STM32_FLASH_SECTORS_TOTAL_1M,
.sectors = NULL, .sectors = NULL,
.sectors_size = STM32_FLASH_SECTOR_SIZE, .sectors_size = STM32_FLASH_SECTOR_SIZE_1M,
.address = (uint8_t *)FLASH_BASE, .address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH_SECTORS_PER_BANK * .size = STM32_FLASH_SIZE_1M * STM32_FLASH_SIZE_SCALE
STM32_FLASH_SECTOR_SIZE
}, },
{ /* Bank 1 & 2 (DBM) organisation. */ { /* Bank 1 & 2 (DBM) organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE | .attributes = FLASH_ATTR_ERASED_IS_ONE |
@ -78,12 +77,11 @@ static const flash_descriptor_t efl_lld_size1[STM32_FLASH_NUMBER_OF_BANKS] = {
FLASH_ATTR_ECC_CAPABLE | FLASH_ATTR_ECC_CAPABLE |
FLASH_ATTR_ECC_ZERO_LINE_CAPABLE, FLASH_ATTR_ECC_ZERO_LINE_CAPABLE,
.page_size = STM32_FLASH_LINE_SIZE, .page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = 2 * STM32_FLASH_DUAL_SECTORS_PER_BANK, .sectors_count = STM32_FLASH_SECTORS_TOTAL_1M,
.sectors = NULL, .sectors = NULL,
.sectors_size = STM32_FLASH_DUAL_SECTOR_SIZE, .sectors_size = STM32_FLASH_DUAL_SECTOR_SIZE_1M,
.address = (uint8_t *)FLASH_BASE, .address = (uint8_t *)FLASH_BASE,
.size = 2 * STM32_FLASH_DUAL_SECTORS_PER_BANK * .size = STM32_FLASH_SIZE_1M * STM32_FLASH_SIZE_SCALE
STM32_FLASH_DUAL_SECTOR_SIZE
} }
}; };
@ -95,12 +93,11 @@ static const flash_descriptor_t efl_lld_size2[STM32_FLASH_NUMBER_OF_BANKS] = {
FLASH_ATTR_ECC_CAPABLE | FLASH_ATTR_ECC_CAPABLE |
FLASH_ATTR_ECC_ZERO_LINE_CAPABLE, FLASH_ATTR_ECC_ZERO_LINE_CAPABLE,
.page_size = STM32_FLASH_LINE_SIZE, .page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH_SECTORS_PER_BANK, .sectors_count = STM32_FLASH_SECTORS_TOTAL_2M,
.sectors = NULL, .sectors = NULL,
.sectors_size = STM32_FLASH_SECTOR_SIZE, .sectors_size = STM32_FLASH_SECTOR_SIZE_2M,
.address = (uint8_t *)FLASH_BASE, .address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH_SECTORS_PER_BANK * .size = STM32_FLASH_SIZE_2M * STM32_FLASH_SIZE_SCALE
STM32_FLASH_SECTOR_SIZE
}, },
{ /* Bank 1 & 2 (DBM) organisation. */ { /* Bank 1 & 2 (DBM) organisation. */
.attributes = FLASH_ATTR_ERASED_IS_ONE | .attributes = FLASH_ATTR_ERASED_IS_ONE |
@ -108,23 +105,20 @@ static const flash_descriptor_t efl_lld_size2[STM32_FLASH_NUMBER_OF_BANKS] = {
FLASH_ATTR_ECC_CAPABLE | FLASH_ATTR_ECC_CAPABLE |
FLASH_ATTR_ECC_ZERO_LINE_CAPABLE, FLASH_ATTR_ECC_ZERO_LINE_CAPABLE,
.page_size = STM32_FLASH_LINE_SIZE, .page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = 2 * STM32_FLASH_DUAL_SECTORS_PER_BANK, .sectors_count = STM32_FLASH_SECTORS_TOTAL_2M,
.sectors = NULL, .sectors = NULL,
.sectors_size = STM32_FLASH_DUAL_SECTOR_SIZE, .sectors_size = STM32_FLASH_DUAL_SECTOR_SIZE_2M,
.address = (uint8_t *)FLASH_BASE, .address = (uint8_t *)FLASH_BASE,
.size = 2 * STM32_FLASH_DUAL_SECTORS_PER_BANK * .size = STM32_FLASH_SIZE_2M * STM32_FLASH_SIZE_SCALE
STM32_FLASH_DUAL_SECTOR_SIZE
} }
}; };
/* Table describing possible flash sizes and descriptors for this device. */ /* Table describing possible flash sizes and descriptors for this device. */
static const efl_lld_size_t efl_lld_flash_sizes[] = { static const efl_lld_size_t efl_lld_flash_sizes[] = {
{ {
.kb_size = STM32_FLASH_SIZE_1M,
.desc = efl_lld_size1 .desc = efl_lld_size1
}, },
{ {
.kb_size = STM32_FLASH_SIZE_2M,
.desc = efl_lld_size2 .desc = efl_lld_size2
} }
}; };
@ -166,13 +160,13 @@ static inline void stm32_flash_wait_busy(EFlashDriver *eflp) {
} }
} }
static inline uint16_t stm32_flash_get_size(void) { static inline size_t stm32_flash_get_size(void) {
return *(uint16_t*)((uint32_t) STM32_FLASH_SIZE_REGISTER); return *(uint16_t*)((uint32_t) STM32_FLASH_SIZE_REGISTER) * STM32_FLASH_SIZE_SCALE;
} }
static inline bool stm32_flash_dual_bank(EFlashDriver *eflp) { static inline bool stm32_flash_dual_bank(EFlashDriver *eflp) {
#if STM32_FLASH_SECTORS_PER_BANK > 1 #if STM32_FLASH_NUMBER_OF_BANKS > 1
return ((eflp->flash->SR & (FLASH_OPTR_DBANK | FLASH_OPTR_DB1M)) != 0U); return ((eflp->flash->SR & (FLASH_OPTR_DBANK | FLASH_OPTR_DB1M)) != 0U);
#endif #endif
return false; return false;
@ -222,7 +216,7 @@ void efl_lld_init(void) {
/* Find the size of the flash and set descriptor reference. */ /* Find the size of the flash and set descriptor reference. */
uint8_t i; uint8_t i;
for (i = 0; i < (sizeof(efl_lld_flash_sizes) / sizeof(efl_lld_size_t)); i++) { for (i = 0; i < (sizeof(efl_lld_flash_sizes) / sizeof(efl_lld_size_t)); i++) {
if (efl_lld_flash_sizes[i].kb_size == stm32_flash_get_size()) { if (efl_lld_flash_sizes[i].desc->size == stm32_flash_get_size()) {
EFLD1.descriptor = efl_lld_flash_sizes[i].desc; EFLD1.descriptor = efl_lld_flash_sizes[i].desc;
if (stm32_flash_dual_bank(&EFLD1)) { if (stm32_flash_dual_bank(&EFLD1)) {
/* Point to the dual bank descriptor. */ /* Point to the dual bank descriptor. */
@ -329,8 +323,8 @@ flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
/** /**
* @brief Program operation. * @brief Program operation.
* @note The device supports ECC, it is only possible to write erased * @note The device supports ECC. It is only possible to write erased
* pages once except when writing all zeroes. * pages once except when writing all zeroes to a location.
* *
* @param[in] ip pointer to a @p EFlashDriver instance * @param[in] ip pointer to a @p EFlashDriver instance
* @param[in] offset offset within full flash address space * @param[in] offset offset within full flash address space

30
os/hal/ports/STM32/STM32L4xx+/hal_efl_lld.h
View File

@ -55,8 +55,12 @@
defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \
defined(__DOXYGEN__) defined(__DOXYGEN__)
/* Flash size register. */
#define STM32_FLASH_SIZE_REGISTER 0x1FFF75E0
#define STM32_FLASH_SIZE_SCALE 1024U
/* /*
* Flash size is: * Device flash size is:
* 1M for STM32L4+ suffix G devices * 1M for STM32L4+ suffix G devices
* 2M for STM32L4+ suffix I devices. * 2M for STM32L4+ suffix I devices.
* *
@ -69,16 +73,25 @@
#define STM32_FLASH_SIZE_1M 1024U #define STM32_FLASH_SIZE_1M 1024U
#define STM32_FLASH_SIZE_2M 2048U #define STM32_FLASH_SIZE_2M 2048U
#define STM32_FLASH_SECTORS_TOTAL_1M 128
#define STM32_FLASH_SECTORS_TOTAL_2M 256
/* Single bank mode bank 1.*/ /* Single bank mode bank 1 for 1M device.*/
#define STM32_FLASH_SECTOR_SIZE 8192U #define STM32_FLASH_SECTOR_SIZE_1M ((STM32_FLASH_SIZE_1M \
#define STM32_FLASH_SECTORS_PER_BANK 256 * STM32_FLASH_SIZE_SCALE) \
/ STM32_FLASH_SECTORS_TOTAL_1M)
/* Dual bank mode banks 1 & 2.*/ /* Dual bank mode banks 1 & 2 for 1M device.*/
#define STM32_FLASH_DUAL_SECTOR_SIZE 4096U #define STM32_FLASH_DUAL_SECTOR_SIZE_1M (STM32_FLASH_SECTOR_SIZE_1M / 2)
#define STM32_FLASH_DUAL_SECTORS_PER_BANK 128
/* Single bank mode bank 1 for 2M device.*/
#define STM32_FLASH_SECTOR_SIZE_2M ((STM32_FLASH_SIZE_2M \
* STM32_FLASH_SIZE_SCALE) \
/ STM32_FLASH_SECTORS_TOTAL_2M)
/* Dual bank mode banks 1 & 2 for 2M device.*/
#define STM32_FLASH_DUAL_SECTOR_SIZE_2M (STM32_FLASH_SECTOR_SIZE_2M / 2)
#define STM32_FLASH_SIZE_REGISTER 0x1FFF75E0
#else #else
#error "This EFL driver does not support the selected device" #error "This EFL driver does not support the selected device"
#endif #endif
@ -89,7 +102,6 @@
/* A flash size declaration. */ /* A flash size declaration. */
typedef struct { typedef struct {
uint16_t kb_size;
const flash_descriptor_t* desc; const flash_descriptor_t* desc;
} efl_lld_size_t; } efl_lld_size_t;