diff --git a/os/ex/ST/lps25h.c b/os/ex/ST/lps25h.c new file mode 100644 index 000000000..28c00816c --- /dev/null +++ b/os/ex/ST/lps25h.c @@ -0,0 +1,318 @@ +/* + ChibiOS - Copyright (C) 2016 Rocco Marco Guglielmi + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + +*/ + +/** + * @file lps25h.c + * @brief LPS25H MEMS interface module code. + * + * @addtogroup lps25h + * @{ + */ + +#include "hal.h" +#include "lps25h.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#if (LPS25H_USE_I2C) || defined(__DOXYGEN__) +/** + * @brief Reads registers value using I2C. + * @pre The I2C interface must be initialized and the driver started. + * + * @param[in] i2cp pointer to the I2C interface + * @param[in] sad slave address without R bit + * @param[in] reg first sub-register address + * @return the read value. + */ +uint8_t lps25hI2CReadRegister(I2CDriver *i2cp, lps25h_sad_t sad, uint8_t reg, + msg_t* msgp) { + msg_t msg; + uint8_t rxbuf; + msg = i2cMasterTransmitTimeout(i2cp, sad, ®, 1, &rxbuf, 1, + TIME_INFINITE); + if(msgp != NULL){ + *msgp = msg; + } + return rxbuf; +} + +/** + * @brief Writes a value into a register using I2C. + * @pre The I2C interface must be initialized and the driver started. + * + * @param[in] i2cp pointer to the I2C interface + * @param[in] sad slave address without R bit + * @param[in] sub sub-register address + * @param[in] value the value to be written + * @return the operation status. + */ +msg_t lps25hI2CWriteRegister(I2CDriver *i2cp, lps25h_sad_t sad, uint8_t reg, + uint8_t value) { + uint8_t txbuf[2]; + txbuf[0] = reg; + txbuf[1] = value; + return i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, NULL, 0, TIME_INFINITE); +} +#endif /* LPS25H_USE_I2C */ + +/* + * Interface implementation. + */ +static size_t get_axes_number(void *ip) { + + osalDbgCheck(ip != NULL); + return LPS25H_NUMBER_OF_AXES; +} + +static msg_t read_raw(void *ip, int32_t* axis) { + int32_t tmp; + msg_t msg = MSG_OK; + osalDbgCheck((ip != NULL) && (axis != NULL)); + osalDbgAssert((((LPS25HDriver *)ip)->state == LPS25H_READY), + "read_raw(), invalid state"); + +#if LPS25H_USE_I2C + osalDbgAssert((((LPS25HDriver *)ip)->config->i2cp->state == I2C_READY), + "read_raw(), channel not ready"); +#if LPS25H_SHARED_I2C + i2cAcquireBus(((LPS25HDriver *)ip)->config->i2cp); + i2cStart(((LPS25HDriver *)ip)->config->i2cp, + ((LPS25HDriver *)ip)->config->i2ccfg); +#endif /* LPS25H_SHARED_I2C */ + tmp = lps25hI2CReadRegister(((LPS25HDriver *)ip)->config->i2cp, + ((LPS25HDriver *)ip)->config->slaveaddress, + LPS25H_AD_PRESS_OUT_XL, NULL); + if (msg != MSG_OK) + return msg; + tmp += lps25hI2CReadRegister(((LPS25HDriver *)ip)->config->i2cp, + ((LPS25HDriver *)ip)->config->slaveaddress, + LPS25H_AD_PRESS_OUT_L, NULL) << 8; + if (msg != MSG_OK) + return msg; + tmp += lps25hI2CReadRegister(((LPS25HDriver *)ip)->config->i2cp, + ((LPS25HDriver *)ip)->config->slaveaddress, + LPS25H_AD_PRESS_OUT_H, NULL) << 16; + if (msg != MSG_OK) + return msg; + *axis = (int32_t)tmp; + + +#if LPS25H_SHARED_I2C + i2cReleaseBus(((LPS25HDriver *)ip)->config->i2cp); +#endif /* LPS25H_SHARED_I2C */ +#endif /* LPS25H_USE_I2C */ + return MSG_OK; +} + +static msg_t read_cooked(void *ip, float* axis) { + int32_t raw; + msg_t msg; + + osalDbgCheck((ip != NULL) && (axis != NULL)); + + osalDbgAssert((((LPS25HDriver *)ip)->state == LPS25H_READY), + "read_cooked(), invalid state"); + + msg = read_raw(ip, &raw); + + *axis = raw / ((LPS25HDriver *)ip)->sensitivity; + *axis -= ((LPS25HDriver *)ip)->bias; + return msg; +} + + +static msg_t set_bias(void *ip, int32_t *bp) { + osalDbgCheck((ip != NULL) && (bp != NULL)); + + osalDbgAssert((((LPS25HDriver *)ip)->state == LPS25H_READY) || + (((LPS25HDriver *)ip)->state == LPS25H_STOP), + "set_bias(), invalid state"); + + ((LPS25HDriver *)ip)->bias = *bp; + return MSG_OK; +} + +static msg_t reset_bias(void *ip) { + osalDbgCheck(ip != NULL); + + osalDbgAssert((((LPS25HDriver *)ip)->state == LPS25H_READY) || + (((LPS25HDriver *)ip)->state == LPS25H_STOP), + "reset_bias(), invalid state"); + + ((LPS25HDriver *)ip)->bias = 0; + return MSG_OK; +} + + +static msg_t set_sensivity(void *ip, float *sp) { + + osalDbgCheck((ip != NULL) && (sp !=NULL)); + + osalDbgAssert((((LPS25HDriver *)ip)->state == LPS25H_READY), + "set_sensivity(), invalid state"); + + ((LPS25HDriver *)ip)->sensitivity = *sp; + return MSG_OK; +} + +static msg_t reset_sensivity(void *ip) { + + osalDbgCheck(ip != NULL); + + osalDbgAssert((((LPS25HDriver *)ip)->state == LPS25H_READY), + "reset_sensivity(), invalid state"); + + ((LPS25HDriver *)ip)->sensitivity = LPS25H_SENS; + return MSG_OK; +} + +static const struct BaseSensorVMT vmt_basesensor = { + get_axes_number, read_raw, read_cooked +}; + +static const struct BaseBarometerVMT vmt_basebarometer = { + get_axes_number, read_raw, read_cooked, + set_bias, reset_bias, set_sensivity, reset_sensivity +}; + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes an instance. + * + * @param[out] devp pointer to the @p LPS25HDriver object + * + * @init + */ +void lps25hObjectInit(LPS25HDriver *devp) { + + devp->vmt_basesensor = &vmt_basesensor; + devp->vmt_basebarometer = &vmt_basebarometer; + devp->config = NULL; + devp->bias = 0; + devp->state = LPS25H_STOP; +} + +/** + * @brief Configures and activates LPS25H Complex Driver peripheral. + * + * @param[in] devp pointer to the @p LPS25HDriver object + * @param[in] config pointer to the @p LPS25HConfig object + * + * @api + */ +void lps25hStart(LPS25HDriver *devp, const LPS25HConfig *config) { + uint8_t cr; + osalDbgCheck((devp != NULL) && (config != NULL)); + + osalDbgAssert((devp->state == LPS25H_STOP) || (devp->state == LPS25H_READY), + "lps25hStart(), invalid state"); + + devp->config = config; + +#if LPS25H_USE_I2C +#if LPS25H_SHARED_I2C + i2cAcquireBus((devp)->config->i2cp); +#endif /* LPS25H_SHARED_I2C */ + i2cStart((devp)->config->i2cp, + (devp)->config->i2ccfg); + + /* Control register 1 configuration block.*/ + { + cr = devp->config->outputdatarate | LPS25H_CTRL_REG1_PD; +#if LPS25H_USE_ADVANCED || defined(__DOXYGEN__) + cr |= devp->config->blockdataupdate; + +#endif + lps25hI2CWriteRegister(devp->config->i2cp, devp->config->slaveaddress, + LPS25H_AD_CTRL_REG1, cr); + } + + /* Control register 1 configuration block.*/ + { + cr = 0x05; +#if LPS25H_USE_ADVANCED || defined(__DOXYGEN__) + cr = devp->config->respressure | devp->config->restemperature; + +#endif + lps25hI2CWriteRegister(devp->config->i2cp, devp->config->slaveaddress, + LPS25H_AD_RES_CONF, cr); + } + +#if LPS25H_SHARED_I2C + i2cReleaseBus((devp)->config->i2cp); +#endif /* LPS25H_SHARED_I2C */ +#endif /* LPS25H_USE_I2C */ + /* Storing sensitivity information according to full scale value */ + devp->sensitivity = LPS25H_SENS; + /* This is the Barometer transient recovery time */ + osalThreadSleepMilliseconds(5); + + devp->state = LPS25H_READY; +} + +/** + * @brief Deactivates the LPS25H Complex Driver peripheral. + * + * @param[in] devp pointer to the @p LPS25HDriver object + * + * @api + */ +void lps25hStop(LPS25HDriver *devp) { + + osalDbgCheck(devp != NULL); + + osalDbgAssert((devp->state == LPS25H_STOP) || (devp->state == LPS25H_READY), + "lps25hStop(), invalid state"); + +#if (LPS25H_USE_I2C) + if (devp->state == LPS25H_STOP) { +#if LPS25H_SHARED_I2C + i2cAcquireBus((devp)->config->i2cp); + i2cStart((devp)->config->i2cp, + (devp)->config->i2ccfg); +#endif /* LPS25H_SHARED_I2C */ + lps25hI2CWriteRegister(devp->config->i2cp, devp->config->slaveaddress, + LPS25H_AD_CTRL_REG1, 0); + i2cStop((devp)->config->i2cp); +#if LPS25H_SHARED_I2C + i2cReleaseBus((devp)->config->i2cp); +#endif /* LPS25H_SHARED_I2C */ + } +#endif /* LPS25H_USE_I2C */ + devp->state = LPS25H_STOP; +} +/** @} */ diff --git a/os/ex/ST/lps25h.h b/os/ex/ST/lps25h.h new file mode 100644 index 000000000..7cffb881d --- /dev/null +++ b/os/ex/ST/lps25h.h @@ -0,0 +1,456 @@ +/* + ChibiOS - Copyright (C) 2016 Rocco Marco Guglielmi + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + +*/ + +/** + * @file lps25h.h + * @brief LPS25H MEMS interface module header. + * + * @{ + */ +#ifndef _LPS25H_H_ +#define _LPS25H_H_ + +#include "hal_barometer.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Version identification + * @{ + */ +/** + * @brief LPS25H driver version string. + */ +#define EX_LPS25H_VERSION "1.0.0" + +/** + * @brief LPS25H driver version major number. + */ +#define EX_LPS25H_MAJOR 1 + +/** + * @brief LPS25H driver version minor number. + */ +#define EX_LPS25H_MINOR 0 + +/** + * @brief LPS25H driver version patch number. + */ +#define EX_LPS25H_PATCH 0 +/** @} */ + +/** + * @brief LPS25H characteristics. + * + * @{ + */ +#define LPS25H_NUMBER_OF_AXES 1U + +#define LPS25H_SENS 4096.0f /**< LSB/hPa */ +/** @} */ + +/** + * @name LPS25H communication interfaces related bit masks + * @{ + */ +#define LPS25H_DI_MASK 0xFF /**< Data In mask */ +#define LPS25H_DI(n) (1 << n) /**< Data In bit n */ +#define LPS25H_AD_MASK 0x3F /**< Address Data mask */ +#define LPS25H_AD(n) (1 << n) /**< Address Data bit n */ +#define LPS25H_MS (1 << 6) /**< Multiple read write */ +#define LPS25H_RW (1 << 7) /**< Read Write selector */ + +#define LPS25H_SUB_MS (1 << 7) /**< Multiple read write in I2C mode */ +/** @} */ + +/** + * @name LPS25H register addresses + * @{ + */ +#define LPS25H_AD_REF_P_XL 0x08 +#define LPS25H_AD_REF_P_L 0x09 +#define LPS25H_AD_REF_P_H 0x0A +#define LPS25H_AD_WHO_AM_I 0x0F +#define LPS25H_AD_RES_CONF 0x10 +#define LPS25H_AD_CTRL_REG1 0x20 +#define LPS25H_AD_CTRL_REG2 0x21 +#define LPS25H_AD_CTRL_REG3 0x22 +#define LPS25H_AD_CTRL_REG4 0x23 +#define LPS25H_AD_INT_CFG 0x24 +#define LPS25H_AD_INT_SRC 0x25 +#define LPS25H_AD_STATUS_REG 0x27 +#define LPS25H_AD_CTRL_REG5 0x24 +#define LPS25H_AD_REFERENCE 0x25 +#define LPS25H_AD_OUT_TEMP 0x26 +#define LPS25H_AD_PRESS_OUT_XL 0x28 +#define LPS25H_AD_PRESS_OUT_L 0x29 +#define LPS25H_AD_PRESS_OUT_H 0x2A +#define LPS25H_AD_TEMP_OUT_L 0x2B +#define LPS25H_AD_TEMP_OUT_H 0x2C +#define LPS25H_AD_FIFO_CTRL 0x2E +#define LPS25H_AD_FIFO_SRC 0x2F +#define LPS25H_AD_THS_P_L 0x30 +#define LPS25H_AD_THS_P_H 0x31 +#define LPS25H_AD_RPDS_L 0x39 +#define LPS25H_AD_RPDS_H 0x3A +/** @} */ + +/** + * @name LPS25H_CTRL_REG1 register bits definitions + * @{ + */ +#define LPS25H_CTRL_REG1_MASK 0xFF +#define LPS25H_CTRL_REG1_SIM (1 << 0) +#define LPS25H_CTRL_REG1_RESET_AZ (1 << 1) +#define LPS25H_CTRL_REG1_BDU (1 << 2) +#define LPS25H_CTRL_REG1_DIFF_EN (1 << 3) +#define LPS25H_CTRL_REG1_ODR0 (1 << 4) +#define LPS25H_CTRL_REG1_ODR1 (1 << 5) +#define LPS25H_CTRL_REG1_ODR2 (1 << 6) +#define LPS25H_CTRL_REG1_PD (1 << 7) +/** @} */ + +/** + * @name LPS25H_CTRL_REG2 register bits definitions + * @{ + */ +#define LPS25H_CTRL_REG2_MASK 0xF3 +#define LPS25H_CTRL_REG2_ONE_SHOT (1 << 0) +#define LPS25H_CTRL_REG2_AUTO_ZERO (1 << 1) +#define LPS25H_CTRL_REG2_SWRESET (1 << 2) +#define LPS25H_CTRL_REG2_FIFO_MEAN_DEC (1 << 4) +#define LPS25H_CTRL_REG2_WTM_EN (1 << 5) +#define LPS25H_CTRL_REG2_FIFO_EN (1 << 6) +#define LPS25H_CTRL_REG2_BOOT (1 << 7) +/** @} */ + +/** + * @name LPS25H_CTRL_REG3 register bits definitions + * @{ + */ +#define LPS25H_CTRL_REG3_MASK 0xC3 +#define LPS25H_CTRL_REG3_INT_S1 (1 << 0) +#define LPS25H_CTRL_REG3_INT_S2 (1 << 1) +#define LPS25H_CTRL_REG3_PP_OD (1 << 6) +#define LPS25H_CTRL_REG3_INT_H_L (1 << 7) +/** @} */ + +/** + * @name LPS25H_CTRL_REG4 register bits definitions + * @{ + */ +#define LPS25H_CTRL_REG4_MASK 0x0F +#define LPS25H_CTRL_REG4_P1_DRDY (1 << 0) +#define LPS25H_CTRL_REG4_P1_OVERRUN (1 << 1) +#define LPS25H_CTRL_REG4_P1_WTM (1 << 2) +#define LPS25H_CTRL_REG4_P1_EMPTY (1 << 3) +/** @} */ + +/** + * @name LPS25H_INT1_CFG register bits definitions + * @{ + */ +#define LPS25H_INT1_CFG_MASK 0x07 +#define LPS25H_INT1_CFG_PH_E (1 << 0) +#define LPS25H_INT1_CFG_PL_E (1 << 1) +#define LPS25H_INT1_CFG_LIR (1 << 2) +/** @} */ + +/** + * @name LPS25H_INT1_SRC register bits definitions + * @{ + */ +#define LPS25H_INT1_SRC_MASK 0x07 +#define LPS25H_INT1_SRC_PH (1 << 0) +#define LPS25H_INT1_SRC_PL (1 << 1) +#define LPS25H_INT1_SRC_IA (1 << 2) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief LPS25H SPI interface switch. + * @details If set to @p TRUE the support for SPI is included. + * @note The default is @p FALSE. + */ +#if !defined(LPS25H_USE_SPI) || defined(__DOXYGEN__) +#define LPS25H_USE_SPI FALSE +#endif + +/** + * @brief LPS25H I2C interface switch. + * @details If set to @p TRUE the support for I2C is included. + * @note The default is @p FALSE. + */ +#if !defined(LPS25H_USE_I2C) || defined(__DOXYGEN__) +#define LPS25H_USE_I2C TRUE +#endif + +/** + * @brief LPS25H advanced configurations switch. + * @details If set to @p TRUE more configurations are available. + * @note The default is @p FALSE. + */ +#if !defined(LPS25H_USE_ADVANCED) || defined(__DOXYGEN__) +#define LPS25H_USE_ADVANCED FALSE +#endif + +/** + * @brief LPS25H shared I2C switch. + * @details If set to @p TRUE the device acquires I2C bus ownership + * on each transaction. + * @note The default is @p FALSE. Requires I2C_USE_MUTUAL_EXCLUSION + */ +#if !defined(LPS25H_SHARED_SPI) || defined(__DOXYGEN__) +#define LPS25H_SHARED_I2C FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !(LPS25H_USE_SPI ^ LPS25H_USE_I2C) +#error "LPS25H_USE_SPI and LPS25H_USE_I2C cannot be both true or both false" +#endif + +#if LPS25H_USE_SPI && !HAL_USE_SPI +#error "LPS25H_USE_SPI requires HAL_USE_SPI" +#endif + +#if LPS25H_USE_SPI +#error "LPS25H over SPI still not supported" +#endif + +#if LPS25H_USE_I2C && !HAL_USE_I2C +#error "LPS25H_USE_I2C requires HAL_USE_I2C" +#endif + +#if LPS25H_SHARED_I2C && !I2C_USE_MUTUAL_EXCLUSION +#error "LPS25H_SHARED_I2C requires I2C_USE_MUTUAL_EXCLUSION" +#endif + +/* + * TODO: Add SPI support. + */ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @name LPS25H data structures and types. + * @{ + */ +/** + * @brief LPS25H slave address + */ +typedef enum { + LPS25H_SAD_GND = 0x5C, /**< Slave Address when SA0 is to GND */ + LPS25H_SAD_VCC = 0x5D /**< Slave Address when SA0 is to VCC */ +}lps25h_sad_t; + +/** + * @brief LPS25H output data rate and bandwidth. + */ +typedef enum { + LPS25H_ODR_ONE_SHOT = 0x00, /**< One shot. */ + LPS25H_ODR_1HZ = 0x10, /**< Output data rate 1 Hz. */ + LPS25H_ODR_7HZ = 0x20, /**< Output data rate 7 Hz. */ + LPS25H_ODR_12P5HZ = 0x30, /**< Output data rate 12.5 Hz. */ + LPS25H_ODR_25HZ = 0x40 /**< Output data rate 25 Hz. */ +}lps25h_odr_t; + +/** + * @brief LPS25H pressure resolution. + */ +typedef enum { + LPS25H_AVGP_8 = 0x00, /**< Number of internal average is 8. */ + LPS25H_AVGP_32 = 0x01, /**< Number of internal average is 8. */ + LPS25H_AVGP_128 = 0x02, /**< Number of internal average is 8. */ + LPS25H_AVGP_512 = 0x03, /**< Number of internal average is 8. */ +}lps25h_avgp_t; + +/** + * @brief LPS25H temperature resolution. + */ +typedef enum { + LPS25H_AVGT_8 = 0x00, /**< Number of internal average is 8. */ + LPS25H_AVGT_32 = 0x04, /**< Number of internal average is 8. */ + LPS25H_AVGT_128 = 0x08, /**< Number of internal average is 8. */ + LPS25H_AVGT_512 = 0x0C, /**< Number of internal average is 8. */ +}lps25h_avgt_t; + +/** + * @brief LPS25H block data update. + */ +typedef enum { + LPS25H_BDU_CONTINUOUS = 0x00, /**< Block data continuously updated. */ + LPS25H_BDU_BLOCKED = 0x40 /**< Block data updated after reading. */ +}lps25h_bdu_t; + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + LPS25H_UNINIT = 0, /**< Not initialized. */ + LPS25H_STOP = 1, /**< Stopped. */ + LPS25H_READY = 2, /**< Ready. */ +} lps25h_state_t; + +/** + * @brief LPS25H configuration structure. + */ +typedef struct { + +#if LPS25H_USE_SPI || defined(__DOXYGEN__) + /** + * @brief SPI driver associated to this LPS25H. + */ + SPIDriver *spip; + /** + * @brief SPI configuration associated to this LPS25H. + */ + const SPIConfig *spicfg; +#endif /* LPS25H_USE_SPI */ +#if LPS25H_USE_I2C || defined(__DOXYGEN__) + /** + * @brief I2C driver associated to this LPS25H. + */ + I2CDriver *i2cp; + /** + * @brief I2C configuration associated to this LPS25H. + */ + const I2CConfig *i2ccfg; +#endif /* LPS25H_USE_I2C */ + /** + * @brief LPS25H initial sensitivity. + */ + float sensitivity; + /** + * @brief LPS25H initial bias. + */ + float bias; + /** + * @brief LPS25H slave address + */ + lps25h_sad_t slaveaddress; + /** + * @brief LPS25H output data rate selection. + */ + lps25h_odr_t outputdatarate; +#if LPS25H_USE_ADVANCED || defined(__DOXYGEN__) + /** + * @brief LPS25H block data update. + */ + lps25h_bdu_t blockdataupdate; + /** + * @brief LPS25H pressure resolution. + */ + lps25h_avgp_t respressure; + /** + * @brief LPS25H temperature resolution. + */ + lps25h_avgt_t restemperature; +#endif +} LPS25HConfig; + +/** + * @brief Structure representing a LPS25H driver. + */ +typedef struct LPS25HDriver LPS25HDriver; + +/** + * @brief @p LPS25H specific methods. + */ +#define _lps25h_methods \ + _base_barometer_methods + +/** + * @extends BaseGyroscopeVMT + * + * @brief @p LPS25H virtual methods table. + */ +struct LPS25HVMT { + _lps25h_methods +}; + +/** + * @brief @p LPS25HDriver specific data. + */ +#define _lps25h_data \ + _base_barometer_data \ + /* Driver state.*/ \ + lps25h_state_t state; \ + /* Current configuration data.*/ \ + const LPS25HConfig *config; \ + /* Current sensitivity data.*/ \ + float sensitivity; \ + /* Current Bias data.*/ \ + float bias; + +/** + * @extends BaseGyroscope + * + * @brief LPS25H 3-axis barometer class. + * @details This class extends @p BaseGyroscope by adding physical + * driver implementation. + */ +struct LPS25HDriver { + /** @brief BaseSensor Virtual Methods Table. */ + const struct BaseSensorVMT *vmt_basesensor; + /** @brief BaseBarometer Virtual Methods Table. */ + const struct BaseBarometerVMT *vmt_basebarometer; + /** @brief LPS25H Virtual Methods Table. */ + const struct LPS25HVMT *vmt_lps25h; + _lps25h_data +}; +/** @} */ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void lps25hObjectInit(LPS25HDriver *devp); + void lps25hStart(LPS25HDriver *devp, const LPS25HConfig *config); + void lps25hStop(LPS25HDriver *devp); +#ifdef __cplusplus +} +#endif + +#endif /* _LPS25H_H_ */ + +/** @} */ + diff --git a/os/ex/ST/lps25h.mk b/os/ex/ST/lps25h.mk new file mode 100644 index 000000000..1d8d6ec8d --- /dev/null +++ b/os/ex/ST/lps25h.mk @@ -0,0 +1,6 @@ +# List of all the LPS25H device files. +LPS25HSRC := $(CHIBIOS)/os/ex/ST/lps25h.c + +# Required include directories +LPS25HINC := $(CHIBIOS)/os/hal/lib/peripherals/sensors \ + $(CHIBIOS)/os/ex/ST \ No newline at end of file diff --git a/testhal/STM32/STM32F4xx/I2C-LPS25H/.cproject b/testhal/STM32/STM32F4xx/I2C-LPS25H/.cproject new file mode 100644 index 000000000..0012badfd --- /dev/null +++ b/testhal/STM32/STM32F4xx/I2C-LPS25H/.cproject @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32/STM32F4xx/I2C-LPS25H/.project b/testhal/STM32/STM32F4xx/I2C-LPS25H/.project new file mode 100644 index 000000000..ca572b406 --- /dev/null +++ b/testhal/STM32/STM32F4xx/I2C-LPS25H/.project @@ -0,0 +1,38 @@ + + + STM32F4xx-I2C-LPS25H + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/os/hal/boards/ST_NUCLEO64_F401RE + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/STM32/STM32F4xx/I2C-LPS25H/Makefile b/testhal/STM32/STM32F4xx/I2C-LPS25H/Makefile new file mode 100644 index 000000000..057c420fb --- /dev/null +++ b/testhal/STM32/STM32F4xx/I2C-LPS25H/Makefile @@ -0,0 +1,223 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../.. +# Startup files. +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F401RE/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). +include $(CHIBIOS)/os/ex/ST/lps25h.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/STM32F401xE.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(LPS25HSRC) \ + $(STREAMSSRC) \ + $(SHELLSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = +ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(CHIBIOS)/os/license \ + $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(LPS25HINC) \ + $(STREAMSINC) $(SHELLINC) + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DCHPRINTF_USE_FLOAT=1 -DSHELL_CMD_TEST_ENABLED=0 \ + -DLPS25H_USE_ADVANCED=0 + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/STM32/STM32F4xx/I2C-LPS25H/build/ch.elf b/testhal/STM32/STM32F4xx/I2C-LPS25H/build/ch.elf new file mode 100644 index 000000000..3e24a5e23 Binary files /dev/null and b/testhal/STM32/STM32F4xx/I2C-LPS25H/build/ch.elf differ diff --git a/testhal/STM32/STM32F4xx/I2C-LPS25H/chconf.h b/testhal/STM32/STM32F4xx/I2C-LPS25H/chconf.h new file mode 100644 index 000000000..ad6b53ade --- /dev/null +++ b/testhal/STM32/STM32F4xx/I2C-LPS25H/chconf.h @@ -0,0 +1,520 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/STM32/STM32F4xx/I2C-LPS25H/debug/STM32F4xx-I2C-LPS25H (OpenOCD, Flash and Run).launch b/testhal/STM32/STM32F4xx/I2C-LPS25H/debug/STM32F4xx-I2C-LPS25H (OpenOCD, Flash and Run).launch new file mode 100644 index 000000000..7a2096330 --- /dev/null +++ b/testhal/STM32/STM32F4xx/I2C-LPS25H/debug/STM32F4xx-I2C-LPS25H (OpenOCD, Flash and Run).launch @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32/STM32F4xx/I2C-LPS25H/halconf.h b/testhal/STM32/STM32F4xx/I2C-LPS25H/halconf.h new file mode 100644 index 000000000..07b0143bd --- /dev/null +++ b/testhal/STM32/STM32F4xx/I2C-LPS25H/halconf.h @@ -0,0 +1,388 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C TRUE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the QSPI subsystem. + */ +#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__) +#define HAL_USE_QSPI FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/STM32/STM32F4xx/I2C-LPS25H/main.c b/testhal/STM32/STM32F4xx/I2C-LPS25H/main.c new file mode 100644 index 000000000..c31fef938 --- /dev/null +++ b/testhal/STM32/STM32F4xx/I2C-LPS25H/main.c @@ -0,0 +1,180 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#include "string.h" +#include "shell.h" +#include "chprintf.h" + +#include "lps25h.h" + +/*===========================================================================*/ +/* LPS25H related. */ +/*===========================================================================*/ + +/* LPS25H Driver: This object represent an LPS25H instance */ +static LPS25HDriver LPS25HD1; + +static int32_t rawdata; +static float cookeddata; + +static const I2CConfig i2ccfg = { + OPMODE_I2C, + 400000, + FAST_DUTY_CYCLE_2, +}; + +static const LPS25HConfig lps25hcfg = { + &I2CD1, + &i2ccfg, + 0, /* Use default sensitivity.*/ + 0, /* Use default bias.*/ + LPS25H_SAD_VCC, /* SA0 connected to VCC */ + LPS25H_ODR_7HZ, /* Output data rate 7 Hz.*/ +#if LPS25H_USE_ADVANCED || defined(__DOXYGEN__) + LPS25H_BDU_CONTINUOUS, + LPS25H_AVGP_512, + LPS25H_AVGT_512 +#endif +}; + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +/* Enable use of special ANSI escape sequences */ +#define CHPRINTF_USE_ANSI_CODE TRUE +#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048) + +static void cmd_read(BaseSequentialStream *chp, int argc, char *argv[]) { + + if (argc != 1) { + chprintf(chp, "Usage: read [raw|cooked]\r\n"); + return; + } + + while (chnGetTimeout((BaseChannel *)chp, 150) == Q_TIMEOUT) { + if (!strcmp (argv[0], "raw")) { +#if CHPRINTF_USE_ANSI_CODE + chprintf(chp, "\033[2J\033[1;1H"); +#endif + barometerReadRaw(&LPS25HD1, &rawdata); + chprintf(chp, "LPS25H Barometer raw data...\r\n"); + chprintf(chp, "RAW: %d\r\n", rawdata); + } + else if (!strcmp (argv[0], "cooked")) { +#if CHPRINTF_USE_ANSI_CODE + chprintf(chp, "\033[2J\033[1;1H"); +#endif + barometerReadCooked(&LPS25HD1, &cookeddata); + chprintf(chp, "LPS25H Barometer cooked data...\r\n"); + chprintf(chp, "COOCKED: %.4f hPa\r\n", cookeddata); + } + else { + chprintf(chp, "Usage: read [raw|cooked]\r\n"); + return; + } + } + chprintf(chp, "Stopped\r\n"); +} + +static const ShellCommand commands[] = { + {"read", cmd_read}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD2, + commands +}; + +/*===========================================================================*/ +/* Main code. */ +/*===========================================================================*/ + +/* + * LED blinker thread, times are in milliseconds. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (true) { + palClearPad(GPIOA, GPIOA_LED_GREEN); + chThdSleepMilliseconds(500); + palSetPad(GPIOA, GPIOA_LED_GREEN); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + palSetLineMode(LINE_ARD_D15, PAL_MODE_ALTERNATE(4) | + PAL_STM32_OSPEED_HIGHEST); + palSetLineMode(LINE_ARD_D14, PAL_MODE_ALTERNATE(4) | + PAL_STM32_OSPEED_HIGHEST); + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * LPS25H Object Initialization + */ + lps25hObjectInit(&LPS25HD1); + + /* + * Activates the LPS25H driver. + */ + lps25hStart(&LPS25HD1, &lps25hcfg); + + /* + * Shell manager initialization. + */ + shellInit(); + + while(TRUE) { + + thread_t *shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, + "shell", NORMALPRIO + 1, + shellThread, (void *)&shell_cfg1); + chThdWait(shelltp); /* Waiting termination. */ + chThdSleepMilliseconds(1000); + } + lps25hStop(&LPS25HD1); +} diff --git a/testhal/STM32/STM32F4xx/I2C-LPS25H/mcuconf.h b/testhal/STM32/STM32F4xx/I2C-LPS25H/mcuconf.h new file mode 100644 index 000000000..166f04112 --- /dev/null +++ b/testhal/STM32/STM32F4xx/I2C-LPS25H/mcuconf.h @@ -0,0 +1,251 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLM_VALUE 16 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 4 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* MCUCONF_H */ diff --git a/testhal/STM32/STM32F4xx/I2C-LPS25H/readme.txt b/testhal/STM32/STM32F4xx/I2C-LPS25H/readme.txt new file mode 100644 index 000000000..aae24364d --- /dev/null +++ b/testhal/STM32/STM32F4xx/I2C-LPS25H/readme.txt @@ -0,0 +1,32 @@ +***************************************************************************** +** ChibiOS/HAL + ChibiOS/EX - SPI + L3GD20 demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STM32 Nucleo64-F401RE board. It has been tested with the +X-NUCLEO-IKS01A1 shield. + +** The Demo ** + +The application demonstrates the use of the STM32F4xx I2C driver in order +to acquire data from LSM6DS0 using ChibiOS/EX. + +** Board Setup ** + +None required. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com