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ChibiOS
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LED flashing but at a wrong rate, so, still issues. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11183 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2017-12-25 17:22:41 +00:00
parent 72c3417c88
commit faf6c9f25f
6 changed files with 11 additions and 20 deletions
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2
demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch
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File diff suppressed because one or more lines are too long

10
demos/STM32/RT-STM32H743I-NUCLEO144/main.c
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@ -29,9 +29,9 @@ static THD_FUNCTION(Thread1, arg) {
(void)arg;
chRegSetThreadName("blinker");
while (true) {
palSetLine(LINE_ARD_D13);
palSetLine(LINE_ZIO_D33);
chThdSleepMilliseconds(500);
palClearLine(LINE_ARD_D13);
palClearLine(LINE_ZIO_D33);
chThdSleepMilliseconds(500);
}
}
@ -51,12 +51,6 @@ int main(void) {
halInit();
chSysInit();
/*
* ARD_D13 is programmed as output (board LED).
*/
palClearLine(LINE_ARD_D13);
palSetLineMode(LINE_ARD_D13, PAL_MODE_OUTPUT_PUSHPULL);
/*
* Activates the serial driver 1 using the driver default configuration.
*/

8
demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h
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@ -102,10 +102,6 @@
#define STM32_PLL3_DIVP_VALUE 2
#define STM32_PLL3_DIVQ_VALUE 8
#define STM32_PLL3_DIVR_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
#define STM32_MCO1PRE_VALUE 4
#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
#define STM32_MCO2PRE_VALUE 4
/*
* Core clocks dynamic settings (can be changed at runtime).
@ -124,6 +120,10 @@
* Peripherals clocks static settings.
* Reading STM32 Reference Manual is required.
*/
#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
#define STM32_MCO1PRE_VALUE 4
#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
#define STM32_MCO2PRE_VALUE 4
#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK
#define STM32_QSPISEL STM32_QSPISEL_HCLK

4
os/hal/boards/ST_NUCLEO144_H743ZI/board.c
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@ -155,8 +155,8 @@ static void stm32_gpio_init(void) {
/* Enabling GPIO-related clocks, the mask comes from the
registry header file.*/
rccResetAHB1(STM32_GPIO_EN_MASK);
rccEnableAHB1(STM32_GPIO_EN_MASK, true);
rccResetAHB4(STM32_GPIO_EN_MASK);
rccEnableAHB4(STM32_GPIO_EN_MASK, true);
/* Initializing all the defined GPIO ports.*/
#if STM32_HAS_GPIOA

1
os/hal/ports/STM32/LLD/GPIOv2/stm32_gpio.h
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@ -96,7 +96,6 @@ typedef struct {
volatile uint32_t LOCKR;
volatile uint32_t AFRL;
volatile uint32_t AFRH;
volatile uint32_t BRR;
} stm32_gpio_t;
/*===========================================================================*/

6
os/hal/ports/STM32/STM32H7xx/hal_lld.h
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@ -1607,8 +1607,7 @@
/**
* @brief PLL2 DIVP field.
*/
#if ((STM32_PLL2_DIVP_VALUE >= 2) && (STM32_PLL2_DIVP_VALUE <= 128) && \
((STM32_PLL2_DIVP_VALUE & 1U) == 0U)) || \
#if ((STM32_PLL2_DIVP_VALUE >= 2) && (STM32_PLL2_DIVP_VALUE <= 128)) || \
defined(__DOXYGEN__)
#define STM32_PLL2_DIVP ((STM32_PLL2_DIVP_VALUE - 1U) << 9U)
#else
@ -1618,8 +1617,7 @@
/**
* @brief PLL3 DIVP field.
*/
#if ((STM32_PLL3_DIVP_VALUE >= 2) && (STM32_PLL3_DIVP_VALUE <= 128) && \
((STM32_PLL3_DIVP_VALUE & 1U) == 0U)) || \
#if ((STM32_PLL3_DIVP_VALUE >= 2) && (STM32_PLL3_DIVP_VALUE <= 128)) || \
defined(__DOXYGEN__)
#define STM32_PLL3_DIVP ((STM32_PLL3_DIVP_VALUE - 1U) << 9U)
#else