diff --git a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h
index 8f6984d18..3526305c7 100644
--- a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h
+++ b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h
@@ -717,11 +717,11 @@
 #if STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
 #define STM32_ADC123_CLOCK              (STM32_ADCCLK / ADC123_PRESC_VALUE)
 #elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC123_CLOCK              (STM32_HCLK / 1)
+#define STM32_ADC123_CLOCK              (STM32_ADCCLK / 1)
 #elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
-#define STM32_ADC123_CLOCK              (STM32_HCLK / 2)
+#define STM32_ADC123_CLOCK              (STM32_ADCCLK / 2)
 #elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
-#define STM32_ADC123_CLOCK              (STM32_HCLK / 4)
+#define STM32_ADC123_CLOCK              (STM32_ADCCLK / 4)
 #else
 #error "invalid clock mode selected for STM32_ADC_ADC123_CLOCK_MODE"
 #endif
diff --git a/readme.txt b/readme.txt
index c7351f139..50d98e8c8 100644
--- a/readme.txt
+++ b/readme.txt
@@ -74,6 +74,8 @@
 *****************************************************************************
 
 *** Next ***
+- FIX: Fixed incorrect clock check when using PLLSAI1R in ADCv3 (bug #1078)
+       (backported to 20.3.1).
 - RT:  Relocated the "ctx" field in the thread structure in order to save
        some RAM, it caused unused space in the "ch" variable.
 - EX:  Added support for ADXL355 Low Noise, Low Drift, Low Power, 3-Axis
@@ -86,3 +88,4 @@
        (backported to 20.3.1).
 - FIX: Fixed problem in chMtxUnlockAllS() (bug #1076).
        (backported to 20.3.1)(backported to 19.1.4)(backported to 18.2.3).
+