From fcb6bb70855e9894e1425987f5af6c82a9bdc3c3 Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Fri, 24 Jul 2020 08:49:43 +0000
Subject: [PATCH] #1117 #4.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13781 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
---
 os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h | 37 ++++++++++++++++++++++
 os/hal/ports/STM32/STM32H7xx/hal_lld.h     |  2 +-
 2 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h b/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h
index 9a53c0483..350770380 100644
--- a/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h
+++ b/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h
@@ -350,7 +350,42 @@
 #error "Invalid IRQ priority assigned to ADC3"
 #endif
 
+#if !defined(STM32_ENFORCE_H7_REV_XY)
 /* ADC clock source checks.*/
+#if (STM32_D1HPRE == STM32_D1HPRE_DIV1)
+#define STM32_ADC_SCLK                  STM32_SYSCLK
+#else
+#define STM32_ADC_SCLK                  (STM32_SYSCLK / 2)
+#endif
+
+#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
+/* CHTODO: also check ADC_CCR_PRESC.*/
+#define STM32_ADC12_CLOCK               (STM32_ADCCLK / 2)
+#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
+#define STM32_ADC12_CLOCK               (STM32_ADC_SCLK / 1 / 2)
+#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
+#define STM32_ADC12_CLOCK               (STM32_ADC_SCLK / 2 / 2)
+#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
+#define STM32_ADC12_CLOCK               (STM32_ADC_SCLK / 4 / 2)
+#else
+#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
+#endif
+
+#if STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
+/* CHTODO: also check ADC_CCR_PRESC.*/
+#define STM32_ADC3_CLOCK               (STM32_ADCCLK / 2)
+#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
+#define STM32_ADC3_CLOCK               (STM32_ADC_SCLK / 1 / 2)
+#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
+#define STM32_ADC3_CLOCK               (STM32_ADC_SCLK / 2 / 2)
+#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
+#define STM32_ADC3_CLOCK               (STM32_ADC_SCLK / 4 / 2)
+#else
+#error "invalid clock mode selected for STM32_ADC_ADC3_CLOCK_MODE"
+#endif
+
+#else /* defined(STM32_ENFORCE_H7_REV_XY) */
+
 #if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
 #define STM32_ADC12_CLOCK               STM32_ADCCLK
 #elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
@@ -375,6 +410,8 @@
 #error "invalid clock mode selected for STM32_ADC_ADC3_CLOCK_MODE"
 #endif
 
+#endif /* defined(STM32_ENFORCE_H7_REV_XY) */
+
 #if STM32_ADC12_CLOCK > STM32_ADCCLK_MAX
 #error "STM32_ADC12_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)"
 #endif
diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
index 9867fa435..3dc31c512 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
@@ -212,7 +212,7 @@
 /**
  * @brief   Maximum ADC clock frequency.
  */
-#define STM32_ADCCLK_MAX                100000000
+#define STM32_ADCCLK_MAX                50000000
 /** @} */
 
 #else /* defined(STM32_ENFORCE_H7_REV_XY) */