From fcf9090b967d7078d20072e3fef2e269ecff9699 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 8 Feb 2013 15:23:03 +0000 Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5130 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/GENERIC_SPC56EL/board.c | 2 +- demos/PPC-SPC56EL-GCC/.project | 2 +- demos/PPC-SPC56EL-GCC/Makefile | 2 +- os/hal/platforms/SPC56ELxx/hal_lld.c | 62 +++++++++++----------------- os/hal/platforms/SPC56ELxx/hal_lld.h | 8 ++-- 5 files changed, 31 insertions(+), 45 deletions(-) diff --git a/boards/GENERIC_SPC56EL/board.c b/boards/GENERIC_SPC56EL/board.c index e5d7d2a83..d3595528f 100644 --- a/boards/GENERIC_SPC56EL/board.c +++ b/boards/GENERIC_SPC56EL/board.c @@ -55,7 +55,7 @@ const PALConfig pal_default_config = { */ void __early_init(void) { - spc_clock_init(); + spc_early_init(); /* SWT disabled.*/ SWT.SR.R = 0xC520; diff --git a/demos/PPC-SPC56EL-GCC/.project b/demos/PPC-SPC56EL-GCC/.project index 3f986fc83..67220475f 100644 --- a/demos/PPC-SPC56EL-GCC/.project +++ b/demos/PPC-SPC56EL-GCC/.project @@ -27,7 +27,7 @@ board 2 - CHIBIOS/boards/GENERIC_SPC563M + CHIBIOS/boards/GENERIC_SPC56EL os diff --git a/demos/PPC-SPC56EL-GCC/Makefile b/demos/PPC-SPC56EL-GCC/Makefile index 7561877cc..c35491bda 100644 --- a/demos/PPC-SPC56EL-GCC/Makefile +++ b/demos/PPC-SPC56EL-GCC/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C specific options here (added to USE_OPT). diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.c b/os/hal/platforms/SPC56ELxx/hal_lld.c index 792ab7f22..3e52ea1ff 100644 --- a/os/hal/platforms/SPC56ELxx/hal_lld.c +++ b/os/hal/platforms/SPC56ELxx/hal_lld.c @@ -39,25 +39,6 @@ /* Driver interrupt handlers. */ /*===========================================================================*/ -/** - * @brief PIT channel 3 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(vector59) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - /* Resets the PIT channel 3 IRQ flag.*/ - PIT.CHANNEL[0].TFLG.R = 1; - - CH_IRQ_EPILOGUE(); -} - /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -69,7 +50,6 @@ CH_IRQ_HANDLER(vector59) { */ void hal_lld_init(void) { extern void _vectors(void); - uint32_t reg; /* The system is switched to the RUN0 mode, the default for normal operations.*/ @@ -81,30 +61,17 @@ void hal_lld_init(void) { INTC.MCR.R = 0; INTC.CPR.R = 0; INTC.IACKR.R = (uint32_t)_vectors; - - /* PIT channel 0 initialization for Kernel ticks, the PIT is configured - to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other - modes.*/ - INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY; - halSPCSetPeripheralClockMode(92, - SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); - reg = halSPCGetSystemClock() / CH_FREQUENCY - 1; - PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */ - PIT.CHANNEL[0].LDVAL.R = reg; - PIT.CHANNEL[0].CVAL.R = reg; - PIT.CHANNEL[0].TFLG.R = 1; /* Interrupt flag cleared. */ - PIT.CHANNEL[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */ } /** - * @brief SPC56ELxx clocks and PLL initialization. + * @brief SPC56ELxx early initialization. * @note All the involved constants come from the file @p board.h and * @p hal_lld.h * @note This function must be invoked only after the system reset. * * @special */ -void spc_clock_init(void) { +void spc_early_init(void) { /* Waiting for IRC stabilization before attempting anything else.*/ while (!ME.GS.B.S_IRCOSC) @@ -112,6 +79,29 @@ void spc_clock_init(void) { #if !SPC5_NO_INIT + /* SSCM initialization. Setting up the most restrictive handling of + invalid accesses to peripherals.*/ + SSCM.ERROR.R = 3; /* PAE and RAE bits. */ + + /* Enabling peripheral bridges to allow any operation.*/ + AIPS.MPROT.R = 0x77777777; + AIPS.PACR0_7.R = 0; + AIPS.PACR8_15.R = 0; + AIPS.PACR16_23.R = 0; + AIPS.PACR24_31.R = 0; + AIPS.OPACR0_7.R = 0; + AIPS.OPACR8_15.R = 0; + AIPS.OPACR16_23.R = 0; + AIPS.OPACR24_31.R = 0; + AIPS.OPACR32_39.R = 0; + AIPS.OPACR40_47.R = 0; + AIPS.OPACR48_55.R = 0; + AIPS.OPACR56_63.R = 0; + AIPS.OPACR64_71.R = 0; + AIPS.OPACR72_79.R = 0; + AIPS.OPACR80_87.R = 0; + AIPS.OPACR88_95.R = 0; + #if defined(SPC5_OSC_BYPASS) /* If the board is equipped with an oscillator instead of a xtal then the bypass must be activated.*/ @@ -235,8 +225,6 @@ uint32_t halSPCGetSystemClock(void) { return SPC5_XOSC_CLK; case SPC5_ME_GS_SYSCLK_FMPLL0: return SPC5_FMPLL0_CLK; - case SPC5_ME_GS_SYSCLK_FMPLL1: - return SPC5_FMPLL1_CLK; default: return 0; } diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.h b/os/hal/platforms/SPC56ELxx/hal_lld.h index 9f679555c..d83265061 100644 --- a/os/hal/platforms/SPC56ELxx/hal_lld.h +++ b/os/hal/platforms/SPC56ELxx/hal_lld.h @@ -108,8 +108,8 @@ * @name FMPLLs register bits definitions * @{ */ -#define SPC5_FMPLL_SRC_IRC (0 << 24) -#define SPC5_FMPLL_SRC_XOSC (1 << 24) +#define SPC5_FMPLL_SRC_IRC (0U << 24) +#define SPC5_FMPLL_SRC_XOSC (1U << 24) /** @} */ /** @@ -130,7 +130,6 @@ #define SPC5_ME_GS_SYSCLK_IRC (0U << 0) #define SPC5_ME_GS_SYSCLK_XOSC (2U << 0) #define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0) -#define SPC5_ME_GS_SYSCLK_FMPLL1 (5U << 0) /** @} */ /** @@ -157,7 +156,6 @@ #define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0) #define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2) #define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4) -#define SPC5_ME_MC_SYSCLK_FMPLL1 SPC5_ME_MC_SYSCLK(5) #define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15) #define SPC5_ME_MC_IRCON (1U << 4) #define SPC5_ME_MC_XOSC0ON (1U << 5) @@ -743,7 +741,7 @@ typedef enum { extern "C" { #endif void hal_lld_init(void); - void spc_clock_init(void); + void spc_early_init(void); bool_t halSPCSetRunMode(spc5_runmode_t mode); void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl); #if !SPC5_NO_INIT