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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3254 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2011-08-26 13:47:22 +00:00
parent 0aa2dd0511
commit fe0093f795
37 changed files with 799 additions and 67 deletions
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2
os/hal/platforms/STM32/DMAv1/stm32_dma.c
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@ -19,7 +19,7 @@
*/
/**
* @file stm32_dma.c
* @file DMAv1/stm32_dma.c
* @brief STM32 DMA helper driver code.
*
* @addtogroup STM32_DMA

2
os/hal/platforms/STM32/DMAv1/stm32_dma.h
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@ -19,7 +19,7 @@
*/
/**
* @file stm32_dma.h
* @file DMAv1/stm32_dma.h
* @brief STM32 DMA helper driver header.
* @note This file requires definitions from the ST STM32 header file
* stm32f10x.h.

239
os/hal/platforms/STM32/DMAv1/stm32_dma_alt.c Normal file
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@ -0,0 +1,239 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file DMAv1/stm32_dma.c
* @brief DMA helper driver code.
*
* @addtogroup STM32_DMA
* @details DMA sharing helper driver. In the STM32 the DMA streams are a
* shared resource, this driver allows to allocate and free DMA
* streams at runtime in order to allow all the other device
* drivers to coordinate the access to the resource.
* @note The DMA ISR handlers are all declared into this module because
* sharing, the various device drivers can associate a callback to
* IRSs when allocating streams.
* @{
*/
#include "ch.h"
#include "hal.h"
/* The following macro is only defined if some driver requiring DMA services
has been enabled.*/
#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/**
* @brief Mask of the DMA1 streams in @p dma_streams_mask.
*/
#define STM32_DMA1_STREAMS_MASK 0x0000007F
/**
* @brief Mask of the DMA2 streams in @p dma_streams_mask.
*/
#define STM32_DMA2_STREAMS_MASK 0x00000F80
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/**
* @brief DMA streams descriptors.
* @details This table keeps the association between an unique stream
* identifier and the involved physical registers.
* @note Don't use this array directly, use the appropriate wrapper macros
* instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
*/
const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
{0, DMA1, DMA1_Channel1, &DMA1->IFCR, 0},
{1, DMA1, DMA1_Channel2, &DMA1->IFCR, 4},
{2, DMA1, DMA1_Channel3, &DMA1->IFCR, 8},
{3, DMA1, DMA1_Channel4, &DMA1->IFCR, 12},
{4, DMA1, DMA1_Channel5, &DMA1->IFCR, 16},
{5, DMA1, DMA1_Channel6, &DMA1->IFCR, 20},
{6, DMA1, DMA1_Channel7, &DMA1->IFCR, 24},
#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
{7, DMA2, DMA2_Channel1, &DMA2->IFCR, 0},
{8, DMA2, DMA2_Channel2, &DMA2->IFCR, 4},
{9, DMA2, DMA2_Channel3, &DMA2->IFCR, 8},
{10, DMA2, DMA2_Channel4, &DMA2->IFCR, 12},
{11, DMA2, DMA2_Channel5, &DMA2->IFCR, 16},
#endif
};
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/**
* @brief DMA ISR redirector type.
*/
typedef struct {
stm32_dmaisr_t dma_func;
void *dma_param;
} dma_isr_redir_t;
/**
* @brief Mask of the allocated streams.
*/
static uint32_t dma_streams_mask;
/**
* @brief DMA IRQ redirectors.
*/
static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/**
* @brief DMA1 stream 1 shared interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
uint32_t flags;
CH_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
if (dma_isr_redir[0].dma_func)
dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
CH_IRQ_EPILOGUE();
}
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief STM32 DMA helper initialization.
*
* @init
*/
void dmaInit(void) {
int i;
dma_streams_mask = 0;
for (i = 0; i < STM32_DMA_STREAMS; i--) {
_stm32_dma_streams[i].channel->CCR = 0;
dma_isr_redir[i].dma_func = NULL;
}
DMA1->IFCR = 0xFFFFFFFF;
#if STM32_HAS_DMA2
DMA2->IFCR = 0xFFFFFFFF;
#endif
}
/**
* @brief Allocates a DMA stream.
* @details The stream is allocated and, if required, the DMA clock enabled.
* Trying to allocate a stream already allocated is an illegal
* operation and is trapped if assertions are enabled.
* @pre The stream must not be already in use.
* @post The stream is allocated and the default ISR handler redirected
* to the specified function.
* @post The stream must be freed using @p dmaRelease() before it can
* be reused with another peripheral.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] func handling function pointer, can be @p NULL
* @param[in] param a parameter to be passed to the handling function
* @return The operation status.
* @retval FALSE no error, stream taken.
* @retval TRUE error, stream already taken.
*
* @special
*/
bool_t dmaAllocate(stm32_dma_stream_t *dmastp,
stm32_dmaisr_t func, void *param) {
chDbgCheck(dmastp != NULL, "dmaAllocate");
/* Checks if the stream is already taken.*/
if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
return TRUE;
/* Marks the stream as allocated.*/
dma_isr_redir[dmastp->selfindex].dma_func = func;
dma_isr_redir[dmastp->selfindex].dma_param = param;
dma_streams_mask |= (1 << dmastp->selfindex);
/* Enabling DMA clocks required by the current streams set.*/
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
RCC->AHBENR |= RCC_AHBENR_DMA1EN;
#if STM32_HAS_DMA2
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
RCC->AHBENR |= RCC_AHBENR_DMA2EN;
#endif
/* Making sure there are no spurious interrupts flags pending.*/
dmaStreamClearInterrupt(dmastp);
return FALSE;
}
/**
* @brief Releases a DMA stream.
* @details The stream is freed and, if required, the DMA clock disabled.
* Trying to release a unallocated stream is an illegal operation
* and is trapped if assertions are enabled.
* @pre The stream must have been allocated using @p dmaRequest().
* @post The stream is again available.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @special
*/
void dmaRelease(stm32_dma_stream_t *dmastp) {
chDbgCheck(dmastp != NULL, "dmaRelease");
/* Check if the streams is not taken.*/
chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
"dmaRelease(), #1", "not allocated");
/* Marks the stream as not allocated.*/
dma_streams_mask &= ~(1 << dmastp->selfindex);
/* Shutting down clocks that are no more required, if any.*/
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
RCC->AHBENR &= ~RCC_AHBENR_DMA1EN;
#if STM32_HAS_DMA2
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
RCC->AHBENR &= ~RCC_AHBENR_DMA2EN;
#endif
}
#endif /* STM32_DMA_REQUIRED */
/** @} */

261
os/hal/platforms/STM32/DMAv1/stm32_dma_alt.h Normal file
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@ -0,0 +1,261 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file DMAv1/stm32_dma.h
* @brief DMA helper driver header.
* @note This file requires definitions from the ST header files
* stm32f10x.h or stm32l1xx.h.
* @note This driver uses the new naming convention used for the STM32F2xx
* so the "DMA channels" are referred as "DMA streams".
*
* @addtogroup STM32_DMA
* @{
*/
#ifndef _STM32_DMA_H_
#define _STM32_DMA_H_
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @brief Total number of DMA streams.
* @note This is the total number of streams among all the DMA units.
*/
#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
#define STM32_DMA_STREAMS 12
#else
#define STM32_DMA_STREAMS 7
#endif
/**
* @brief Mask of the ISR bits passed to the DMA callback functions.
*/
#define STM32_DMA_ISR_MASK 0x0F
/**
* @name DMA streams identifiers
* @{
*/
#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[0])
#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[1])
#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[2])
#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[3])
#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[4])
#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[5])
#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[6])
#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[8])
#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[9])
#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[10])
#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[11])
#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[12])
/** @} */
/**
* @name CR register constants common to all DMA types
*/
#define STM32_DMA_CR_EN DMA_CCR1_EN
#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE
#define STM32_DMA_CR_HTIE DMA_CCR1_HTIE
#define STM32_DMA_CR_TCIE DMA_CCR1_TCIE
#define STM32_DMA_CR_DIR_MASK (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM)
#define STM32_DMA_CR_DIR_P2M 0
#define STM32_DMA_CR_DIR_M2P DMA_CCR1_DIR
#define STM32_DMA_CR_DIR_M2M DMA_CCR1_MEM2MEM
#define STM32_DMA_CR_CIRC DMA_CCR1_CIRC
#define STM32_DMA_CR_PINC DMA_CCR1_PINC
#define STM32_DMA_CR_MINC DMA_CCR1_MINC
#define STM32_DMA_CR_PSIZE_MASK DMA_CCR1_PSIZE
#define STM32_DMA_CR_PSIZE_BYTE 0
#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR1_PSIZE_0
#define STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1
#define STM32_DMA_CR_MSIZE_MASK DMA_CCR1_MSIZE
#define STM32_DMA_CR_MSIZE_BYTE 0
#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0
#define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1
#define STM32_DMA_CR_PL_MASK DMA_CCR1_PL
#define STM32_DMA_CR_PL(n) ((n) << 16)
/** @} */
/**
* @name CR register constants only found in enhanced DMA
*/
#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */
#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */
/** @} */
/**
* @name Status flags passed to the ISR callbacks
*/
#define STM32_DMA_ISR_FEIF 0
#define STM32_DMA_ISR_DMEIF 0
#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1
#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1
#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief STM32 DMA stream descriptor structure.
*/
typedef struct {
uint32_t selfindex; /**< @brief Index to self in array. */
DMA_TypeDef *dma; /**< @brief Associated DMA unit. */
DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */
volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
uint32_t ishift; /**< @brief Bits offset in xIFCR
register. */
} stm32_dma_stream_t;
/**
* @brief STM32 DMA ISR function type.
*
* @param[in] p parameter for the registered function
* @param[in] flags pre-shifted content of the ISR register, the bits
* are aligned to bit zero
*/
typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Associates a peripheral data register to a DMA stream.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] addr value to be written in the CPAR register
*
* @special
*/
#define dmaStreamSetPeripheral(dmastp, addr) { \
(dmastp)->channel->CPAR = (uint32_t)(addr); \
}
/**
* @brief Associates a memory destination to a DMA stream.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] addr value to be written in the CMAR register
*
* @special
*/
#define dmaStreamSetMemory0(dmastp, addr) { \
(dmastp)->channel->CMAR = (uint32_t)(addr); \
}
/**
* @brief Associates an alternate memory destination to a DMA stream.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] size value to be written in the CNDTR register
*
* @special
*/
#define dmaStreamSetTransactionSize(dmastp, size) { \
(dmastp)->channel->CNDTR = (uint32_t)(size); \
}
/**
* @brief Programs the stream mode settings.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] mode value to be written in the CCR register
*
* @special
*/
#define dmaStreamSetMode(dmastp, mode) { \
(dmastp)->channel->CCR = (uint32_t)(mode2); \
}
/**
* @brief DMA stream enable.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmachp pointer to a stm32_dma_stream_t structure
*
* @special
*/
#define dmaStreamEnable(dmachp) { \
(dmastp)->channel->CCR |= STM32_DMA_CR_EN; \
}
/**
* @brief DMA stream disable.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @special
*/
#define dmaStreamDisable(dmastp) { \
(dmastp)->channel->CCR &= ~STM32_DMA_CR_EN; \
}
/**
* @brief DMA stream interrupt sources clear.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @special
*/
#define dmaStreamClearInterrupt(dmastp) { \
*(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \
}
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
#endif
#ifdef __cplusplus
extern "C" {
#endif
void dmaInit(void);
bool_t dmaAllocate(stm32_dma_stream_t *dmastp,
stm32_dmaisr_t func, void *param);
void dmaRelease(stm32_dma_stream_t *dmastp);
#ifdef __cplusplus
}
#endif
#endif /* _STM32_DMA_H_ */
/** @} */

88
os/hal/platforms/STM32/DMAv2/stm32_dma.c
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@ -20,7 +20,7 @@
/**
* @file DMAv2/stm32_dma.c
* @brief STM32F2xx Enhanced DMA helper driver code.
* @brief Enhanced DMA helper driver code.
*
* @addtogroup STM32_DMA
* @details DMA sharing helper driver. In the STM32 the DMA streams are a
@ -40,6 +40,20 @@
has been enabled.*/
#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/**
* @brief Mask of the DMA1 streams in @p dma_streams_mask.
*/
#define STM32_DMA1_STREAMS_MASK 0x000000FF
/**
* @brief Mask of the DMA2 streams in @p dma_streams_mask.
*/
#define STM32_DMA2_STREAMS_MASK 0x0000FF00
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@ -51,23 +65,23 @@
* @note Don't use this array directly, use the appropriate wrapper macros
* instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc.
*/
const stm32_dma_stream_t _stm32_dma_streams[16] = {
{0, DMA1, DMA1_Stream0, &DMA1->LISR, &DMA1->LIFCR, 0},
{1, DMA1, DMA1_Stream1, &DMA1->LISR, &DMA1->LIFCR, 6},
{2, DMA1, DMA1_Stream2, &DMA1->LISR, &DMA1->LIFCR, 16},
{3, DMA1, DMA1_Stream3, &DMA1->LISR, &DMA1->LIFCR, 22},
{4, DMA1, DMA1_Stream4, &DMA1->HISR, &DMA1->HIFCR, 0},
{5, DMA1, DMA1_Stream5, &DMA1->HISR, &DMA1->HIFCR, 6},
{6, DMA1, DMA1_Stream6, &DMA1->HISR, &DMA1->HIFCR, 16},
{7, DMA1, DMA1_Stream7, &DMA1->HISR, &DMA1->HIFCR, 22},
{8, DMA2, DMA2_Stream0, &DMA2->LISR, &DMA2->LIFCR, 0},
{9, DMA2, DMA2_Stream1, &DMA2->LISR, &DMA2->LIFCR, 6},
{10, DMA2, DMA2_Stream2, &DMA2->LISR, &DMA2->LIFCR, 16},
{11, DMA2, DMA2_Stream3, &DMA2->LISR, &DMA2->LIFCR, 22},
{12, DMA2, DMA2_Stream4, &DMA2->HISR, &DMA2->HIFCR, 0},
{13, DMA2, DMA2_Stream5, &DMA2->HISR, &DMA2->HIFCR, 6},
{14, DMA2, DMA2_Stream6, &DMA2->HISR, &DMA2->HIFCR, 16},
{15, DMA2, DMA2_Stream7, &DMA2->HISR, &DMA2->HIFCR, 22},
const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
{0, DMA1, DMA1_Stream0, &DMA1->LIFCR, 0},
{1, DMA1, DMA1_Stream1, &DMA1->LIFCR, 6},
{2, DMA1, DMA1_Stream2, &DMA1->LIFCR, 16},
{3, DMA1, DMA1_Stream3, &DMA1->LIFCR, 22},
{4, DMA1, DMA1_Stream4, &DMA1->HIFCR, 0},
{5, DMA1, DMA1_Stream5, &DMA1->HIFCR, 6},
{6, DMA1, DMA1_Stream6, &DMA1->HIFCR, 16},
{7, DMA1, DMA1_Stream7, &DMA1->HIFCR, 22},
{8, DMA2, DMA2_Stream0, &DMA2->LIFCR, 0},
{9, DMA2, DMA2_Stream1, &DMA2->LIFCR, 6},
{10, DMA2, DMA2_Stream2, &DMA2->LIFCR, 16},
{11, DMA2, DMA2_Stream3, &DMA2->LIFCR, 22},
{12, DMA2, DMA2_Stream4, &DMA2->HIFCR, 0},
{13, DMA2, DMA2_Stream5, &DMA2->HIFCR, 6},
{14, DMA2, DMA2_Stream6, &DMA2->HIFCR, 16},
{15, DMA2, DMA2_Stream7, &DMA2->HIFCR, 22},
};
/*===========================================================================*/
@ -398,11 +412,11 @@ CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) {
* @init
*/
void dmaInit(void) {
stm32_dma_stream_t *stp;
int i;
dma_streams_mask = 0;
for (i = 0 - 1; i < STM32_DMA_STREAMS; i--) {
_stm32_dma_streams[i]->stream->CR = 0;
for (i = 0; i < STM32_DMA_STREAMS; i--) {
_stm32_dma_streams[i].stream->CR = 0;
dma_isr_redir[i].dma_func = NULL;
}
DMA1->LIFCR = 0xFFFFFFFF;
@ -426,17 +440,20 @@ void dmaInit(void) {
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] func handling function pointer, can be @p NULL
* @param[in] param a parameter to be passed to the handling function
* @return The operation status.
* @retval FALSE no error, stream taken.
* @retval TRUE error, stream already taken.
*
* @special
*/
void dmaAllocate(stm32_dma_stream_t *dmastp,
stm32_dmaisr_t func, void *param) {
bool_t dmaAllocate(stm32_dma_stream_t *dmastp,
stm32_dmaisr_t func, void *param) {
chDbgCheck(dmastp != NULL, "dmaAllocate");
/* Checks if the stream is already taken.*/
chDbgAssert((dma_streams_mask & dmastp->mask) == 0,
"dmaAllocate(), #1", "already allocated");
if ((dma_streams_mask & dmastp->mask) != 0)
return TRUE;
/* Marks the stream as allocated.*/
dma_isr_redir[dmastp->selfindex].dma_func = func;
@ -444,13 +461,18 @@ void dmaAllocate(stm32_dma_stream_t *dmastp,
dma_streams_mask |= (1 << dmastp->selfindex);
/* Enabling DMA clocks required by the current streams set.*/
if ((dma_streams_mask & 0x000000FF) != 0)
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) {
RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;
if ((dma_streams_mask & 0x0000FF00) != 0)
RCC->AHB1LPENR |= RCC_AHB1LPENR_DMA1LPEN;
}
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) {
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
RCC->AHB1LPENR |= RCC_AHB1LPENR_DMA2LPEN;
}
/* Making sure there are no spurious interrupts flags pending.*/
dmaStreamClearInterrupt();
dmaStreamClearInterrupt(dmastp);
return FALSE;
}
/**
@ -468,6 +490,8 @@ void dmaAllocate(stm32_dma_stream_t *dmastp,
*/
void dmaRelease(stm32_dma_stream_t *dmastp) {
chDbgCheck(dmastp != NULL, "dmaRelease");
/* Check if the streams is not taken.*/
chDbgAssert((dma_streams_mask & dmastp->mask) != 0,
"dmaRelease(), #1", "not allocated");
@ -476,10 +500,14 @@ void dmaRelease(stm32_dma_stream_t *dmastp) {
dma_streams_mask &= ~(1 << dmastp->selfindex);
/* Shutting down clocks that are no more required, if any.*/
if ((dma_streams_mask & 0x000000FF) == 0)
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) {
RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA1EN;
if ((dma_streams_mask & 0x0000FF00) == 0)
RCC->AHB1LPENR &= ~RCC_AHB1LPENR_DMA1LPEN;
}
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) {
RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA2EN;
RCC->AHB1LPENR &= ~RCC_AHB1LPENR_DMA2LPEN;
}
}
#endif /* STM32_DMA_REQUIRED */

150
os/hal/platforms/STM32/DMAv2/stm32_dma.h
View File

@ -20,7 +20,7 @@
/**
* @file DMAv2/stm32_dma.h
* @brief STM32F2xx Enhanced DMA helper driver header.
* @brief Enhanced-DMA helper driver header.
* @note This file requires definitions from the ST STM32F2xx header file
* stm32f2xx.h.
*
@ -39,33 +39,104 @@
* @brief Total number of DMA streams.
* @note This is the total number of streams among all the DMA units.
*/
#define STM32_DMA_STREAMS 16
#define STM32_DMA_STREAMS 16
/**
* @brief Mask of the ISR bits passed to the DMA callback functions.
*/
#define STM32_DMA_ISR_MASK 0x3D
#define STM32_DMA_ISR_MASK 0x3D
/**
* @name DMA streams identifiers
* @{
*/
#define STM32_DMA1_STREAM0 (&_stm32_dma_streams[0])
#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[1])
#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[2])
#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[3])
#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[4])
#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[5])
#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[6])
#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[7])
#define STM32_DMA2_STREAM0 (&_stm32_dma_streams[8])
#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[9])
#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[10])
#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[11])
#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[12])
#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[13])
#define STM32_DMA2_STREAM6 (&_stm32_dma_streams[14])
#define STM32_DMA2_STREAM7 (&_stm32_dma_streams[15])
#define STM32_DMA1_STREAM0 (&_stm32_dma_streams[0])
#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[1])
#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[2])
#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[3])
#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[4])
#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[5])
#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[6])
#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[7])
#define STM32_DMA2_STREAM0 (&_stm32_dma_streams[8])
#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[9])
#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[10])
#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[11])
#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[12])
#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[13])
#define STM32_DMA2_STREAM6 (&_stm32_dma_streams[14])
#define STM32_DMA2_STREAM7 (&_stm32_dma_streams[15])
/** @} */
/**
* @name CR register constants common to all DMA types
*/
#define STM32_DMA_CR_EN DMA_SxCR_EN
#define STM32_DMA_CR_TEIE DMA_SxCR_TEIE
#define STM32_DMA_CR_HTIE DMA_SxCR_HTIE
#define STM32_DMA_CR_TCIE DMA_SxCR_TCIE
#define STM32_DMA_CR_DIR_MASK DMA_SxCR_DIR
#define STM32_DMA_CR_DIR_P2M 0
#define STM32_DMA_CR_DIR_M2P DMA_SxCR_DIR_0
#define STM32_DMA_CR_DIR_M2M DMA_SxCR_DIR_1
#define STM32_DMA_CR_CIRC DMA_SxCR_CIRC
#define STM32_DMA_CR_PINC DMA_SxCR_PINC
#define STM32_DMA_CR_MINC DMA_SxCR_MINC
#define STM32_DMA_CR_PSIZE_MASK DMA_SxCR_PSIZE
#define STM32_DMA_CR_PSIZE_BYTE 0
#define STM32_DMA_CR_PSIZE_HWORD DMA_SxCR_PSIZE_0
#define STM32_DMA_CR_PSIZE_WORD DMA_SxCR_PSIZE_1
#define STM32_DMA_CR_MSIZE_MASK DMA_SxCR_MSIZE
#define STM32_DMA_CR_MSIZE_BYTE 0
#define STM32_DMA_CR_MSIZE_HWORD DMA_SxCR_MSIZE_0
#define STM32_DMA_CR_MSIZE_WORD DMA_SxCR_MSIZE_1
#define STM32_DMA_CR_PL_MASK DMA_SxCR_PL
#define STM32_DMA_CR_PL(n) ((n) << 16)
/** @} */
/**
* @name CR register constants only found in STM32F2xx
*/
#define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE
#define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL
#define STM32_DMA_CR_PINCOS DMA_SxCR_PINCOS
#define STM32_DMA_CR_DBM DMA_SxCR_DBM
#define STM32_DMA_CR_CT DMA_SxCR_CT
#define STM32_DMA_CR_PBURST_MASK DMA_SxCR_PBURST
#define STM32_DMA_CR_PBURST_SINGLE 0
#define STM32_DMA_CR_PBURST_INCR4 DMA_SxCR_PBURST_0
#define STM32_DMA_CR_PBURST_INCR8 DMA_SxCR_PBURST_1
#define STM32_DMA_CR_PBURST_INCR16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1)
#define STM32_DMA_CR_MBURST_MASK DMA_SxCR_MBURST
#define STM32_DMA_CR_MBURST_SINGLE 0
#define STM32_DMA_CR_MBURST_INCR4 DMA_SxCR_MBURST_0
#define STM32_DMA_CR_MBURST_INCR8 DMA_SxCR_MBURST_1
#define STM32_DMA_CR_MBURST_INCR16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1)
#define STM32_DMA_CR_CHSEL_MASK DMA_SxCR_CHSEL
#define STM32_DMA_CR_CHSEL(n) ((n) << 25)
/** @} */
/**
* @name FCR register constants only found in STM32F2xx
*/
#define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE
#define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS
#define STM32_DMA_FCR_DMDIS DMA_SxFCR_DMDIS
#define STM32_DMA_FCR_FTH_MASK DMA_SxFCR_FTH
#define STM32_DMA_FCR_FTH_1Q 0
#define STM32_DMA_FCR_FTH_HALF DMA_SxFCR_FTH_0
#define STM32_DMA_FCR_FTH_3Q DMA_SxFCR_FTH_1
#define STM32_DMA_FCR_FTH_FULL (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1)
/** @} */
/**
* @name Status flags passed to the ISR callbacks
*/
#define STM32_DMA_ISR_FEIF DMA_LISR_FEIF0
#define STM32_DMA_ISR_DMEIF DMA_LISR_DMEIF0
#define STM32_DMA_ISR_TEIF DMA_LISR_TEIF0
#define STM32_DMA_ISR_HTIF DMA_LISR_HTIF0
#define STM32_DMA_ISR_TCIF DMA_LISR_TCIF0
/** @} */
/*===========================================================================*/
@ -89,8 +160,8 @@ typedef struct {
DMA_Stream_TypeDef *stream; /**< @brief Associated DMA stream. */
volatile uint32_t *isr; /**< @brief Associated xISR reg. */
volatile uint32_t *ifcr; /**< @brief Associated xIFCR reg. */
uint32_t ishift; /**< @brief Bits offset in xISR and
xIFCR registers. */
uint32_t ishift; /**< @brief Bits offset in xIFCR
registers. */
} stm32_dma_stream_t;
/**
@ -163,14 +234,25 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] mode1 value to be written in the FCR register
* @param[in] mode2 value to be written in the CR register
* @param[in] mode value to be written in the CR register
*
* @special
*/
#define dmaStreamSetMode(dmastp, mode1, mode2) { \
(dmastp)->stream->FCR = (uint32_t)(mode1); \
(dmastp)->stream->CR = (uint32_t)(mode2); \
#define dmaStreamSetMode(dmastp, mode) { \
(dmastp)->stream->CR = (uint32_t)(mode2); \
}
/**
* @brief Programs the stream FIFO settings.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] mode value to be written in the FCR register
*
* @special
*/
#define dmaStreamSetFIFO(dmastp, mode) { \
(dmastp)->stream->FCR = (uint32_t)(mode); \
}
/**
@ -182,7 +264,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @special
*/
#define dmaStreamEnable(dmachp) { \
(dmastp)->stream->CR |= DMA_SxCR_EN; \
(dmastp)->stream->CR |= STM32_DMA_CR_EN; \
}
/**
@ -194,13 +276,11 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @special
*/
#define dmaStreamDisable(dmastp) { \
(dmastp)->stream->CR &= ~DMA_SxCR_EN; \
(dmastp)->stream->CR &= ~STM32_DMA_CR_EN; \
}
/**
* @brief DMA stream interrupt sources clear.
* @details Sets the appropriate CGIF bit into the IFCR register in order to
* withdraw all the pending interrupt bits from the ISR register.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
@ -208,23 +288,23 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @special
*/
#define dmaStreamClearInterrupt(dmastp) { \
*(dmastp)->stream->ifcr = STM32_DMA_ISR_MASK << (dmastp)->stream->ishift; \
*(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \
}
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined()
extern _stm32_dma_streams[STM32_DMA_STREAMS];
#if !defined(__DOXYGEN__)
extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
#endif
#ifdef __cplusplus
extern "C" {
#endif
void dmaInit(void);
void dmaAllocate(stm32_dma_stream_t *dmastp,
stm32_dmaisr_t func, void *param);
bool_t dmaAllocate(stm32_dma_stream_t *dmastp,
stm32_dmaisr_t func, void *param);
void dmaRelease(stm32_dma_stream_t *dmastp);
#ifdef __cplusplus
}

4
os/hal/src/adc.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_ADC || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/src/can.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_CAN || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/src/gpt.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_GPT || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/src/hal.c
View File

@ -29,6 +29,10 @@
#include "ch.h"
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/src/i2c.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_I2C || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/src/icu.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_ICU || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/src/mac.c
View File

@ -33,6 +33,10 @@
#if HAL_USE_MAC || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/src/mmc_spi.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/src/pal.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_PAL || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/src/pwm.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_PWM || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/src/sdc.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_SDC || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/src/serial.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_SERIAL || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/src/serial_usb.c
View File

@ -33,6 +33,10 @@
#if HAL_USE_SERIAL_USB || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/src/spi.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_SPI || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/src/uart.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_UART || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/src/usb.c
View File

@ -34,6 +34,10 @@
#if HAL_USE_USB || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/templates/adc_lld.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_ADC || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/templates/can_lld.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_CAN || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/templates/gpt_lld.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_GPT || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/templates/hal_lld.c
View File

@ -29,6 +29,10 @@
#include "ch.h"
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/templates/i2c_lld.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_I2C || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/templates/icu_lld.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_ICU || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/templates/mac_lld.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_MAC || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/templates/meta/driver.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_XXX || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/templates/meta/driver_lld.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_XXX || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/templates/pal_lld.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_PAL || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/templates/pwm_lld.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_PWM || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/templates/serial_lld.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_SERIAL || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/templates/spi_lld.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_SPI || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/templates/uart_lld.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_UART || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/

4
os/hal/templates/usb_lld.c
View File

@ -31,6 +31,10 @@
#if HAL_USE_USB || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/