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More headers updated. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10825 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2017-10-15 10:58:26 +00:00
parent 33a3c8f732
commit fe3507eb99
61 changed files with 387897 additions and 256734 deletions
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52
os/common/ext/ST/STM32F3xx/stm32f301x8.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f301x8.h * @file stm32f301x8.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F301x8 Devices Peripheral Access Layer Header File. * @brief CMSIS STM32F301x8 Devices Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -3541,9 +3539,19 @@ typedef struct
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
#endif #endif
#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
#define EXTI_IMR2_IM_Pos (0U) #define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */ #define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#else
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#endif
/******************* Bit definition for EXTI_EMR2 ****************************/ /******************* Bit definition for EXTI_EMR2 ****************************/
#define EXTI_EMR2_MR32_Pos (0U) #define EXTI_EMR2_MR32_Pos (0U)
@ -3562,6 +3570,20 @@ typedef struct
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
#endif #endif
#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#else
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x1U << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#endif
/****************** Bit definition for EXTI_RTSR2 register ********************/ /****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U) #define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */ #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
@ -3811,21 +3833,6 @@ typedef struct
#define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ #define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_WRP2 register ******************/
#define OB_WRP2_WRP2_Pos (0U)
#define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
#define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
#define OB_WRP2_nWRP2_Pos (8U)
#define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
#define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3_Pos (16U)
#define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
#define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3_Pos (24U)
#define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
#define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -5442,9 +5449,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -5494,6 +5501,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register ******************/ /******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */

52
os/common/ext/ST/STM32F3xx/stm32f302x8.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f302x8.h * @file stm32f302x8.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F302x8 Devices Peripheral Access Layer Header File. * @brief CMSIS STM32F302x8 Devices Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -7137,9 +7135,19 @@ typedef struct
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
#endif #endif
#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
#define EXTI_IMR2_IM_Pos (0U) #define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */ #define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#else
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#endif
/******************* Bit definition for EXTI_EMR2 ****************************/ /******************* Bit definition for EXTI_EMR2 ****************************/
#define EXTI_EMR2_MR32_Pos (0U) #define EXTI_EMR2_MR32_Pos (0U)
@ -7158,6 +7166,20 @@ typedef struct
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
#endif #endif
#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#else
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x1U << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#endif
/****************** Bit definition for EXTI_RTSR2 register ********************/ /****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U) #define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */ #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
@ -7407,21 +7429,6 @@ typedef struct
#define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ #define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_WRP2 register ******************/
#define OB_WRP2_WRP2_Pos (0U)
#define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
#define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
#define OB_WRP2_nWRP2_Pos (8U)
#define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
#define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3_Pos (16U)
#define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
#define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3_Pos (24U)
#define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
#define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -9058,9 +9065,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -9110,6 +9117,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register ******************/ /******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */

29
os/common/ext/ST/STM32F3xx/stm32f302xc.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f302xc.h * @file stm32f302xc.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F302xC Devices Peripheral Access Layer Header File. * @brief CMSIS STM32F302xC Devices Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -7343,9 +7341,15 @@ typedef struct
#define EXTI_IMR2_IM34 EXTI_IMR2_MR34 #define EXTI_IMR2_IM34 EXTI_IMR2_MR34
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
#if defined(EXTI_IMR2_MR33)
#define EXTI_IMR2_IM_Pos (0U) #define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */ #define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#else
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#endif
/******************* Bit definition for EXTI_EMR2 ****************************/ /******************* Bit definition for EXTI_EMR2 ****************************/
#define EXTI_EMR2_MR32_Pos (0U) #define EXTI_EMR2_MR32_Pos (0U)
@ -7366,6 +7370,16 @@ typedef struct
#define EXTI_EMR2_EM34 EXTI_EMR2_MR34 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
#if defined(EXTI_EMR2_MR33)
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#else
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#endif
/****************** Bit definition for EXTI_RTSR2 register ********************/ /****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U) #define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */ #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
@ -9295,9 +9309,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -9347,6 +9361,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register ******************/ /******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */

29
os/common/ext/ST/STM32F3xx/stm32f302xe.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f302xe.h * @file stm32f302xe.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F302xE Devices Peripheral Access Layer Header File. * @brief CMSIS STM32F302xE Devices Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -7371,9 +7369,15 @@ typedef struct
#define EXTI_IMR2_IM34 EXTI_IMR2_MR34 #define EXTI_IMR2_IM34 EXTI_IMR2_MR34
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
#if defined(EXTI_IMR2_MR33)
#define EXTI_IMR2_IM_Pos (0U) #define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */ #define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#else
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#endif
/******************* Bit definition for EXTI_EMR2 ****************************/ /******************* Bit definition for EXTI_EMR2 ****************************/
#define EXTI_EMR2_MR32_Pos (0U) #define EXTI_EMR2_MR32_Pos (0U)
@ -7394,6 +7398,16 @@ typedef struct
#define EXTI_EMR2_EM34 EXTI_EMR2_MR34 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
#if defined(EXTI_EMR2_MR33)
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#else
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#endif
/****************** Bit definition for EXTI_RTSR2 register ********************/ /****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U) #define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */ #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
@ -10974,9 +10988,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -11026,6 +11040,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register ******************/ /******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */

58
os/common/ext/ST/STM32F3xx/stm32f303x8.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f303x8.h * @file stm32f303x8.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F303x8 Devices Peripheral Access Layer Header File. * @brief CMSIS STM32F303x8 Devices Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -7151,9 +7149,19 @@ typedef struct
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
#endif #endif
#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
#define EXTI_IMR2_IM_Pos (0U) #define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */ #define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#else
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#endif
/******************* Bit definition for EXTI_EMR2 ****************************/ /******************* Bit definition for EXTI_EMR2 ****************************/
#define EXTI_EMR2_MR32_Pos (0U) #define EXTI_EMR2_MR32_Pos (0U)
@ -7172,6 +7180,20 @@ typedef struct
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
#endif #endif
#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#else
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x1U << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#endif
/****************** Bit definition for EXTI_RTSR2 register ********************/ /****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U) #define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */ #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
@ -7421,21 +7443,6 @@ typedef struct
#define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ #define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_WRP2 register ******************/
#define OB_WRP2_WRP2_Pos (0U)
#define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
#define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
#define OB_WRP2_nWRP2_Pos (8U)
#define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
#define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3_Pos (16U)
#define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
#define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3_Pos (24U)
#define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
#define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -9012,9 +9019,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -9064,6 +9071,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register ******************/ /******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
@ -9605,12 +9617,6 @@ typedef struct
#define SPI_SR_TXE_Pos (1U) #define SPI_SR_TXE_Pos (1U)
#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
#define SPI_SR_CHSIDE_Pos (2U)
#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
#define SPI_SR_UDR_Pos (3U)
#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
#define SPI_SR_CRCERR_Pos (4U) #define SPI_SR_CRCERR_Pos (4U)
#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */

17
os/common/ext/ST/STM32F3xx/stm32f303xc.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f303xc.h * @file stm32f303xc.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F303xC Devices Peripheral Access Layer Header File. * @brief CMSIS STM32F303xC Devices Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -7911,6 +7909,10 @@ typedef struct
#define EXTI_EMR2_EM34 EXTI_EMR2_MR34 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
/****************** Bit definition for EXTI_RTSR2 register ********************/ /****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U) #define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */ #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
@ -9897,9 +9899,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -9949,6 +9951,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register ******************/ /******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */

17
os/common/ext/ST/STM32F3xx/stm32f303xe.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f303xe.h * @file stm32f303xe.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F303xE Devices Peripheral Access Layer Header File. * @brief CMSIS STM32F303xE Devices Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -7917,6 +7915,10 @@ typedef struct
#define EXTI_EMR2_EM34 EXTI_EMR2_MR34 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
/****************** Bit definition for EXTI_RTSR2 register ********************/ /****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U) #define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */ #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
@ -11562,9 +11564,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -11614,6 +11616,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register ******************/ /******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */

37
os/common/ext/ST/STM32F3xx/stm32f318xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f318xx.h * @file stm32f318xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F318xx Devices Peripheral Access Layer Header File. * @brief CMSIS STM32F318xx Devices Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -3540,9 +3538,19 @@ typedef struct
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
#endif #endif
#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
#define EXTI_IMR2_IM_Pos (0U) #define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */ #define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#else
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#endif
/******************* Bit definition for EXTI_EMR2 ****************************/ /******************* Bit definition for EXTI_EMR2 ****************************/
#define EXTI_EMR2_MR32_Pos (0U) #define EXTI_EMR2_MR32_Pos (0U)
@ -3561,6 +3569,20 @@ typedef struct
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
#endif #endif
#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#else
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x1U << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#endif
/****************** Bit definition for EXTI_RTSR2 register ********************/ /****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U) #define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */ #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
@ -5415,9 +5437,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -5467,6 +5489,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register ******************/ /******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */

67
os/common/ext/ST/STM32F3xx/stm32f328xx.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f328xx.h * @file stm32f328xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F328xx Devices Peripheral Access Layer Header File. * @brief CMSIS STM32F328xx Devices Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -7150,9 +7148,19 @@ typedef struct
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
#endif #endif
#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
#define EXTI_IMR2_IM_Pos (0U) #define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */ #define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#else
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#endif
/******************* Bit definition for EXTI_EMR2 ****************************/ /******************* Bit definition for EXTI_EMR2 ****************************/
#define EXTI_EMR2_MR32_Pos (0U) #define EXTI_EMR2_MR32_Pos (0U)
@ -7171,6 +7179,20 @@ typedef struct
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
#endif #endif
#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#else
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x1U << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#endif
/****************** Bit definition for EXTI_RTSR2 register ********************/ /****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U) #define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */ #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
@ -7420,21 +7442,6 @@ typedef struct
#define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ #define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_WRP2 register ******************/
#define OB_WRP2_WRP2_Pos (0U)
#define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
#define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
#define OB_WRP2_nWRP2_Pos (8U)
#define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
#define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3_Pos (16U)
#define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
#define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3_Pos (24U)
#define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
#define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -8985,9 +8992,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -9037,6 +9044,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register ******************/ /******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
@ -9578,12 +9590,6 @@ typedef struct
#define SPI_SR_TXE_Pos (1U) #define SPI_SR_TXE_Pos (1U)
#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
#define SPI_SR_CHSIDE_Pos (2U)
#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
#define SPI_SR_UDR_Pos (3U)
#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
#define SPI_SR_CRCERR_Pos (4U) #define SPI_SR_CRCERR_Pos (4U)
#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
@ -9966,15 +9972,6 @@ typedef struct
#define SYSCFG_CFGR3_ADC2_DMA_RMP SYSCFG_CFGR3_ADC2_DMA_RMP_Msk /*!< ADC2 DMA remap */ #define SYSCFG_CFGR3_ADC2_DMA_RMP SYSCFG_CFGR3_ADC2_DMA_RMP_Msk /*!< ADC2 DMA remap */
#define SYSCFG_CFGR3_ADC2_DMA_RMP_0 (0x1U << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000100 */ #define SYSCFG_CFGR3_ADC2_DMA_RMP_0 (0x1U << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000100 */
#define SYSCFG_CFGR3_ADC2_DMA_RMP_1 (0x2U << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000200 */ #define SYSCFG_CFGR3_ADC2_DMA_RMP_1 (0x2U << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000200 */
#define SYSCFG_CFGR3_TRIGGER_RMP_Pos (16U)
#define SYSCFG_CFGR3_TRIGGER_RMP_Msk (0x3U << SYSCFG_CFGR3_TRIGGER_RMP_Pos) /*!< 0x00030000 */
#define SYSCFG_CFGR3_TRIGGER_RMP SYSCFG_CFGR3_TRIGGER_RMP_Msk /*!< Trigger remap mask */
#define SYSCFG_CFGR3_DAC1_TRG3_RMP_Pos (16U)
#define SYSCFG_CFGR3_DAC1_TRG3_RMP_Msk (0x1U << SYSCFG_CFGR3_DAC1_TRG3_RMP_Pos) /*!< 0x00010000 */
#define SYSCFG_CFGR3_DAC1_TRG3_RMP SYSCFG_CFGR3_DAC1_TRG3_RMP_Msk /*!< DAC1 TRG3 remap */
#define SYSCFG_CFGR3_DAC1_TRG5_RMP_Pos (17U)
#define SYSCFG_CFGR3_DAC1_TRG5_RMP_Msk (0x1U << SYSCFG_CFGR3_DAC1_TRG5_RMP_Pos) /*!< 0x00020000 */
#define SYSCFG_CFGR3_DAC1_TRG5_RMP SYSCFG_CFGR3_DAC1_TRG5_RMP_Msk /*!< DAC1 TRG5 remap */
/******************************************************************************/ /******************************************************************************/
/* */ /* */

58
os/common/ext/ST/STM32F3xx/stm32f334x8.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f334x8.h * @file stm32f334x8.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F334x8 Devices Peripheral Access Layer Header File. * @brief CMSIS STM32F334x8 Devices Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -7339,9 +7337,19 @@ typedef struct
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
#endif #endif
#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#else
#define EXTI_IMR2_IM_Pos (0U) #define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */ #define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
#endif
/******************* Bit definition for EXTI_EMR2 ****************************/ /******************* Bit definition for EXTI_EMR2 ****************************/
#define EXTI_EMR2_MR32_Pos (0U) #define EXTI_EMR2_MR32_Pos (0U)
@ -7360,6 +7368,20 @@ typedef struct
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
#endif #endif
#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#else
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x1U << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
#endif
/****************** Bit definition for EXTI_RTSR2 register ********************/ /****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U) #define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */ #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
@ -7609,21 +7631,6 @@ typedef struct
#define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ #define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_WRP2 register ******************/
#define OB_WRP2_WRP2_Pos (0U)
#define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
#define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
#define OB_WRP2_nWRP2_Pos (8U)
#define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
#define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3_Pos (16U)
#define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
#define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3_Pos (24U)
#define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
#define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -11958,9 +11965,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -12010,6 +12017,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register ******************/ /******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
@ -12551,12 +12563,6 @@ typedef struct
#define SPI_SR_TXE_Pos (1U) #define SPI_SR_TXE_Pos (1U)
#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
#define SPI_SR_CHSIDE_Pos (2U)
#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
#define SPI_SR_UDR_Pos (3U)
#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
#define SPI_SR_CRCERR_Pos (4U) #define SPI_SR_CRCERR_Pos (4U)
#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */

17
os/common/ext/ST/STM32F3xx/stm32f358xx.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f358xx.h * @file stm32f358xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F358xx Devices Peripheral Access Layer Header File. * @brief CMSIS STM32F358xx Devices Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -7863,6 +7861,10 @@ typedef struct
#define EXTI_EMR2_EM34 EXTI_EMR2_MR34 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
/****************** Bit definition for EXTI_RTSR2 register ********************/ /****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U) #define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */ #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
@ -9806,9 +9808,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -9858,6 +9860,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register ******************/ /******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */

13
os/common/ext/ST/STM32F3xx/stm32f373xc.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f373xc.h * @file stm32f373xc.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F373xC Devices Peripheral Access Layer Header File. * @brief CMSIS STM32F373xC Devices Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -8374,9 +8372,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -8426,6 +8424,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register ******************/ /******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */

13
os/common/ext/ST/STM32F3xx/stm32f378xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f378xx.h * @file stm32f378xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F378xx Devices Peripheral Access Layer Header File. * @brief CMSIS STM32F378xx Devices Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -8287,9 +8285,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -8339,6 +8337,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register ******************/ /******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */

17
os/common/ext/ST/STM32F3xx/stm32f398xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f398xx.h * @file stm32f398xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F398xx Devices Peripheral Access Layer Header File. * @brief CMSIS STM32F398xx Devices Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -7867,6 +7865,10 @@ typedef struct
#define EXTI_EMR2_EM34 EXTI_EMR2_MR34 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
/****************** Bit definition for EXTI_RTSR2 register ********************/ /****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U) #define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */ #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
@ -11469,9 +11471,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -11521,6 +11523,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register ******************/ /******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */

6
os/common/ext/ST/STM32F3xx/stm32f3xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f3xx.h * @file stm32f3xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -121,11 +119,11 @@
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.3.1 * @brief CMSIS Device version number V2.3.2
*/ */
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ #define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ #define __STM32F3_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\ #define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\ |(__STM32F3_CMSIS_VERSION_SUB1 << 16)\

2
os/common/ext/ST/STM32F3xx/system_stm32f3xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f3xx.h * @file system_stm32f3xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices. * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention

75
os/common/ext/ST/STM32H7xx/stm32h743xx.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32h743xx.h * @file stm32h743xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.1.0
* @date 21-April-2017 * @date 31-August-2017
* @brief CMSIS STM32H743xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32H743xx Device Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -1846,7 +1846,9 @@ typedef struct
uint32_t Reserved30[2]; /*!< Reserved 030h */ uint32_t Reserved30[2]; /*!< Reserved 030h */
__IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
__IO uint32_t CID; /*!< User ID Register 03Ch */ __IO uint32_t CID; /*!< User ID Register 03Ch */
uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
__IO uint32_t GHWCFG1; /* User HW config1 044h*/
__IO uint32_t GHWCFG2; /* User HW config2 048h*/
__IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
uint32_t Reserved6; /*!< Reserved 050h */ uint32_t Reserved6; /*!< Reserved 050h */
__IO uint32_t GLPMCFG; /*!< LPM Register 054h */ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
@ -1966,11 +1968,14 @@ typedef struct
#define D3_SRAM_BASE ((uint32_t)0x38000000) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */ #define D3_SRAM_BASE ((uint32_t)0x38000000) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */ #define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
#define FLASH_BANK1_BASE ((uint32_t)0x08000000) /*!< Base address of : Flash Bank1 accessible over AXI */ #define FLASH_BANK1_BASE ((uint32_t)0x08000000) /*!< Base address of : Flash Bank1 accessible over AXI */
#define FLASH_BANK2_BASE ((uint32_t)0x08100000) /*!< Base address of : Flash Bank2 accessible over AXI */ #define FLASH_BANK2_BASE ((uint32_t)0x08100000) /*!< Base address of : Flash Bank2 accessible over AXI */
#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
/* Legacy define */
#define FLASH_BASE FLASH_BANK1_BASE
/*!< Peripheral memory map */ /*!< Peripheral memory map */
@ -13681,9 +13686,6 @@ typedef struct
#define PWR_CR3_USB33DEN_Pos (24U) #define PWR_CR3_USB33DEN_Pos (24U)
#define PWR_CR3_USB33DEN_Msk (0x1U << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */ #define PWR_CR3_USB33DEN_Msk (0x1U << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */
#define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */ #define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */
#define PWR_CR3_SDEXTRDY_Pos (16U)
#define PWR_CR3_SDEXTRDY_Msk (0x1U << PWR_CR3_SDEXTRDY_Pos) /*!< 0x00010000 */
#define PWR_CR3_SDEXTRDY PWR_CR3_SDEXTRDY_Msk /*!< Step Down converter External supply ready */
#define PWR_CR3_VBRS_Pos (9U) #define PWR_CR3_VBRS_Pos (9U)
#define PWR_CR3_VBRS_Msk (0x1U << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */ #define PWR_CR3_VBRS_Msk (0x1U << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */
#define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */ #define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */
@ -14713,9 +14715,6 @@ typedef struct
#define RCC_AHB3ENR_JPGDECEN_Pos (5U) #define RCC_AHB3ENR_JPGDECEN_Pos (5U)
#define RCC_AHB3ENR_JPGDECEN_Msk (0x1U << RCC_AHB3ENR_JPGDECEN_Pos) /*!< 0x00000020 */ #define RCC_AHB3ENR_JPGDECEN_Msk (0x1U << RCC_AHB3ENR_JPGDECEN_Pos) /*!< 0x00000020 */
#define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk #define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk
#define RCC_AHB3ENR_FLASHEN_Pos (8U)
#define RCC_AHB3ENR_FLASHEN_Msk (0x1U << RCC_AHB3ENR_FLASHEN_Pos) /*!< 0x00000100 */
#define RCC_AHB3ENR_FLASHEN RCC_AHB3ENR_FLASHEN_Msk
#define RCC_AHB3ENR_FMCEN_Pos (12U) #define RCC_AHB3ENR_FMCEN_Pos (12U)
#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00001000 */ #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00001000 */
#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
@ -14774,8 +14773,8 @@ typedef struct
#define RCC_AHB2ENR_SDMMC2EN_Pos (9U) #define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1U << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */ #define RCC_AHB2ENR_SDMMC2EN_Msk (0x1U << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */
#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk #define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
#define RCC_AHB2ENR_D2SRAM1EN_Pos (30U) #define RCC_AHB2ENR_D2SRAM1EN_Pos (29U)
#define RCC_AHB2ENR_D2SRAM1EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM1EN_Pos) /*!< 0x40000000 */ #define RCC_AHB2ENR_D2SRAM1EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM1EN_Pos) /*!< 0x20000000 */
#define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_D2SRAM1EN_Msk #define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_D2SRAM1EN_Msk
#define RCC_AHB2ENR_D2SRAM2EN_Pos (30U) #define RCC_AHB2ENR_D2SRAM2EN_Pos (30U)
#define RCC_AHB2ENR_D2SRAM2EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM2EN_Pos) /*!< 0x40000000 */ #define RCC_AHB2ENR_D2SRAM2EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM2EN_Pos) /*!< 0x40000000 */
@ -15699,7 +15698,7 @@ typedef struct
#define RCC_APB4LPENR_SAI4LPEN_Pos (21U) #define RCC_APB4LPENR_SAI4LPEN_Pos (21U)
#define RCC_APB4LPENR_SAI4LPEN_Msk (0x1U << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */ #define RCC_APB4LPENR_SAI4LPEN_Msk (0x1U << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */
#define RCC_APB4LPENR_SAI4LPEN RCC_APB4LPENR_SAI4LPEN_Msk #define RCC_APB4LPENR_SAI4LPEN RCC_APB4LPENR_SAI4LPEN_Msk
/******************** Bit definition for RCC_RSR register *******************/ /******************** Bit definition for RCC_RSR register *******************/
#define RCC_RSR_RMVF_Pos (16U) #define RCC_RSR_RMVF_Pos (16U)
#define RCC_RSR_RMVF_Msk (0x1U << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */ #define RCC_RSR_RMVF_Msk (0x1U << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */
@ -23862,49 +23861,6 @@ typedef struct
#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_CHNUM_Pos (0U)
#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos (4U)
#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
#define USB_OTG_DPID_Pos (15U)
#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_PKTSTS_Pos (17U)
#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
#define USB_OTG_EPNUM_Pos (0U)
#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_FRMNUM_Pos (21U)
#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/ /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
@ -24584,6 +24540,9 @@ typedef struct
#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< OUT Status Phase Received interrupt */
#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
@ -25322,7 +25281,7 @@ typedef struct
#define FLASH_SIZE 0x200000 /* 2MB */ #define FLASH_SIZE 0x200000 /* 2MB */
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1MB */ #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1MB */
#define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB */ #define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB */

77
os/common/ext/ST/STM32H7xx/stm32h753xx.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32h753xx.h * @file stm32h753xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.1.0
* @date 21-April-2017 * @date 31-August-2017
* @brief CMSIS STM32H753xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32H753xx Device Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -913,7 +913,7 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
typedef struct typedef struct
{ {
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
__IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
__IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
__IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
@ -1916,7 +1916,9 @@ typedef struct
uint32_t Reserved30[2]; /*!< Reserved 030h */ uint32_t Reserved30[2]; /*!< Reserved 030h */
__IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
__IO uint32_t CID; /*!< User ID Register 03Ch */ __IO uint32_t CID; /*!< User ID Register 03Ch */
uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
__IO uint32_t GHWCFG1; /* User HW config1 044h*/
__IO uint32_t GHWCFG2; /* User HW config2 048h*/
__IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
uint32_t Reserved6; /*!< Reserved 050h */ uint32_t Reserved6; /*!< Reserved 050h */
__IO uint32_t GLPMCFG; /*!< LPM Register 054h */ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
@ -2036,11 +2038,14 @@ typedef struct
#define D3_SRAM_BASE ((uint32_t)0x38000000) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */ #define D3_SRAM_BASE ((uint32_t)0x38000000) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */ #define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
#define FLASH_BANK1_BASE ((uint32_t)0x08000000) /*!< Base address of : Flash Bank1 accessible over AXI */ #define FLASH_BANK1_BASE ((uint32_t)0x08000000) /*!< Base address of : Flash Bank1 accessible over AXI */
#define FLASH_BANK2_BASE ((uint32_t)0x08100000) /*!< Base address of : Flash Bank2 accessible over AXI */ #define FLASH_BANK2_BASE ((uint32_t)0x08100000) /*!< Base address of : Flash Bank2 accessible over AXI */
#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
/* Legacy define */
#define FLASH_BASE FLASH_BANK1_BASE
/*!< Peripheral memory map */ /*!< Peripheral memory map */
@ -2624,6 +2629,7 @@ typedef struct
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE #define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE #define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
/** /**
* @} * @}
*/ */
@ -4209,6 +4215,7 @@ typedef struct
#define VREFBUF_CCR_TRIM_Msk (0x3FU << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */ #define VREFBUF_CCR_TRIM_Msk (0x3FU << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */ #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
/* Flexible Datarate Controller Area Network */ /* Flexible Datarate Controller Area Network */
@ -6210,6 +6217,7 @@ typedef struct
#define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */ #define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */ #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
/* DCMI */ /* DCMI */
@ -10403,7 +10411,6 @@ typedef struct
#define FLASH_BOOT_ADD0 0x0000FFFFU #define FLASH_BOOT_ADD0 0x0000FFFFU
#define FLASH_BOOT_ADD1 0xFFFF0000U #define FLASH_BOOT_ADD1 0xFFFF0000U
/******************* Bits definition for FLASH_CRCCR register ********************/ /******************* Bits definition for FLASH_CRCCR register ********************/
#define FLASH_CRCCR_CRC_SECT 0x00000007U #define FLASH_CRCCR_CRC_SECT 0x00000007U
#define FLASH_CRCCR_ALL_BANK 0x00000080U #define FLASH_CRCCR_ALL_BANK 0x00000080U
@ -13946,9 +13953,6 @@ typedef struct
#define PWR_CR3_USB33DEN_Pos (24U) #define PWR_CR3_USB33DEN_Pos (24U)
#define PWR_CR3_USB33DEN_Msk (0x1U << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */ #define PWR_CR3_USB33DEN_Msk (0x1U << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */
#define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */ #define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */
#define PWR_CR3_SDEXTRDY_Pos (16U)
#define PWR_CR3_SDEXTRDY_Msk (0x1U << PWR_CR3_SDEXTRDY_Pos) /*!< 0x00010000 */
#define PWR_CR3_SDEXTRDY PWR_CR3_SDEXTRDY_Msk /*!< Step Down converter External supply ready */
#define PWR_CR3_VBRS_Pos (9U) #define PWR_CR3_VBRS_Pos (9U)
#define PWR_CR3_VBRS_Msk (0x1U << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */ #define PWR_CR3_VBRS_Msk (0x1U << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */
#define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */ #define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */
@ -14978,9 +14982,6 @@ typedef struct
#define RCC_AHB3ENR_JPGDECEN_Pos (5U) #define RCC_AHB3ENR_JPGDECEN_Pos (5U)
#define RCC_AHB3ENR_JPGDECEN_Msk (0x1U << RCC_AHB3ENR_JPGDECEN_Pos) /*!< 0x00000020 */ #define RCC_AHB3ENR_JPGDECEN_Msk (0x1U << RCC_AHB3ENR_JPGDECEN_Pos) /*!< 0x00000020 */
#define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk #define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk
#define RCC_AHB3ENR_FLASHEN_Pos (8U)
#define RCC_AHB3ENR_FLASHEN_Msk (0x1U << RCC_AHB3ENR_FLASHEN_Pos) /*!< 0x00000100 */
#define RCC_AHB3ENR_FLASHEN RCC_AHB3ENR_FLASHEN_Msk
#define RCC_AHB3ENR_FMCEN_Pos (12U) #define RCC_AHB3ENR_FMCEN_Pos (12U)
#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00001000 */ #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00001000 */
#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
@ -15039,8 +15040,8 @@ typedef struct
#define RCC_AHB2ENR_SDMMC2EN_Pos (9U) #define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1U << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */ #define RCC_AHB2ENR_SDMMC2EN_Msk (0x1U << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */
#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk #define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
#define RCC_AHB2ENR_D2SRAM1EN_Pos (30U) #define RCC_AHB2ENR_D2SRAM1EN_Pos (29U)
#define RCC_AHB2ENR_D2SRAM1EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM1EN_Pos) /*!< 0x40000000 */ #define RCC_AHB2ENR_D2SRAM1EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM1EN_Pos) /*!< 0x20000000 */
#define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_D2SRAM1EN_Msk #define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_D2SRAM1EN_Msk
#define RCC_AHB2ENR_D2SRAM2EN_Pos (30U) #define RCC_AHB2ENR_D2SRAM2EN_Pos (30U)
#define RCC_AHB2ENR_D2SRAM2EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM2EN_Pos) /*!< 0x40000000 */ #define RCC_AHB2ENR_D2SRAM2EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM2EN_Pos) /*!< 0x40000000 */
@ -24127,49 +24128,6 @@ typedef struct
#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_CHNUM_Pos (0U)
#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos (4U)
#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
#define USB_OTG_DPID_Pos (15U)
#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_PKTSTS_Pos (17U)
#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
#define USB_OTG_EPNUM_Pos (0U)
#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_FRMNUM_Pos (21U)
#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/ /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
@ -24849,6 +24807,9 @@ typedef struct
#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< OUT Status Phase Received interrupt */
#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */

16
os/common/ext/ST/STM32H7xx/stm32h7xx.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32h7xx.h * @file stm32h7xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.1.0
* @date 21-April-2017 * @date 31-August-2017
* @brief CMSIS STM32H7xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32H7xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -94,16 +94,16 @@
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V1.0.0 * @brief CMSIS Device version number V1.1.0
*/ */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ #define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|(__CMSIS_DEVICE_HAL_VERSION_RC)) |(__CMSIS_DEVICE_HAL_VERSION_RC))
/** /**
* @} * @}
@ -177,7 +177,7 @@ typedef enum
*/ */
#if defined (USE_HAL_DRIVER) #if defined (USE_HAL_DRIVER)
#include "stm32h7xx_hal_conf.h" #include "stm32h7xx_hal.h"
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */

4
os/common/ext/ST/STM32H7xx/system_stm32h7xx.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file system_stm32h7xx.h * @file system_stm32h7xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.1.0
* @date 21-April-2017 * @date 31-August-2017
* @brief CMSIS Cortex-Mx Device System Source File for STM32H7xx devices. * @brief CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention

2
os/common/ext/ST/STM32L0xx/stm32l011xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32l011xx.h * @file stm32l011xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l011xx devices. * definitions and memory mapping for stm32l011xx devices.

2
os/common/ext/ST/STM32L0xx/stm32l021xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32l021xx.h * @file stm32l021xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l021xx devices. * definitions and memory mapping for stm32l021xx devices.

2
os/common/ext/ST/STM32L0xx/stm32l031xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32l031xx.h * @file stm32l031xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l031xx devices. * definitions and memory mapping for stm32l031xx devices.

2
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32l041xx.h * @file stm32l041xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l041xx devices. * definitions and memory mapping for stm32l041xx devices.

2
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32l051xx.h * @file stm32l051xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l051xx devices. * definitions and memory mapping for stm32l051xx devices.

2
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32l052xx.h * @file stm32l052xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l052xx devices. * definitions and memory mapping for stm32l052xx devices.

2
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****************************************************************************** ******************************************************************************
* @file stm32l053xx.h * @file stm32l053xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l053xx devices. * definitions and memory mapping for stm32l053xx devices.

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****************************************************************************** ******************************************************************************
* @file stm32l061xx.h * @file stm32l061xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l061xx devices. * definitions and memory mapping for stm32l061xx devices.

2
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****************************************************************************** ******************************************************************************
* @file stm32l062xx.h * @file stm32l062xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l062xx devices. * definitions and memory mapping for stm32l062xx devices.

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****************************************************************************** ******************************************************************************
* @file stm32l063xx.h * @file stm32l063xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l063xx devices. * definitions and memory mapping for stm32l063xx devices.

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****************************************************************************** ******************************************************************************
* @file stm32l071xx.h * @file stm32l071xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l071xx devices. * definitions and memory mapping for stm32l071xx devices.

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****************************************************************************** ******************************************************************************
* @file stm32l072xx.h * @file stm32l072xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l072xx devices. * definitions and memory mapping for stm32l072xx devices.

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****************************************************************************** ******************************************************************************
* @file stm32l073xx.h * @file stm32l073xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l073xx devices. * definitions and memory mapping for stm32l073xx devices.

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****************************************************************************** ******************************************************************************
* @file stm32l081xx.h * @file stm32l081xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l081xx devices. * definitions and memory mapping for stm32l081xx devices.

2
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****************************************************************************** ******************************************************************************
* @file stm32l082xx.h * @file stm32l082xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l082xx devices. * definitions and memory mapping for stm32l082xx devices.

2
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****************************************************************************** ******************************************************************************
* @file stm32l083xx.h * @file stm32l083xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l083xx devices. * definitions and memory mapping for stm32l083xx devices.

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****************************************************************************** ******************************************************************************
* @file stm32l0xx.h * @file stm32l0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices. * definitions and memory mapping for STM32L0xx devices.
@ -118,7 +116,7 @@
*/ */
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ #define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ #define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\ #define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\ |(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\

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****************************************************************************** ******************************************************************************
* @file system_stm32l0xx.h * @file system_stm32l0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
****************************************************************************** ******************************************************************************
* @attention * @attention

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/** /**
****************************************************************************** ******************************************************************************
* @file stm32l4xx.h * @file stm32l4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.3.1 * @brief CMSIS STM32L4xx Device Peripheral Access Layer Header File.
* @date 21-April-2017 *
* @brief CMSIS STM32L4xx Device Peripheral Access Layer Header File. * The file is the unique include file that the application programmer
* * is using in the C source code, usually in main.c. This file contains:
* The file is the unique include file that the application programmer * - Configuration section that allows to select:
* is using in the C source code, usually in main.c. This file contains: * - The STM32L4xx device used in the target application
* - Configuration section that allows to select: * - To use or not the peripheral’s drivers in application code(i.e.
* - The STM32L4xx device used in the target application * code will be based on direct access to peripheral’s registers
* - To use or not the peripheral’s drivers in application code(i.e. * rather than drivers API), this option is controlled by
* code will be based on direct access to peripheral’s registers * "#define USE_HAL_DRIVER"
* rather than drivers API), this option is controlled by *
* "#define USE_HAL_DRIVER" ******************************************************************************
* * @attention
****************************************************************************** *
* @attention * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* *
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2> * Redistribution and use in source and binary forms, with or without modification,
* * are permitted provided that the following conditions are met:
* Redistribution and use in source and binary forms, with or without modification, * 1. Redistributions of source code must retain the above copyright notice,
* are permitted provided that the following conditions are met: * this list of conditions and the following disclaimer.
* 1. Redistributions of source code must retain the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer in the documentation
* 2. Redistributions in binary form must reproduce the above copyright notice, * and/or other materials provided with the distribution.
* this list of conditions and the following disclaimer in the documentation * 3. Neither the name of STMicroelectronics nor the names of its contributors
* and/or other materials provided with the distribution. * may be used to endorse or promote products derived from this software
* 3. Neither the name of STMicroelectronics nor the names of its contributors * without specific prior written permission.
* may be used to endorse or promote products derived from this software *
* without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE *
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************
* */
******************************************************************************
*/ /** @addtogroup CMSIS
* @{
/** @addtogroup CMSIS */
* @{
*/ /** @addtogroup stm32l4xx
* @{
/** @addtogroup stm32l4xx */
* @{
*/ #ifndef __STM32L4xx_H
#define __STM32L4xx_H
#ifndef __STM32L4xx_H
#define __STM32L4xx_H #ifdef __cplusplus
extern "C" {
#ifdef __cplusplus #endif /* __cplusplus */
extern "C" {
#endif /* __cplusplus */ /** @addtogroup Library_configuration_section
* @{
/** @addtogroup Library_configuration_section */
* @{
*/ /**
* @brief STM32 Family
/** */
* @brief STM32 Family #if !defined (STM32L4)
*/ #define STM32L4
#if !defined (STM32L4) #endif /* STM32L4 */
#define STM32L4
#endif /* STM32L4 */ /* Uncomment the line below according to the target STM32L4 device used in your
application
/* Uncomment the line below according to the target STM32L4 device used in your */
application
*/ #if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
!defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
!defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ !defined (STM32L496xx) && !defined (STM32L4A6xx) && \
!defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx)
!defined (STM32L496xx) && !defined (STM32L4A6xx) /* #define STM32L431xx */ /*!< STM32L431xx Devices */
/* #define STM32L431xx */ /*!< STM32L431xx Devices */ /* #define STM32L432xx */ /*!< STM32L432xx Devices */
/* #define STM32L432xx */ /*!< STM32L432xx Devices */ /* #define STM32L433xx */ /*!< STM32L433xx Devices */
/* #define STM32L433xx */ /*!< STM32L433xx Devices */ /* #define STM32L442xx */ /*!< STM32L442xx Devices */
/* #define STM32L442xx */ /*!< STM32L442xx Devices */ /* #define STM32L443xx */ /*!< STM32L443xx Devices */
/* #define STM32L443xx */ /*!< STM32L443xx Devices */ /* #define STM32L451xx */ /*!< STM32L451xx Devices */
/* #define STM32L451xx */ /*!< STM32L451xx Devices */ /* #define STM32L452xx */ /*!< STM32L452xx Devices */
/* #define STM32L452xx */ /*!< STM32L452xx Devices */ /* #define STM32L462xx */ /*!< STM32L462xx Devices */
/* #define STM32L462xx */ /*!< STM32L462xx Devices */ /* #define STM32L471xx */ /*!< STM32L471xx Devices */
/* #define STM32L471xx */ /*!< STM32L471xx Devices */ /* #define STM32L475xx */ /*!< STM32L475xx Devices */
/* #define STM32L475xx */ /*!< STM32L475xx Devices */ /* #define STM32L476xx */ /*!< STM32L476xx Devices */
/* #define STM32L476xx */ /*!< STM32L476xx Devices */ /* #define STM32L485xx */ /*!< STM32L485xx Devices */
/* #define STM32L485xx */ /*!< STM32L485xx Devices */ /* #define STM32L486xx */ /*!< STM32L486xx Devices */
/* #define STM32L486xx */ /*!< STM32L486xx Devices */ /* #define STM32L496xx */ /*!< STM32L496xx Devices */
/* #define STM32L496xx */ /*!< STM32L496xx Devices */ /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */
/* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ /* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */
#endif /* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */
/* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */
/* Tip: To avoid modifying this file each time you need to switch between these /* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */
devices, you can define the device in your toolchain compiler preprocessor. /* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */
*/ /* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */
#if !defined (USE_HAL_DRIVER) #endif
/**
* @brief Comment the line below if you will not use the peripherals drivers. /* Tip: To avoid modifying this file each time you need to switch between these
In this case, these drivers will not be included and the application code will devices, you can define the device in your toolchain compiler preprocessor.
be based on direct access to peripherals registers */
*/ #if !defined (USE_HAL_DRIVER)
/*#define USE_HAL_DRIVER */ /**
#endif /* USE_HAL_DRIVER */ * @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
/** be based on direct access to peripherals registers
* @brief CMSIS Device version number V1.3.1 */
*/ /*#define USE_HAL_DRIVER */
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ #endif /* USE_HAL_DRIVER */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ /**
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ * @brief CMSIS Device version number $VERSION$
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ */
|(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ #define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
|(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ #define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
|(__STM32L4_CMSIS_VERSION_RC)) #define __STM32L4_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
/** #define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
* @} |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
*/ |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L4_CMSIS_VERSION_RC))
/** @addtogroup Device_Included
* @{ /**
*/ * @}
*/
#if defined(STM32L431xx)
#include "stm32l431xx.h" /** @addtogroup Device_Included
#elif defined(STM32L432xx) * @{
#include "stm32l432xx.h" */
#elif defined(STM32L433xx)
#include "stm32l433xx.h" #if defined(STM32L431xx)
#elif defined(STM32L442xx) #include "stm32l431xx.h"
#include "stm32l442xx.h" #elif defined(STM32L432xx)
#elif defined(STM32L443xx) #include "stm32l432xx.h"
#include "stm32l443xx.h" #elif defined(STM32L433xx)
#elif defined(STM32L451xx) #include "stm32l433xx.h"
#include "stm32l451xx.h" #elif defined(STM32L442xx)
#elif defined(STM32L452xx) #include "stm32l442xx.h"
#include "stm32l452xx.h" #elif defined(STM32L443xx)
#elif defined(STM32L462xx) #include "stm32l443xx.h"
#include "stm32l462xx.h" #elif defined(STM32L451xx)
#elif defined(STM32L471xx) #include "stm32l451xx.h"
#include "stm32l471xx.h" #elif defined(STM32L452xx)
#elif defined(STM32L475xx) #include "stm32l452xx.h"
#include "stm32l475xx.h" #elif defined(STM32L462xx)
#elif defined(STM32L476xx) #include "stm32l462xx.h"
#include "stm32l476xx.h" #elif defined(STM32L471xx)
#elif defined(STM32L485xx) #include "stm32l471xx.h"
#include "stm32l485xx.h" #elif defined(STM32L475xx)
#elif defined(STM32L486xx) #include "stm32l475xx.h"
#include "stm32l486xx.h" #elif defined(STM32L476xx)
#elif defined(STM32L496xx) #include "stm32l476xx.h"
#include "stm32l496xx.h" #elif defined(STM32L485xx)
#elif defined(STM32L4A6xx) #include "stm32l485xx.h"
#include "stm32l4a6xx.h" #elif defined(STM32L486xx)
#else #include "stm32l486xx.h"
#error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" #elif defined(STM32L496xx)
#endif #include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
/** #include "stm32l4a6xx.h"
* @} #elif defined(STM32L4R5xx)
*/ #include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
/** @addtogroup Exported_types #include "stm32l4r7xx.h"
* @{ #elif defined(STM32L4R9xx)
*/ #include "stm32l4r9xx.h"
typedef enum #elif defined(STM32L4S5xx)
{ #include "stm32l4s5xx.h"
RESET = 0, #elif defined(STM32L4S7xx)
SET = !RESET #include "stm32l4s7xx.h"
} FlagStatus, ITStatus; #elif defined(STM32L4S9xx)
#include "stm32l4s9xx.h"
typedef enum #else
{ #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
DISABLE = 0, #endif
ENABLE = !DISABLE
} FunctionalState; /**
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) * @}
*/
typedef enum
{ /** @addtogroup Exported_types
ERROR = 0, * @{
SUCCESS = !ERROR */
} ErrorStatus; typedef enum
{
/** RESET = 0,
* @} SET = !RESET
*/ } FlagStatus, ITStatus;
typedef enum
/** @addtogroup Exported_macros {
* @{ DISABLE = 0,
*/ ENABLE = !DISABLE
#define SET_BIT(REG, BIT) ((REG) |= (BIT)) } FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
typedef enum
#define READ_BIT(REG, BIT) ((REG) & (BIT)) {
ERROR = 0,
#define CLEAR_REG(REG) ((REG) = (0x0)) SUCCESS = !ERROR
} ErrorStatus;
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
/**
#define READ_REG(REG) ((REG)) * @}
*/
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) /** @addtogroup Exported_macros
* @{
*/
/** #define SET_BIT(REG, BIT) ((REG) |= (BIT))
* @}
*/ #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#if defined (USE_HAL_DRIVER) #define READ_BIT(REG, BIT) ((REG) & (BIT))
#include "stm32l4xx_hal.h"
#endif /* USE_HAL_DRIVER */ #define CLEAR_REG(REG) ((REG) = (0x0))
#ifdef __cplusplus #define WRITE_REG(REG, VAL) ((REG) = (VAL))
}
#endif /* __cplusplus */ #define READ_REG(REG) ((REG))
#endif /* __STM32L4xx_H */ #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
/**
* @} #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
*/
/** /**
* @} * @}
*/ */
#if defined (USE_HAL_DRIVER)
#include "stm32l4xx_hal.h"
#endif /* USE_HAL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32L4xx_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

248
os/common/ext/ST/STM32L4xx/system_stm32l4xx.h
View File

@ -1,125 +1,123 @@
/** /**
****************************************************************************** ******************************************************************************
* @file system_stm32l4xx.h * @file system_stm32l4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.3.1 * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
* @date 21-April-2017 ******************************************************************************
* @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. * @attention
****************************************************************************** *
* @attention * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* *
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2> * Redistribution and use in source and binary forms, with or without modification,
* * are permitted provided that the following conditions are met:
* Redistribution and use in source and binary forms, with or without modification, * 1. Redistributions of source code must retain the above copyright notice,
* are permitted provided that the following conditions are met: * this list of conditions and the following disclaimer.
* 1. Redistributions of source code must retain the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer in the documentation
* 2. Redistributions in binary form must reproduce the above copyright notice, * and/or other materials provided with the distribution.
* this list of conditions and the following disclaimer in the documentation * 3. Neither the name of STMicroelectronics nor the names of its contributors
* and/or other materials provided with the distribution. * may be used to endorse or promote products derived from this software
* 3. Neither the name of STMicroelectronics nor the names of its contributors * without specific prior written permission.
* may be used to endorse or promote products derived from this software *
* without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE *
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************
* */
******************************************************************************
*/ /** @addtogroup CMSIS
* @{
/** @addtogroup CMSIS */
* @{
*/ /** @addtogroup stm32l4xx_system
* @{
/** @addtogroup stm32l4xx_system */
* @{
*/ /**
* @brief Define to prevent recursive inclusion
/** */
* @brief Define to prevent recursive inclusion #ifndef __SYSTEM_STM32L4XX_H
*/ #define __SYSTEM_STM32L4XX_H
#ifndef __SYSTEM_STM32L4XX_H
#define __SYSTEM_STM32L4XX_H #ifdef __cplusplus
extern "C" {
#ifdef __cplusplus #endif
extern "C" {
#endif /** @addtogroup STM32L4xx_System_Includes
* @{
/** @addtogroup STM32L4xx_System_Includes */
* @{
*/ /**
* @}
/** */
* @}
*/
/** @addtogroup STM32L4xx_System_Exported_Variables
* @{
/** @addtogroup STM32L4xx_System_Exported_Variables */
* @{ /* The SystemCoreClock variable is updated in three ways:
*/ 1) by calling CMSIS function SystemCoreClockUpdate()
/* The SystemCoreClock variable is updated in three ways: 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
1) by calling CMSIS function SystemCoreClockUpdate() 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
2) by calling HAL API function HAL_RCC_GetSysClockFreq() Note: If you use this function to configure the system clock; then there
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency is no need to call the 2 first functions listed above, since SystemCoreClock
Note: If you use this function to configure the system clock; then there variable is updated automatically.
is no need to call the 2 first functions listed above, since SystemCoreClock */
variable is updated automatically. extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ /**
* @}
/** */
* @}
*/ /** @addtogroup STM32L4xx_System_Exported_Constants
* @{
/** @addtogroup STM32L4xx_System_Exported_Constants */
* @{
*/ /**
* @}
/** */
* @}
*/ /** @addtogroup STM32L4xx_System_Exported_Macros
* @{
/** @addtogroup STM32L4xx_System_Exported_Macros */
* @{
*/ /**
* @}
/** */
* @}
*/ /** @addtogroup STM32L4xx_System_Exported_Functions
* @{
/** @addtogroup STM32L4xx_System_Exported_Functions */
* @{
*/ extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
extern void SystemInit(void); /**
extern void SystemCoreClockUpdate(void); * @}
/** */
* @}
*/ #ifdef __cplusplus
}
#ifdef __cplusplus #endif
}
#endif #endif /*__SYSTEM_STM32L4XX_H */
#endif /*__SYSTEM_STM32L4XX_H */ /**
* @}
/** */
* @}
*/ /**
* @}
/** */
* @} /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/