More headers updated.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10825 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio
parent
33a3c8f732
commit
fe3507eb99
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@ -2,8 +2,6 @@
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******************************************************************************
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* @file stm32f301x8.h
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* @author MCD Application Team
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* @version V2.3.1
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* @date 16-December-2016
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* @brief CMSIS STM32F301x8 Devices Peripheral Access Layer Header File.
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*
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* This file contains:
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@ -3541,9 +3539,19 @@ typedef struct
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#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
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#endif
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#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
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#define EXTI_IMR2_IM_Pos (0U)
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#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
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#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
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#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
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#define EXTI_IMR2_IM_Pos (0U)
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#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
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#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
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#else
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#define EXTI_IMR2_IM_Pos (0U)
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#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
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#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
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#endif
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/******************* Bit definition for EXTI_EMR2 ****************************/
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#define EXTI_EMR2_MR32_Pos (0U)
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@ -3562,6 +3570,20 @@ typedef struct
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#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
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#endif
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#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
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#define EXTI_EMR2_EM_Pos (0U)
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#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
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#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
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#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
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#define EXTI_EMR2_EM_Pos (0U)
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#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
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#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
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#else
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#define EXTI_EMR2_EM_Pos (0U)
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#define EXTI_EMR2_EM_Msk (0x1U << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */
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#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
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#endif
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/****************** Bit definition for EXTI_RTSR2 register ********************/
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#define EXTI_RTSR2_TR32_Pos (0U)
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#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
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@ -3811,21 +3833,6 @@ typedef struct
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#define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
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#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
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/****************** Bit definition for FLASH_WRP2 register ******************/
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#define OB_WRP2_WRP2_Pos (0U)
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#define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
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#define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
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#define OB_WRP2_nWRP2_Pos (8U)
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#define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
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#define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
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/****************** Bit definition for FLASH_WRP3 register ******************/
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#define OB_WRP3_WRP3_Pos (16U)
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#define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
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#define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
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#define OB_WRP3_nWRP3_Pos (24U)
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#define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
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#define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
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/******************************************************************************/
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/* */
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@ -5442,9 +5449,9 @@ typedef struct
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#define RTC_CR_COSEL_Pos (19U)
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#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
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#define RTC_CR_COSEL RTC_CR_COSEL_Msk
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#define RTC_CR_BCK_Pos (18U)
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#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
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#define RTC_CR_BCK RTC_CR_BCK_Msk
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#define RTC_CR_BKP_Pos (18U)
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#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
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#define RTC_CR_BKP RTC_CR_BKP_Msk
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#define RTC_CR_SUB1H_Pos (17U)
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#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
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#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
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@ -5494,6 +5501,11 @@ typedef struct
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#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
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#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
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/* Legacy defines */
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#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
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#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
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#define RTC_CR_BCK RTC_CR_BKP
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/******************** Bits definition for RTC_ISR register ******************/
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#define RTC_ISR_RECALPF_Pos (16U)
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#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
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@ -2,8 +2,6 @@
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******************************************************************************
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* @file stm32f302x8.h
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* @author MCD Application Team
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* @version V2.3.1
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* @date 16-December-2016
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* @brief CMSIS STM32F302x8 Devices Peripheral Access Layer Header File.
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*
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* This file contains:
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@ -7137,9 +7135,19 @@ typedef struct
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#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
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#endif
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#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
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#define EXTI_IMR2_IM_Pos (0U)
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#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
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#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
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#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
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#define EXTI_IMR2_IM_Pos (0U)
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#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
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#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
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#else
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#define EXTI_IMR2_IM_Pos (0U)
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#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
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#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
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#endif
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/******************* Bit definition for EXTI_EMR2 ****************************/
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#define EXTI_EMR2_MR32_Pos (0U)
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@ -7158,6 +7166,20 @@ typedef struct
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#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
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#endif
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#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
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#define EXTI_EMR2_EM_Pos (0U)
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#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
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#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
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#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
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#define EXTI_EMR2_EM_Pos (0U)
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#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
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#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
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#else
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#define EXTI_EMR2_EM_Pos (0U)
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#define EXTI_EMR2_EM_Msk (0x1U << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */
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#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
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#endif
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/****************** Bit definition for EXTI_RTSR2 register ********************/
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#define EXTI_RTSR2_TR32_Pos (0U)
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#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
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@ -7407,21 +7429,6 @@ typedef struct
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#define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
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#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
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/****************** Bit definition for FLASH_WRP2 register ******************/
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#define OB_WRP2_WRP2_Pos (0U)
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#define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
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#define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
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#define OB_WRP2_nWRP2_Pos (8U)
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#define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
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#define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
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/****************** Bit definition for FLASH_WRP3 register ******************/
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#define OB_WRP3_WRP3_Pos (16U)
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#define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
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#define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
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#define OB_WRP3_nWRP3_Pos (24U)
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#define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
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#define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
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/******************************************************************************/
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/* */
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@ -9058,9 +9065,9 @@ typedef struct
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#define RTC_CR_COSEL_Pos (19U)
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#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
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#define RTC_CR_COSEL RTC_CR_COSEL_Msk
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#define RTC_CR_BCK_Pos (18U)
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#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
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#define RTC_CR_BCK RTC_CR_BCK_Msk
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#define RTC_CR_BKP_Pos (18U)
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#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
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#define RTC_CR_BKP RTC_CR_BKP_Msk
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#define RTC_CR_SUB1H_Pos (17U)
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#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
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#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
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@ -9110,6 +9117,11 @@ typedef struct
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#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
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#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
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/* Legacy defines */
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#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
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#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
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#define RTC_CR_BCK RTC_CR_BKP
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/******************** Bits definition for RTC_ISR register ******************/
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#define RTC_ISR_RECALPF_Pos (16U)
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#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
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@ -2,8 +2,6 @@
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******************************************************************************
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* @file stm32f302xc.h
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* @author MCD Application Team
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* @version V2.3.1
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* @date 16-December-2016
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* @brief CMSIS STM32F302xC Devices Peripheral Access Layer Header File.
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*
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* This file contains:
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@ -7343,9 +7341,15 @@ typedef struct
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#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
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#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
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#if defined(EXTI_IMR2_MR33)
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#define EXTI_IMR2_IM_Pos (0U)
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#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
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#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
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#else
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#define EXTI_IMR2_IM_Pos (0U)
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#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
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#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
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#endif
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/******************* Bit definition for EXTI_EMR2 ****************************/
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#define EXTI_EMR2_MR32_Pos (0U)
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@ -7366,6 +7370,16 @@ typedef struct
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#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
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#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
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#if defined(EXTI_EMR2_MR33)
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#define EXTI_EMR2_EM_Pos (0U)
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#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
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#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
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#else
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#define EXTI_EMR2_EM_Pos (0U)
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#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
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#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
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#endif
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/****************** Bit definition for EXTI_RTSR2 register ********************/
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#define EXTI_RTSR2_TR32_Pos (0U)
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#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
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@ -9295,9 +9309,9 @@ typedef struct
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#define RTC_CR_COSEL_Pos (19U)
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#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
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#define RTC_CR_COSEL RTC_CR_COSEL_Msk
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#define RTC_CR_BCK_Pos (18U)
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#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
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#define RTC_CR_BCK RTC_CR_BCK_Msk
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#define RTC_CR_BKP_Pos (18U)
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#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
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#define RTC_CR_BKP RTC_CR_BKP_Msk
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#define RTC_CR_SUB1H_Pos (17U)
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#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
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#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
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@ -9347,6 +9361,11 @@ typedef struct
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#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
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#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
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/* Legacy defines */
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#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
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#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
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#define RTC_CR_BCK RTC_CR_BKP
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/******************** Bits definition for RTC_ISR register ******************/
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#define RTC_ISR_RECALPF_Pos (16U)
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#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
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@ -2,8 +2,6 @@
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******************************************************************************
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* @file stm32f302xe.h
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* @author MCD Application Team
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* @version V2.3.1
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* @date 16-December-2016
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* @brief CMSIS STM32F302xE Devices Peripheral Access Layer Header File.
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*
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* This file contains:
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@ -7371,9 +7369,15 @@ typedef struct
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#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
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#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
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#if defined(EXTI_IMR2_MR33)
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#define EXTI_IMR2_IM_Pos (0U)
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#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
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#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
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#else
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#define EXTI_IMR2_IM_Pos (0U)
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#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
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#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
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#endif
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/******************* Bit definition for EXTI_EMR2 ****************************/
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#define EXTI_EMR2_MR32_Pos (0U)
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@ -7394,6 +7398,16 @@ typedef struct
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#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
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#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
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#if defined(EXTI_EMR2_MR33)
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#define EXTI_EMR2_EM_Pos (0U)
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#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
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#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
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#else
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#define EXTI_EMR2_EM_Pos (0U)
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#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
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#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
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#endif
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/****************** Bit definition for EXTI_RTSR2 register ********************/
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#define EXTI_RTSR2_TR32_Pos (0U)
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#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
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|
|
@ -10974,9 +10988,9 @@ typedef struct
|
|||
#define RTC_CR_COSEL_Pos (19U)
|
||||
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
||||
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
||||
#define RTC_CR_BCK_Pos (18U)
|
||||
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BCK RTC_CR_BCK_Msk
|
||||
#define RTC_CR_BKP_Pos (18U)
|
||||
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BKP RTC_CR_BKP_Msk
|
||||
#define RTC_CR_SUB1H_Pos (17U)
|
||||
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
||||
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
||||
|
|
@ -11026,6 +11040,11 @@ typedef struct
|
|||
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
|
||||
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
|
||||
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
|
||||
#define RTC_CR_BCK RTC_CR_BKP
|
||||
|
||||
/******************** Bits definition for RTC_ISR register ******************/
|
||||
#define RTC_ISR_RECALPF_Pos (16U)
|
||||
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32f303x8.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.1
|
||||
* @date 16-December-2016
|
||||
* @brief CMSIS STM32F303x8 Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -7151,9 +7149,19 @@ typedef struct
|
|||
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
|
||||
#endif
|
||||
|
||||
#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
|
||||
#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
|
||||
#else
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
|
||||
#endif
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 ****************************/
|
||||
#define EXTI_EMR2_MR32_Pos (0U)
|
||||
|
|
@ -7172,6 +7180,20 @@ typedef struct
|
|||
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
|
||||
#endif
|
||||
|
||||
#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
|
||||
#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
|
||||
#else
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0x1U << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
|
||||
#endif
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32_Pos (0U)
|
||||
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -7421,21 +7443,6 @@ typedef struct
|
|||
#define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
|
||||
#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/****************** Bit definition for FLASH_WRP2 register ******************/
|
||||
#define OB_WRP2_WRP2_Pos (0U)
|
||||
#define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
|
||||
#define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP2_nWRP2_Pos (8U)
|
||||
#define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
|
||||
#define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/****************** Bit definition for FLASH_WRP3 register ******************/
|
||||
#define OB_WRP3_WRP3_Pos (16U)
|
||||
#define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
|
||||
#define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP3_nWRP3_Pos (24U)
|
||||
#define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
|
||||
#define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -9012,9 +9019,9 @@ typedef struct
|
|||
#define RTC_CR_COSEL_Pos (19U)
|
||||
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
||||
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
||||
#define RTC_CR_BCK_Pos (18U)
|
||||
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BCK RTC_CR_BCK_Msk
|
||||
#define RTC_CR_BKP_Pos (18U)
|
||||
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BKP RTC_CR_BKP_Msk
|
||||
#define RTC_CR_SUB1H_Pos (17U)
|
||||
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
||||
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
||||
|
|
@ -9064,6 +9071,11 @@ typedef struct
|
|||
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
|
||||
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
|
||||
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
|
||||
#define RTC_CR_BCK RTC_CR_BKP
|
||||
|
||||
/******************** Bits definition for RTC_ISR register ******************/
|
||||
#define RTC_ISR_RECALPF_Pos (16U)
|
||||
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
|
||||
|
|
@ -9605,12 +9617,6 @@ typedef struct
|
|||
#define SPI_SR_TXE_Pos (1U)
|
||||
#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
|
||||
#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
|
||||
#define SPI_SR_CHSIDE_Pos (2U)
|
||||
#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
|
||||
#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
|
||||
#define SPI_SR_UDR_Pos (3U)
|
||||
#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
|
||||
#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
|
||||
#define SPI_SR_CRCERR_Pos (4U)
|
||||
#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
|
||||
#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32f303xc.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.1
|
||||
* @date 16-December-2016
|
||||
* @brief CMSIS STM32F303xC Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -7911,6 +7909,10 @@ typedef struct
|
|||
#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
|
||||
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
|
||||
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32_Pos (0U)
|
||||
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -9897,9 +9899,9 @@ typedef struct
|
|||
#define RTC_CR_COSEL_Pos (19U)
|
||||
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
||||
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
||||
#define RTC_CR_BCK_Pos (18U)
|
||||
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BCK RTC_CR_BCK_Msk
|
||||
#define RTC_CR_BKP_Pos (18U)
|
||||
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BKP RTC_CR_BKP_Msk
|
||||
#define RTC_CR_SUB1H_Pos (17U)
|
||||
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
||||
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
||||
|
|
@ -9949,6 +9951,11 @@ typedef struct
|
|||
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
|
||||
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
|
||||
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
|
||||
#define RTC_CR_BCK RTC_CR_BKP
|
||||
|
||||
/******************** Bits definition for RTC_ISR register ******************/
|
||||
#define RTC_ISR_RECALPF_Pos (16U)
|
||||
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32f303xe.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.1
|
||||
* @date 16-December-2016
|
||||
* @brief CMSIS STM32F303xE Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -7917,6 +7915,10 @@ typedef struct
|
|||
#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
|
||||
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
|
||||
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32_Pos (0U)
|
||||
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -11562,9 +11564,9 @@ typedef struct
|
|||
#define RTC_CR_COSEL_Pos (19U)
|
||||
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
||||
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
||||
#define RTC_CR_BCK_Pos (18U)
|
||||
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BCK RTC_CR_BCK_Msk
|
||||
#define RTC_CR_BKP_Pos (18U)
|
||||
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BKP RTC_CR_BKP_Msk
|
||||
#define RTC_CR_SUB1H_Pos (17U)
|
||||
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
||||
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
||||
|
|
@ -11614,6 +11616,11 @@ typedef struct
|
|||
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
|
||||
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
|
||||
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
|
||||
#define RTC_CR_BCK RTC_CR_BKP
|
||||
|
||||
/******************** Bits definition for RTC_ISR register ******************/
|
||||
#define RTC_ISR_RECALPF_Pos (16U)
|
||||
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32f318xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.1
|
||||
* @date 16-December-2016
|
||||
* @brief CMSIS STM32F318xx Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -3540,9 +3538,19 @@ typedef struct
|
|||
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
|
||||
#endif
|
||||
|
||||
#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
|
||||
#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
|
||||
#else
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
|
||||
#endif
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 ****************************/
|
||||
#define EXTI_EMR2_MR32_Pos (0U)
|
||||
|
|
@ -3561,6 +3569,20 @@ typedef struct
|
|||
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
|
||||
#endif
|
||||
|
||||
#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
|
||||
#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
|
||||
#else
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0x1U << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
|
||||
#endif
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32_Pos (0U)
|
||||
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -5415,9 +5437,9 @@ typedef struct
|
|||
#define RTC_CR_COSEL_Pos (19U)
|
||||
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
||||
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
||||
#define RTC_CR_BCK_Pos (18U)
|
||||
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BCK RTC_CR_BCK_Msk
|
||||
#define RTC_CR_BKP_Pos (18U)
|
||||
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BKP RTC_CR_BKP_Msk
|
||||
#define RTC_CR_SUB1H_Pos (17U)
|
||||
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
||||
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
||||
|
|
@ -5467,6 +5489,11 @@ typedef struct
|
|||
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
|
||||
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
|
||||
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
|
||||
#define RTC_CR_BCK RTC_CR_BKP
|
||||
|
||||
/******************** Bits definition for RTC_ISR register ******************/
|
||||
#define RTC_ISR_RECALPF_Pos (16U)
|
||||
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32f328xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.1
|
||||
* @date 16-December-2016
|
||||
* @brief CMSIS STM32F328xx Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -7150,9 +7148,19 @@ typedef struct
|
|||
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
|
||||
#endif
|
||||
|
||||
#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
|
||||
#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
|
||||
#else
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
|
||||
#endif
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 ****************************/
|
||||
#define EXTI_EMR2_MR32_Pos (0U)
|
||||
|
|
@ -7171,6 +7179,20 @@ typedef struct
|
|||
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
|
||||
#endif
|
||||
|
||||
#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
|
||||
#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
|
||||
#else
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0x1U << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
|
||||
#endif
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32_Pos (0U)
|
||||
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -7420,21 +7442,6 @@ typedef struct
|
|||
#define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
|
||||
#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/****************** Bit definition for FLASH_WRP2 register ******************/
|
||||
#define OB_WRP2_WRP2_Pos (0U)
|
||||
#define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
|
||||
#define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP2_nWRP2_Pos (8U)
|
||||
#define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
|
||||
#define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/****************** Bit definition for FLASH_WRP3 register ******************/
|
||||
#define OB_WRP3_WRP3_Pos (16U)
|
||||
#define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
|
||||
#define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP3_nWRP3_Pos (24U)
|
||||
#define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
|
||||
#define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -8985,9 +8992,9 @@ typedef struct
|
|||
#define RTC_CR_COSEL_Pos (19U)
|
||||
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
||||
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
||||
#define RTC_CR_BCK_Pos (18U)
|
||||
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BCK RTC_CR_BCK_Msk
|
||||
#define RTC_CR_BKP_Pos (18U)
|
||||
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BKP RTC_CR_BKP_Msk
|
||||
#define RTC_CR_SUB1H_Pos (17U)
|
||||
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
||||
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
||||
|
|
@ -9037,6 +9044,11 @@ typedef struct
|
|||
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
|
||||
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
|
||||
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
|
||||
#define RTC_CR_BCK RTC_CR_BKP
|
||||
|
||||
/******************** Bits definition for RTC_ISR register ******************/
|
||||
#define RTC_ISR_RECALPF_Pos (16U)
|
||||
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
|
||||
|
|
@ -9578,12 +9590,6 @@ typedef struct
|
|||
#define SPI_SR_TXE_Pos (1U)
|
||||
#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
|
||||
#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
|
||||
#define SPI_SR_CHSIDE_Pos (2U)
|
||||
#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
|
||||
#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
|
||||
#define SPI_SR_UDR_Pos (3U)
|
||||
#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
|
||||
#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
|
||||
#define SPI_SR_CRCERR_Pos (4U)
|
||||
#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
|
||||
#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
|
||||
|
|
@ -9966,15 +9972,6 @@ typedef struct
|
|||
#define SYSCFG_CFGR3_ADC2_DMA_RMP SYSCFG_CFGR3_ADC2_DMA_RMP_Msk /*!< ADC2 DMA remap */
|
||||
#define SYSCFG_CFGR3_ADC2_DMA_RMP_0 (0x1U << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000100 */
|
||||
#define SYSCFG_CFGR3_ADC2_DMA_RMP_1 (0x2U << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000200 */
|
||||
#define SYSCFG_CFGR3_TRIGGER_RMP_Pos (16U)
|
||||
#define SYSCFG_CFGR3_TRIGGER_RMP_Msk (0x3U << SYSCFG_CFGR3_TRIGGER_RMP_Pos) /*!< 0x00030000 */
|
||||
#define SYSCFG_CFGR3_TRIGGER_RMP SYSCFG_CFGR3_TRIGGER_RMP_Msk /*!< Trigger remap mask */
|
||||
#define SYSCFG_CFGR3_DAC1_TRG3_RMP_Pos (16U)
|
||||
#define SYSCFG_CFGR3_DAC1_TRG3_RMP_Msk (0x1U << SYSCFG_CFGR3_DAC1_TRG3_RMP_Pos) /*!< 0x00010000 */
|
||||
#define SYSCFG_CFGR3_DAC1_TRG3_RMP SYSCFG_CFGR3_DAC1_TRG3_RMP_Msk /*!< DAC1 TRG3 remap */
|
||||
#define SYSCFG_CFGR3_DAC1_TRG5_RMP_Pos (17U)
|
||||
#define SYSCFG_CFGR3_DAC1_TRG5_RMP_Msk (0x1U << SYSCFG_CFGR3_DAC1_TRG5_RMP_Pos) /*!< 0x00020000 */
|
||||
#define SYSCFG_CFGR3_DAC1_TRG5_RMP SYSCFG_CFGR3_DAC1_TRG5_RMP_Msk /*!< DAC1 TRG5 remap */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32f334x8.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.1
|
||||
* @date 16-December-2016
|
||||
* @brief CMSIS STM32F334x8 Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -7339,9 +7337,19 @@ typedef struct
|
|||
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
|
||||
#endif
|
||||
|
||||
#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
|
||||
#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
|
||||
#else
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
|
||||
#endif
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 ****************************/
|
||||
#define EXTI_EMR2_MR32_Pos (0U)
|
||||
|
|
@ -7360,6 +7368,20 @@ typedef struct
|
|||
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
|
||||
#endif
|
||||
|
||||
#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
|
||||
#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
|
||||
#else
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0x1U << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
|
||||
#endif
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32_Pos (0U)
|
||||
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -7609,21 +7631,6 @@ typedef struct
|
|||
#define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
|
||||
#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/****************** Bit definition for FLASH_WRP2 register ******************/
|
||||
#define OB_WRP2_WRP2_Pos (0U)
|
||||
#define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
|
||||
#define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP2_nWRP2_Pos (8U)
|
||||
#define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
|
||||
#define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/****************** Bit definition for FLASH_WRP3 register ******************/
|
||||
#define OB_WRP3_WRP3_Pos (16U)
|
||||
#define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
|
||||
#define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP3_nWRP3_Pos (24U)
|
||||
#define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
|
||||
#define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -11958,9 +11965,9 @@ typedef struct
|
|||
#define RTC_CR_COSEL_Pos (19U)
|
||||
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
||||
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
||||
#define RTC_CR_BCK_Pos (18U)
|
||||
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BCK RTC_CR_BCK_Msk
|
||||
#define RTC_CR_BKP_Pos (18U)
|
||||
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BKP RTC_CR_BKP_Msk
|
||||
#define RTC_CR_SUB1H_Pos (17U)
|
||||
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
||||
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
||||
|
|
@ -12010,6 +12017,11 @@ typedef struct
|
|||
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
|
||||
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
|
||||
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
|
||||
#define RTC_CR_BCK RTC_CR_BKP
|
||||
|
||||
/******************** Bits definition for RTC_ISR register ******************/
|
||||
#define RTC_ISR_RECALPF_Pos (16U)
|
||||
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
|
||||
|
|
@ -12551,12 +12563,6 @@ typedef struct
|
|||
#define SPI_SR_TXE_Pos (1U)
|
||||
#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
|
||||
#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
|
||||
#define SPI_SR_CHSIDE_Pos (2U)
|
||||
#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
|
||||
#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
|
||||
#define SPI_SR_UDR_Pos (3U)
|
||||
#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
|
||||
#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
|
||||
#define SPI_SR_CRCERR_Pos (4U)
|
||||
#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
|
||||
#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32f358xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.1
|
||||
* @date 16-December-2016
|
||||
* @brief CMSIS STM32F358xx Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -7863,6 +7861,10 @@ typedef struct
|
|||
#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
|
||||
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
|
||||
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32_Pos (0U)
|
||||
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -9806,9 +9808,9 @@ typedef struct
|
|||
#define RTC_CR_COSEL_Pos (19U)
|
||||
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
||||
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
||||
#define RTC_CR_BCK_Pos (18U)
|
||||
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BCK RTC_CR_BCK_Msk
|
||||
#define RTC_CR_BKP_Pos (18U)
|
||||
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BKP RTC_CR_BKP_Msk
|
||||
#define RTC_CR_SUB1H_Pos (17U)
|
||||
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
||||
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
||||
|
|
@ -9858,6 +9860,11 @@ typedef struct
|
|||
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
|
||||
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
|
||||
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
|
||||
#define RTC_CR_BCK RTC_CR_BKP
|
||||
|
||||
/******************** Bits definition for RTC_ISR register ******************/
|
||||
#define RTC_ISR_RECALPF_Pos (16U)
|
||||
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32f373xc.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.1
|
||||
* @date 16-December-2016
|
||||
* @brief CMSIS STM32F373xC Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -8374,9 +8372,9 @@ typedef struct
|
|||
#define RTC_CR_COSEL_Pos (19U)
|
||||
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
||||
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
||||
#define RTC_CR_BCK_Pos (18U)
|
||||
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BCK RTC_CR_BCK_Msk
|
||||
#define RTC_CR_BKP_Pos (18U)
|
||||
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BKP RTC_CR_BKP_Msk
|
||||
#define RTC_CR_SUB1H_Pos (17U)
|
||||
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
||||
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
||||
|
|
@ -8426,6 +8424,11 @@ typedef struct
|
|||
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
|
||||
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
|
||||
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
|
||||
#define RTC_CR_BCK RTC_CR_BKP
|
||||
|
||||
/******************** Bits definition for RTC_ISR register ******************/
|
||||
#define RTC_ISR_RECALPF_Pos (16U)
|
||||
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32f378xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.1
|
||||
* @date 16-December-2016
|
||||
* @brief CMSIS STM32F378xx Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -8287,9 +8285,9 @@ typedef struct
|
|||
#define RTC_CR_COSEL_Pos (19U)
|
||||
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
||||
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
||||
#define RTC_CR_BCK_Pos (18U)
|
||||
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BCK RTC_CR_BCK_Msk
|
||||
#define RTC_CR_BKP_Pos (18U)
|
||||
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BKP RTC_CR_BKP_Msk
|
||||
#define RTC_CR_SUB1H_Pos (17U)
|
||||
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
||||
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
||||
|
|
@ -8339,6 +8337,11 @@ typedef struct
|
|||
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
|
||||
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
|
||||
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
|
||||
#define RTC_CR_BCK RTC_CR_BKP
|
||||
|
||||
/******************** Bits definition for RTC_ISR register ******************/
|
||||
#define RTC_ISR_RECALPF_Pos (16U)
|
||||
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32f398xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.1
|
||||
* @date 16-December-2016
|
||||
* @brief CMSIS STM32F398xx Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -7867,6 +7865,10 @@ typedef struct
|
|||
#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
|
||||
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
|
||||
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32_Pos (0U)
|
||||
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -11469,9 +11471,9 @@ typedef struct
|
|||
#define RTC_CR_COSEL_Pos (19U)
|
||||
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
||||
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
||||
#define RTC_CR_BCK_Pos (18U)
|
||||
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BCK RTC_CR_BCK_Msk
|
||||
#define RTC_CR_BKP_Pos (18U)
|
||||
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BKP RTC_CR_BKP_Msk
|
||||
#define RTC_CR_SUB1H_Pos (17U)
|
||||
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
||||
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
||||
|
|
@ -11521,6 +11523,11 @@ typedef struct
|
|||
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
|
||||
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
|
||||
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
|
||||
#define RTC_CR_BCK RTC_CR_BKP
|
||||
|
||||
/******************** Bits definition for RTC_ISR register ******************/
|
||||
#define RTC_ISR_RECALPF_Pos (16U)
|
||||
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.1
|
||||
* @date 16-December-2016
|
||||
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
|
|
@ -121,11 +119,11 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V2.3.1
|
||||
* @brief CMSIS Device version number V2.3.2
|
||||
*/
|
||||
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
|
||||
#define __STM32F3_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
|
||||
#define __STM32F3_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
|
||||
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32f3xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.1
|
||||
* @date 16-December-2016
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32h743xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 21-April-2017
|
||||
* @version V1.1.0
|
||||
* @date 31-August-2017
|
||||
* @brief CMSIS STM32H743xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -1846,7 +1846,9 @@ typedef struct
|
|||
uint32_t Reserved30[2]; /*!< Reserved 030h */
|
||||
__IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
|
||||
__IO uint32_t CID; /*!< User ID Register 03Ch */
|
||||
uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
|
||||
__IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
|
||||
__IO uint32_t GHWCFG1; /* User HW config1 044h*/
|
||||
__IO uint32_t GHWCFG2; /* User HW config2 048h*/
|
||||
__IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
|
||||
uint32_t Reserved6; /*!< Reserved 050h */
|
||||
__IO uint32_t GLPMCFG; /*!< LPM Register 054h */
|
||||
|
|
@ -1966,11 +1968,14 @@ typedef struct
|
|||
#define D3_SRAM_BASE ((uint32_t)0x38000000) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
|
||||
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
|
||||
#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
|
||||
#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
|
||||
|
||||
#define FLASH_BANK1_BASE ((uint32_t)0x08000000) /*!< Base address of : Flash Bank1 accessible over AXI */
|
||||
#define FLASH_BANK2_BASE ((uint32_t)0x08100000) /*!< Base address of : Flash Bank2 accessible over AXI */
|
||||
#define FLASH_BANK2_BASE ((uint32_t)0x08100000) /*!< Base address of : Flash Bank2 accessible over AXI */
|
||||
#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
|
||||
|
||||
/* Legacy define */
|
||||
#define FLASH_BASE FLASH_BANK1_BASE
|
||||
|
||||
|
||||
/*!< Peripheral memory map */
|
||||
|
|
@ -13681,9 +13686,6 @@ typedef struct
|
|||
#define PWR_CR3_USB33DEN_Pos (24U)
|
||||
#define PWR_CR3_USB33DEN_Msk (0x1U << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */
|
||||
#define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */
|
||||
#define PWR_CR3_SDEXTRDY_Pos (16U)
|
||||
#define PWR_CR3_SDEXTRDY_Msk (0x1U << PWR_CR3_SDEXTRDY_Pos) /*!< 0x00010000 */
|
||||
#define PWR_CR3_SDEXTRDY PWR_CR3_SDEXTRDY_Msk /*!< Step Down converter External supply ready */
|
||||
#define PWR_CR3_VBRS_Pos (9U)
|
||||
#define PWR_CR3_VBRS_Msk (0x1U << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */
|
||||
#define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */
|
||||
|
|
@ -14713,9 +14715,6 @@ typedef struct
|
|||
#define RCC_AHB3ENR_JPGDECEN_Pos (5U)
|
||||
#define RCC_AHB3ENR_JPGDECEN_Msk (0x1U << RCC_AHB3ENR_JPGDECEN_Pos) /*!< 0x00000020 */
|
||||
#define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk
|
||||
#define RCC_AHB3ENR_FLASHEN_Pos (8U)
|
||||
#define RCC_AHB3ENR_FLASHEN_Msk (0x1U << RCC_AHB3ENR_FLASHEN_Pos) /*!< 0x00000100 */
|
||||
#define RCC_AHB3ENR_FLASHEN RCC_AHB3ENR_FLASHEN_Msk
|
||||
#define RCC_AHB3ENR_FMCEN_Pos (12U)
|
||||
#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00001000 */
|
||||
#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
|
||||
|
|
@ -14774,8 +14773,8 @@ typedef struct
|
|||
#define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
|
||||
#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1U << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */
|
||||
#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
|
||||
#define RCC_AHB2ENR_D2SRAM1EN_Pos (30U)
|
||||
#define RCC_AHB2ENR_D2SRAM1EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM1EN_Pos) /*!< 0x40000000 */
|
||||
#define RCC_AHB2ENR_D2SRAM1EN_Pos (29U)
|
||||
#define RCC_AHB2ENR_D2SRAM1EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM1EN_Pos) /*!< 0x20000000 */
|
||||
#define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_D2SRAM1EN_Msk
|
||||
#define RCC_AHB2ENR_D2SRAM2EN_Pos (30U)
|
||||
#define RCC_AHB2ENR_D2SRAM2EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM2EN_Pos) /*!< 0x40000000 */
|
||||
|
|
@ -23862,49 +23861,6 @@ typedef struct
|
|||
#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
|
||||
#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
|
||||
|
||||
/******************** Bit definition for OTG register ********************/
|
||||
|
||||
#define USB_OTG_CHNUM_Pos (0U)
|
||||
#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
|
||||
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
|
||||
#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
|
||||
#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
|
||||
#define USB_OTG_BCNT_Pos (4U)
|
||||
#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
|
||||
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
|
||||
|
||||
#define USB_OTG_DPID_Pos (15U)
|
||||
#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
|
||||
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
|
||||
#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
|
||||
|
||||
#define USB_OTG_PKTSTS_Pos (17U)
|
||||
#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
|
||||
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
|
||||
#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
|
||||
#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
|
||||
|
||||
#define USB_OTG_EPNUM_Pos (0U)
|
||||
#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
|
||||
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
|
||||
#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
|
||||
#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
|
||||
|
||||
#define USB_OTG_FRMNUM_Pos (21U)
|
||||
#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
|
||||
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
|
||||
#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
|
||||
#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
|
||||
#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
|
||||
#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
|
||||
#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
|
||||
|
|
@ -24584,6 +24540,9 @@ typedef struct
|
|||
#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
|
||||
#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
|
||||
#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
|
||||
#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< OUT Status Phase Received interrupt */
|
||||
#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
|
||||
#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
|
||||
#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32h753xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 21-April-2017
|
||||
* @version V1.1.0
|
||||
* @date 31-August-2017
|
||||
* @brief CMSIS STM32H753xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -913,7 +913,7 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
|
||||
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
|
||||
__IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
|
||||
__IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
|
||||
__IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
|
||||
|
|
@ -1916,7 +1916,9 @@ typedef struct
|
|||
uint32_t Reserved30[2]; /*!< Reserved 030h */
|
||||
__IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
|
||||
__IO uint32_t CID; /*!< User ID Register 03Ch */
|
||||
uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
|
||||
__IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
|
||||
__IO uint32_t GHWCFG1; /* User HW config1 044h*/
|
||||
__IO uint32_t GHWCFG2; /* User HW config2 048h*/
|
||||
__IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
|
||||
uint32_t Reserved6; /*!< Reserved 050h */
|
||||
__IO uint32_t GLPMCFG; /*!< LPM Register 054h */
|
||||
|
|
@ -2036,11 +2038,14 @@ typedef struct
|
|||
#define D3_SRAM_BASE ((uint32_t)0x38000000) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
|
||||
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
|
||||
#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
|
||||
#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
|
||||
|
||||
#define FLASH_BANK1_BASE ((uint32_t)0x08000000) /*!< Base address of : Flash Bank1 accessible over AXI */
|
||||
#define FLASH_BANK2_BASE ((uint32_t)0x08100000) /*!< Base address of : Flash Bank2 accessible over AXI */
|
||||
#define FLASH_BANK2_BASE ((uint32_t)0x08100000) /*!< Base address of : Flash Bank2 accessible over AXI */
|
||||
#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
|
||||
|
||||
/* Legacy define */
|
||||
#define FLASH_BASE FLASH_BANK1_BASE
|
||||
|
||||
|
||||
/*!< Peripheral memory map */
|
||||
|
|
@ -2624,6 +2629,7 @@ typedef struct
|
|||
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
|
||||
#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -4209,6 +4215,7 @@ typedef struct
|
|||
#define VREFBUF_CCR_TRIM_Msk (0x3FU << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
|
||||
#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Flexible Datarate Controller Area Network */
|
||||
|
|
@ -6210,6 +6217,7 @@ typedef struct
|
|||
#define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
|
||||
#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* DCMI */
|
||||
|
|
@ -10403,7 +10411,6 @@ typedef struct
|
|||
#define FLASH_BOOT_ADD0 0x0000FFFFU
|
||||
#define FLASH_BOOT_ADD1 0xFFFF0000U
|
||||
|
||||
|
||||
/******************* Bits definition for FLASH_CRCCR register ********************/
|
||||
#define FLASH_CRCCR_CRC_SECT 0x00000007U
|
||||
#define FLASH_CRCCR_ALL_BANK 0x00000080U
|
||||
|
|
@ -13946,9 +13953,6 @@ typedef struct
|
|||
#define PWR_CR3_USB33DEN_Pos (24U)
|
||||
#define PWR_CR3_USB33DEN_Msk (0x1U << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */
|
||||
#define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */
|
||||
#define PWR_CR3_SDEXTRDY_Pos (16U)
|
||||
#define PWR_CR3_SDEXTRDY_Msk (0x1U << PWR_CR3_SDEXTRDY_Pos) /*!< 0x00010000 */
|
||||
#define PWR_CR3_SDEXTRDY PWR_CR3_SDEXTRDY_Msk /*!< Step Down converter External supply ready */
|
||||
#define PWR_CR3_VBRS_Pos (9U)
|
||||
#define PWR_CR3_VBRS_Msk (0x1U << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */
|
||||
#define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */
|
||||
|
|
@ -14978,9 +14982,6 @@ typedef struct
|
|||
#define RCC_AHB3ENR_JPGDECEN_Pos (5U)
|
||||
#define RCC_AHB3ENR_JPGDECEN_Msk (0x1U << RCC_AHB3ENR_JPGDECEN_Pos) /*!< 0x00000020 */
|
||||
#define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk
|
||||
#define RCC_AHB3ENR_FLASHEN_Pos (8U)
|
||||
#define RCC_AHB3ENR_FLASHEN_Msk (0x1U << RCC_AHB3ENR_FLASHEN_Pos) /*!< 0x00000100 */
|
||||
#define RCC_AHB3ENR_FLASHEN RCC_AHB3ENR_FLASHEN_Msk
|
||||
#define RCC_AHB3ENR_FMCEN_Pos (12U)
|
||||
#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00001000 */
|
||||
#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
|
||||
|
|
@ -15039,8 +15040,8 @@ typedef struct
|
|||
#define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
|
||||
#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1U << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */
|
||||
#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
|
||||
#define RCC_AHB2ENR_D2SRAM1EN_Pos (30U)
|
||||
#define RCC_AHB2ENR_D2SRAM1EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM1EN_Pos) /*!< 0x40000000 */
|
||||
#define RCC_AHB2ENR_D2SRAM1EN_Pos (29U)
|
||||
#define RCC_AHB2ENR_D2SRAM1EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM1EN_Pos) /*!< 0x20000000 */
|
||||
#define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_D2SRAM1EN_Msk
|
||||
#define RCC_AHB2ENR_D2SRAM2EN_Pos (30U)
|
||||
#define RCC_AHB2ENR_D2SRAM2EN_Msk (0x1U << RCC_AHB2ENR_D2SRAM2EN_Pos) /*!< 0x40000000 */
|
||||
|
|
@ -24127,49 +24128,6 @@ typedef struct
|
|||
#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
|
||||
#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
|
||||
|
||||
/******************** Bit definition for OTG register ********************/
|
||||
|
||||
#define USB_OTG_CHNUM_Pos (0U)
|
||||
#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
|
||||
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
|
||||
#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
|
||||
#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
|
||||
#define USB_OTG_BCNT_Pos (4U)
|
||||
#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
|
||||
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
|
||||
|
||||
#define USB_OTG_DPID_Pos (15U)
|
||||
#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
|
||||
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
|
||||
#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
|
||||
|
||||
#define USB_OTG_PKTSTS_Pos (17U)
|
||||
#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
|
||||
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
|
||||
#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
|
||||
#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
|
||||
|
||||
#define USB_OTG_EPNUM_Pos (0U)
|
||||
#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
|
||||
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
|
||||
#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
|
||||
#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
|
||||
|
||||
#define USB_OTG_FRMNUM_Pos (21U)
|
||||
#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
|
||||
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
|
||||
#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
|
||||
#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
|
||||
#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
|
||||
#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
|
||||
#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
|
||||
|
|
@ -24849,6 +24807,9 @@ typedef struct
|
|||
#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
|
||||
#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
|
||||
#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
|
||||
#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< OUT Status Phase Received interrupt */
|
||||
#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
|
||||
#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
|
||||
#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32h7xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 21-April-2017
|
||||
* @version V1.1.0
|
||||
* @date 31-August-2017
|
||||
* @brief CMSIS STM32H7xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
|
|
@ -94,16 +94,16 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V1.0.0
|
||||
* @brief CMSIS Device version number V1.1.0
|
||||
*/
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|
||||
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|
||||
|(__CMSIS_DEVICE_HAL_VERSION_RC))
|
||||
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|
||||
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|
||||
|(__CMSIS_DEVICE_HAL_VERSION_RC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -177,7 +177,7 @@ typedef enum
|
|||
*/
|
||||
|
||||
#if defined (USE_HAL_DRIVER)
|
||||
#include "stm32h7xx_hal_conf.h"
|
||||
#include "stm32h7xx_hal.h"
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32h7xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 21-April-2017
|
||||
* @version V1.1.0
|
||||
* @date 31-August-2017
|
||||
* @brief CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l011xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l011xx devices.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l021xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l021xx devices.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l031xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l031xx devices.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l041xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l041xx devices.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l051xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l051xx devices.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l052xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l052xx devices.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l053xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l053xx devices.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l061xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l061xx devices.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l062xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l062xx devices.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l063xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l063xx devices.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l071xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l071xx devices.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l072xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l072xx devices.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l073xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l073xx devices.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l081xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l081xx devices.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l082xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l082xx devices.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l083xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l083xx devices.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l0xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for STM32L0xx devices.
|
||||
|
|
@ -118,7 +116,7 @@
|
|||
*/
|
||||
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
|
||||
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
|
||||
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
|
||||
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32l0xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 25-November-2016
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l431xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS STM32L431xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -937,7 +935,7 @@ typedef struct
|
|||
/** @addtogroup Peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 256 KB) base address */
|
||||
#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */
|
||||
#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
|
||||
|
|
@ -945,7 +943,6 @@ typedef struct
|
|||
|
||||
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -6775,23 +6772,14 @@ typedef struct
|
|||
#define EXTI_IMR2_IM34_Pos (2U)
|
||||
#define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
|
||||
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
|
||||
#define EXTI_IMR2_IM35_Pos (3U)
|
||||
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
|
||||
#define EXTI_IMR2_IM36_Pos (4U)
|
||||
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
|
||||
#define EXTI_IMR2_IM37_Pos (5U)
|
||||
#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
|
||||
#define EXTI_IMR2_IM38_Pos (6U)
|
||||
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
|
||||
#define EXTI_IMR2_IM39_Pos (7U)
|
||||
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
|
||||
#define EXTI_IMR2_IM_Msk (0x67U << EXTI_IMR2_IM_Pos) /*!< 0x00000067 */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 register ******************/
|
||||
|
|
@ -6804,29 +6792,17 @@ typedef struct
|
|||
#define EXTI_EMR2_EM34_Pos (2U)
|
||||
#define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
|
||||
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
|
||||
#define EXTI_EMR2_EM35_Pos (3U)
|
||||
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
|
||||
#define EXTI_EMR2_EM36_Pos (4U)
|
||||
#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
|
||||
#define EXTI_EMR2_EM37_Pos (5U)
|
||||
#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
|
||||
#define EXTI_EMR2_EM38_Pos (6U)
|
||||
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
|
||||
#define EXTI_EMR2_EM39_Pos (7U)
|
||||
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0x67U << EXTI_EMR2_EM_Pos) /*!< 0x00000067 */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ******************/
|
||||
#define EXTI_RTSR2_RT35_Pos (3U)
|
||||
#define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
|
||||
#define EXTI_RTSR2_RT36_Pos (4U)
|
||||
#define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
|
||||
#define EXTI_RTSR2_RT37_Pos (5U)
|
||||
#define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
|
||||
|
|
@ -6835,12 +6811,6 @@ typedef struct
|
|||
#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR2 register ******************/
|
||||
#define EXTI_FTSR2_FT35_Pos (3U)
|
||||
#define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
|
||||
#define EXTI_FTSR2_FT36_Pos (4U)
|
||||
#define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
|
||||
#define EXTI_FTSR2_FT37_Pos (5U)
|
||||
#define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
|
||||
|
|
@ -6849,12 +6819,6 @@ typedef struct
|
|||
#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER2 register *****************/
|
||||
#define EXTI_SWIER2_SWI35_Pos (3U)
|
||||
#define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
|
||||
#define EXTI_SWIER2_SWI36_Pos (4U)
|
||||
#define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
|
||||
#define EXTI_SWIER2_SWI37_Pos (5U)
|
||||
#define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
|
||||
|
|
@ -6863,12 +6827,6 @@ typedef struct
|
|||
#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR2 register *******************/
|
||||
#define EXTI_PR2_PIF35_Pos (3U)
|
||||
#define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
|
||||
#define EXTI_PR2_PIF36_Pos (4U)
|
||||
#define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
|
||||
#define EXTI_PR2_PIF37_Pos (5U)
|
||||
#define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
|
||||
|
|
@ -8560,9 +8518,9 @@ typedef struct
|
|||
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
#define PWR_CR3_EIWF_Pos (15U)
|
||||
#define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_EIWUL_Pos (15U)
|
||||
#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_APC_Pos (10U)
|
||||
#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
|
||||
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
|
||||
|
|
@ -8588,6 +8546,12 @@ typedef struct
|
|||
#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
|
||||
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
|
||||
|
||||
/* Legacy defines */
|
||||
#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
|
||||
#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWUL
|
||||
|
||||
|
||||
/******************** Bit definition for PWR_CR4 register ********************/
|
||||
#define PWR_CR4_VBRS_Pos (9U)
|
||||
#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
|
||||
|
|
@ -14254,7 +14218,7 @@ typedef struct
|
|||
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
|
||||
#define USART_ISR_NE_Pos (2U)
|
||||
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
|
||||
#define USART_ISR_ORE_Pos (3U)
|
||||
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
|
||||
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
|
||||
|
|
@ -14323,9 +14287,9 @@ typedef struct
|
|||
#define USART_ICR_FECF_Pos (1U)
|
||||
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
|
||||
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
|
||||
#define USART_ICR_NCF_Pos (2U)
|
||||
#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
|
||||
#define USART_ICR_NECF_Pos (2U)
|
||||
#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
|
||||
#define USART_ICR_ORECF_Pos (3U)
|
||||
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
|
||||
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
|
||||
|
|
@ -14357,6 +14321,11 @@ typedef struct
|
|||
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
|
||||
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
|
||||
#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
|
||||
#define USART_ICR_NCF USART_ICR_NECF
|
||||
|
||||
/******************* Bit definition for USART_RDR register ******************/
|
||||
#define USART_RDR_RDR_Pos (0U)
|
||||
#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l432xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS STM32L432xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -933,7 +931,7 @@ typedef struct
|
|||
/** @addtogroup Peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 256 KB) base address */
|
||||
#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */
|
||||
#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
|
||||
|
|
@ -941,7 +939,6 @@ typedef struct
|
|||
|
||||
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -6763,20 +6760,14 @@ typedef struct
|
|||
#define EXTI_IMR2_IM35_Pos (3U)
|
||||
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
|
||||
#define EXTI_IMR2_IM36_Pos (4U)
|
||||
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
|
||||
#define EXTI_IMR2_IM37_Pos (5U)
|
||||
#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
|
||||
#define EXTI_IMR2_IM38_Pos (6U)
|
||||
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
|
||||
#define EXTI_IMR2_IM39_Pos (7U)
|
||||
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
|
||||
#define EXTI_IMR2_IM_Msk (0x6FU << EXTI_IMR2_IM_Pos) /*!< 0x0000006F */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 register ******************/
|
||||
|
|
@ -6792,26 +6783,20 @@ typedef struct
|
|||
#define EXTI_EMR2_EM35_Pos (3U)
|
||||
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
|
||||
#define EXTI_EMR2_EM36_Pos (4U)
|
||||
#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
|
||||
#define EXTI_EMR2_EM37_Pos (5U)
|
||||
#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
|
||||
#define EXTI_EMR2_EM38_Pos (6U)
|
||||
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
|
||||
#define EXTI_EMR2_EM39_Pos (7U)
|
||||
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0x6FU << EXTI_EMR2_EM_Pos) /*!< 0x0000006F */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ******************/
|
||||
#define EXTI_RTSR2_RT35_Pos (3U)
|
||||
#define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
|
||||
#define EXTI_RTSR2_RT36_Pos (4U)
|
||||
#define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
|
||||
#define EXTI_RTSR2_RT37_Pos (5U)
|
||||
#define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
|
||||
|
|
@ -6823,9 +6808,6 @@ typedef struct
|
|||
#define EXTI_FTSR2_FT35_Pos (3U)
|
||||
#define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
|
||||
#define EXTI_FTSR2_FT36_Pos (4U)
|
||||
#define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
|
||||
#define EXTI_FTSR2_FT37_Pos (5U)
|
||||
#define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
|
||||
|
|
@ -6837,9 +6819,6 @@ typedef struct
|
|||
#define EXTI_SWIER2_SWI35_Pos (3U)
|
||||
#define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
|
||||
#define EXTI_SWIER2_SWI36_Pos (4U)
|
||||
#define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
|
||||
#define EXTI_SWIER2_SWI37_Pos (5U)
|
||||
#define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
|
||||
|
|
@ -6851,9 +6830,6 @@ typedef struct
|
|||
#define EXTI_PR2_PIF35_Pos (3U)
|
||||
#define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
|
||||
#define EXTI_PR2_PIF36_Pos (4U)
|
||||
#define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
|
||||
#define EXTI_PR2_PIF37_Pos (5U)
|
||||
#define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
|
||||
|
|
@ -8548,9 +8524,9 @@ typedef struct
|
|||
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
#define PWR_CR3_EIWF_Pos (15U)
|
||||
#define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_EIWUL_Pos (15U)
|
||||
#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_APC_Pos (10U)
|
||||
#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
|
||||
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
|
||||
|
|
@ -8576,6 +8552,12 @@ typedef struct
|
|||
#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
|
||||
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
|
||||
|
||||
/* Legacy defines */
|
||||
#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
|
||||
#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWUL
|
||||
|
||||
|
||||
/******************** Bit definition for PWR_CR4 register ********************/
|
||||
#define PWR_CR4_VBRS_Pos (9U)
|
||||
#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
|
||||
|
|
@ -13405,7 +13387,7 @@ typedef struct
|
|||
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
|
||||
#define USART_ISR_NE_Pos (2U)
|
||||
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
|
||||
#define USART_ISR_ORE_Pos (3U)
|
||||
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
|
||||
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
|
||||
|
|
@ -13474,9 +13456,9 @@ typedef struct
|
|||
#define USART_ICR_FECF_Pos (1U)
|
||||
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
|
||||
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
|
||||
#define USART_ICR_NCF_Pos (2U)
|
||||
#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
|
||||
#define USART_ICR_NECF_Pos (2U)
|
||||
#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
|
||||
#define USART_ICR_ORECF_Pos (3U)
|
||||
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
|
||||
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
|
||||
|
|
@ -13508,6 +13490,11 @@ typedef struct
|
|||
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
|
||||
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
|
||||
#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
|
||||
#define USART_ICR_NCF USART_ICR_NECF
|
||||
|
||||
/******************* Bit definition for USART_RDR register ******************/
|
||||
#define USART_RDR_RDR_Pos (0U)
|
||||
#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
|
||||
|
|
@ -13801,14 +13788,14 @@ typedef struct
|
|||
/* USB Device FS Endpoint registers */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
|
||||
#define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */
|
||||
#define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */
|
||||
#define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */
|
||||
#define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */
|
||||
#define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */
|
||||
#define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */
|
||||
#define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */
|
||||
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
|
||||
#define USB_EP1R (USB_BASE + 0x00000004) /*!< endpoint 1 register address */
|
||||
#define USB_EP2R (USB_BASE + 0x00000008) /*!< endpoint 2 register address */
|
||||
#define USB_EP3R (USB_BASE + 0x0000000C) /*!< endpoint 3 register address */
|
||||
#define USB_EP4R (USB_BASE + 0x00000010) /*!< endpoint 4 register address */
|
||||
#define USB_EP5R (USB_BASE + 0x00000014) /*!< endpoint 5 register address */
|
||||
#define USB_EP6R (USB_BASE + 0x00000018) /*!< endpoint 6 register address */
|
||||
#define USB_EP7R (USB_BASE + 0x0000001C) /*!< endpoint 7 register address */
|
||||
|
||||
/* bit positions */
|
||||
#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l433xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS STM32L433xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -991,7 +989,7 @@ typedef struct
|
|||
/** @addtogroup Peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 256 KB) base address */
|
||||
#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */
|
||||
#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
|
||||
|
|
@ -999,7 +997,6 @@ typedef struct
|
|||
|
||||
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -6837,9 +6834,6 @@ typedef struct
|
|||
#define EXTI_IMR2_IM35_Pos (3U)
|
||||
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
|
||||
#define EXTI_IMR2_IM36_Pos (4U)
|
||||
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
|
||||
#define EXTI_IMR2_IM37_Pos (5U)
|
||||
#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
|
||||
|
|
@ -6850,7 +6844,7 @@ typedef struct
|
|||
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
|
||||
#define EXTI_IMR2_IM_Msk (0xEFU << EXTI_IMR2_IM_Pos) /*!< 0x000000EF */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 register ******************/
|
||||
|
|
@ -6866,9 +6860,6 @@ typedef struct
|
|||
#define EXTI_EMR2_EM35_Pos (3U)
|
||||
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
|
||||
#define EXTI_EMR2_EM36_Pos (4U)
|
||||
#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
|
||||
#define EXTI_EMR2_EM37_Pos (5U)
|
||||
#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
|
||||
|
|
@ -6878,14 +6869,14 @@ typedef struct
|
|||
#define EXTI_EMR2_EM39_Pos (7U)
|
||||
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0xEFU << EXTI_EMR2_EM_Pos) /*!< 0x000000EF */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ******************/
|
||||
#define EXTI_RTSR2_RT35_Pos (3U)
|
||||
#define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
|
||||
#define EXTI_RTSR2_RT36_Pos (4U)
|
||||
#define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
|
||||
#define EXTI_RTSR2_RT37_Pos (5U)
|
||||
#define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
|
||||
|
|
@ -6897,9 +6888,6 @@ typedef struct
|
|||
#define EXTI_FTSR2_FT35_Pos (3U)
|
||||
#define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
|
||||
#define EXTI_FTSR2_FT36_Pos (4U)
|
||||
#define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
|
||||
#define EXTI_FTSR2_FT37_Pos (5U)
|
||||
#define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
|
||||
|
|
@ -6911,9 +6899,6 @@ typedef struct
|
|||
#define EXTI_SWIER2_SWI35_Pos (3U)
|
||||
#define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
|
||||
#define EXTI_SWIER2_SWI36_Pos (4U)
|
||||
#define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
|
||||
#define EXTI_SWIER2_SWI37_Pos (5U)
|
||||
#define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
|
||||
|
|
@ -6925,9 +6910,6 @@ typedef struct
|
|||
#define EXTI_PR2_PIF35_Pos (3U)
|
||||
#define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
|
||||
#define EXTI_PR2_PIF36_Pos (4U)
|
||||
#define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
|
||||
#define EXTI_PR2_PIF37_Pos (5U)
|
||||
#define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
|
||||
|
|
@ -8625,9 +8607,9 @@ typedef struct
|
|||
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
#define PWR_CR3_EIWF_Pos (15U)
|
||||
#define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_EIWUL_Pos (15U)
|
||||
#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_APC_Pos (10U)
|
||||
#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
|
||||
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
|
||||
|
|
@ -8653,6 +8635,12 @@ typedef struct
|
|||
#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
|
||||
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
|
||||
|
||||
/* Legacy defines */
|
||||
#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
|
||||
#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWUL
|
||||
|
||||
|
||||
/******************** Bit definition for PWR_CR4 register ********************/
|
||||
#define PWR_CR4_VBRS_Pos (9U)
|
||||
#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
|
||||
|
|
@ -14459,7 +14447,7 @@ typedef struct
|
|||
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
|
||||
#define USART_ISR_NE_Pos (2U)
|
||||
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
|
||||
#define USART_ISR_ORE_Pos (3U)
|
||||
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
|
||||
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
|
||||
|
|
@ -14528,9 +14516,9 @@ typedef struct
|
|||
#define USART_ICR_FECF_Pos (1U)
|
||||
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
|
||||
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
|
||||
#define USART_ICR_NCF_Pos (2U)
|
||||
#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
|
||||
#define USART_ICR_NECF_Pos (2U)
|
||||
#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
|
||||
#define USART_ICR_ORECF_Pos (3U)
|
||||
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
|
||||
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
|
||||
|
|
@ -14562,6 +14550,11 @@ typedef struct
|
|||
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
|
||||
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
|
||||
#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
|
||||
#define USART_ICR_NCF USART_ICR_NECF
|
||||
|
||||
/******************* Bit definition for USART_RDR register ******************/
|
||||
#define USART_RDR_RDR_Pos (0U)
|
||||
#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
|
||||
|
|
@ -14881,14 +14874,14 @@ typedef struct
|
|||
/* USB Device FS Endpoint registers */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
|
||||
#define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */
|
||||
#define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */
|
||||
#define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */
|
||||
#define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */
|
||||
#define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */
|
||||
#define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */
|
||||
#define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */
|
||||
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
|
||||
#define USB_EP1R (USB_BASE + 0x00000004) /*!< endpoint 1 register address */
|
||||
#define USB_EP2R (USB_BASE + 0x00000008) /*!< endpoint 2 register address */
|
||||
#define USB_EP3R (USB_BASE + 0x0000000C) /*!< endpoint 3 register address */
|
||||
#define USB_EP4R (USB_BASE + 0x00000010) /*!< endpoint 4 register address */
|
||||
#define USB_EP5R (USB_BASE + 0x00000014) /*!< endpoint 5 register address */
|
||||
#define USB_EP6R (USB_BASE + 0x00000018) /*!< endpoint 6 register address */
|
||||
#define USB_EP7R (USB_BASE + 0x0000001C) /*!< endpoint 7 register address */
|
||||
|
||||
/* bit positions */
|
||||
#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l442xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS STM32L442xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -966,7 +964,7 @@ typedef struct
|
|||
/** @addtogroup Peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 256 KB) base address */
|
||||
#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */
|
||||
#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
|
||||
|
|
@ -974,7 +972,6 @@ typedef struct
|
|||
|
||||
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -6979,20 +6976,14 @@ typedef struct
|
|||
#define EXTI_IMR2_IM35_Pos (3U)
|
||||
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
|
||||
#define EXTI_IMR2_IM36_Pos (4U)
|
||||
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
|
||||
#define EXTI_IMR2_IM37_Pos (5U)
|
||||
#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
|
||||
#define EXTI_IMR2_IM38_Pos (6U)
|
||||
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
|
||||
#define EXTI_IMR2_IM39_Pos (7U)
|
||||
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
|
||||
#define EXTI_IMR2_IM_Msk (0x6FU << EXTI_IMR2_IM_Pos) /*!< 0x0000006F */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 register ******************/
|
||||
|
|
@ -7008,26 +6999,20 @@ typedef struct
|
|||
#define EXTI_EMR2_EM35_Pos (3U)
|
||||
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
|
||||
#define EXTI_EMR2_EM36_Pos (4U)
|
||||
#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
|
||||
#define EXTI_EMR2_EM37_Pos (5U)
|
||||
#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
|
||||
#define EXTI_EMR2_EM38_Pos (6U)
|
||||
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
|
||||
#define EXTI_EMR2_EM39_Pos (7U)
|
||||
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0x6FU << EXTI_EMR2_EM_Pos) /*!< 0x0000006F */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ******************/
|
||||
#define EXTI_RTSR2_RT35_Pos (3U)
|
||||
#define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
|
||||
#define EXTI_RTSR2_RT36_Pos (4U)
|
||||
#define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
|
||||
#define EXTI_RTSR2_RT37_Pos (5U)
|
||||
#define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
|
||||
|
|
@ -7039,9 +7024,6 @@ typedef struct
|
|||
#define EXTI_FTSR2_FT35_Pos (3U)
|
||||
#define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
|
||||
#define EXTI_FTSR2_FT36_Pos (4U)
|
||||
#define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
|
||||
#define EXTI_FTSR2_FT37_Pos (5U)
|
||||
#define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
|
||||
|
|
@ -7053,9 +7035,6 @@ typedef struct
|
|||
#define EXTI_SWIER2_SWI35_Pos (3U)
|
||||
#define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
|
||||
#define EXTI_SWIER2_SWI36_Pos (4U)
|
||||
#define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
|
||||
#define EXTI_SWIER2_SWI37_Pos (5U)
|
||||
#define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
|
||||
|
|
@ -7067,9 +7046,6 @@ typedef struct
|
|||
#define EXTI_PR2_PIF35_Pos (3U)
|
||||
#define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
|
||||
#define EXTI_PR2_PIF36_Pos (4U)
|
||||
#define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
|
||||
#define EXTI_PR2_PIF37_Pos (5U)
|
||||
#define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
|
||||
|
|
@ -8764,9 +8740,9 @@ typedef struct
|
|||
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
#define PWR_CR3_EIWF_Pos (15U)
|
||||
#define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_EIWUL_Pos (15U)
|
||||
#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_APC_Pos (10U)
|
||||
#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
|
||||
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
|
||||
|
|
@ -8792,6 +8768,12 @@ typedef struct
|
|||
#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
|
||||
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
|
||||
|
||||
/* Legacy defines */
|
||||
#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
|
||||
#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWUL
|
||||
|
||||
|
||||
/******************** Bit definition for PWR_CR4 register ********************/
|
||||
#define PWR_CR4_VBRS_Pos (9U)
|
||||
#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
|
||||
|
|
@ -13630,7 +13612,7 @@ typedef struct
|
|||
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
|
||||
#define USART_ISR_NE_Pos (2U)
|
||||
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
|
||||
#define USART_ISR_ORE_Pos (3U)
|
||||
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
|
||||
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
|
||||
|
|
@ -13699,9 +13681,9 @@ typedef struct
|
|||
#define USART_ICR_FECF_Pos (1U)
|
||||
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
|
||||
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
|
||||
#define USART_ICR_NCF_Pos (2U)
|
||||
#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
|
||||
#define USART_ICR_NECF_Pos (2U)
|
||||
#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
|
||||
#define USART_ICR_ORECF_Pos (3U)
|
||||
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
|
||||
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
|
||||
|
|
@ -13733,6 +13715,11 @@ typedef struct
|
|||
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
|
||||
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
|
||||
#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
|
||||
#define USART_ICR_NCF USART_ICR_NECF
|
||||
|
||||
/******************* Bit definition for USART_RDR register ******************/
|
||||
#define USART_RDR_RDR_Pos (0U)
|
||||
#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
|
||||
|
|
@ -14026,14 +14013,14 @@ typedef struct
|
|||
/* USB Device FS Endpoint registers */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
|
||||
#define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */
|
||||
#define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */
|
||||
#define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */
|
||||
#define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */
|
||||
#define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */
|
||||
#define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */
|
||||
#define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */
|
||||
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
|
||||
#define USB_EP1R (USB_BASE + 0x00000004) /*!< endpoint 1 register address */
|
||||
#define USB_EP2R (USB_BASE + 0x00000008) /*!< endpoint 2 register address */
|
||||
#define USB_EP3R (USB_BASE + 0x0000000C) /*!< endpoint 3 register address */
|
||||
#define USB_EP4R (USB_BASE + 0x00000010) /*!< endpoint 4 register address */
|
||||
#define USB_EP5R (USB_BASE + 0x00000014) /*!< endpoint 5 register address */
|
||||
#define USB_EP6R (USB_BASE + 0x00000018) /*!< endpoint 6 register address */
|
||||
#define USB_EP7R (USB_BASE + 0x0000001C) /*!< endpoint 7 register address */
|
||||
|
||||
/* bit positions */
|
||||
#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l443xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS STM32L443xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -1024,7 +1022,7 @@ typedef struct
|
|||
/** @addtogroup Peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 256 KB) base address */
|
||||
#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */
|
||||
#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
|
||||
|
|
@ -1032,7 +1030,6 @@ typedef struct
|
|||
|
||||
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -7053,9 +7050,6 @@ typedef struct
|
|||
#define EXTI_IMR2_IM35_Pos (3U)
|
||||
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
|
||||
#define EXTI_IMR2_IM36_Pos (4U)
|
||||
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
|
||||
#define EXTI_IMR2_IM37_Pos (5U)
|
||||
#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
|
||||
|
|
@ -7066,7 +7060,7 @@ typedef struct
|
|||
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
|
||||
#define EXTI_IMR2_IM_Msk (0xEFU << EXTI_IMR2_IM_Pos) /*!< 0x000000EF */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 register ******************/
|
||||
|
|
@ -7082,9 +7076,6 @@ typedef struct
|
|||
#define EXTI_EMR2_EM35_Pos (3U)
|
||||
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
|
||||
#define EXTI_EMR2_EM36_Pos (4U)
|
||||
#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
|
||||
#define EXTI_EMR2_EM37_Pos (5U)
|
||||
#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
|
||||
|
|
@ -7094,14 +7085,14 @@ typedef struct
|
|||
#define EXTI_EMR2_EM39_Pos (7U)
|
||||
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0xEFU << EXTI_EMR2_EM_Pos) /*!< 0x000000EF */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ******************/
|
||||
#define EXTI_RTSR2_RT35_Pos (3U)
|
||||
#define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
|
||||
#define EXTI_RTSR2_RT36_Pos (4U)
|
||||
#define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
|
||||
#define EXTI_RTSR2_RT37_Pos (5U)
|
||||
#define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
|
||||
|
|
@ -7113,9 +7104,6 @@ typedef struct
|
|||
#define EXTI_FTSR2_FT35_Pos (3U)
|
||||
#define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
|
||||
#define EXTI_FTSR2_FT36_Pos (4U)
|
||||
#define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
|
||||
#define EXTI_FTSR2_FT37_Pos (5U)
|
||||
#define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
|
||||
|
|
@ -7127,9 +7115,6 @@ typedef struct
|
|||
#define EXTI_SWIER2_SWI35_Pos (3U)
|
||||
#define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
|
||||
#define EXTI_SWIER2_SWI36_Pos (4U)
|
||||
#define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
|
||||
#define EXTI_SWIER2_SWI37_Pos (5U)
|
||||
#define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
|
||||
|
|
@ -7141,9 +7126,6 @@ typedef struct
|
|||
#define EXTI_PR2_PIF35_Pos (3U)
|
||||
#define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
|
||||
#define EXTI_PR2_PIF36_Pos (4U)
|
||||
#define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
|
||||
#define EXTI_PR2_PIF37_Pos (5U)
|
||||
#define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
|
||||
|
|
@ -8841,9 +8823,9 @@ typedef struct
|
|||
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
#define PWR_CR3_EIWF_Pos (15U)
|
||||
#define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_EIWUL_Pos (15U)
|
||||
#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_APC_Pos (10U)
|
||||
#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
|
||||
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
|
||||
|
|
@ -8869,6 +8851,12 @@ typedef struct
|
|||
#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
|
||||
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
|
||||
|
||||
/* Legacy defines */
|
||||
#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
|
||||
#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWUL
|
||||
|
||||
|
||||
/******************** Bit definition for PWR_CR4 register ********************/
|
||||
#define PWR_CR4_VBRS_Pos (9U)
|
||||
#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
|
||||
|
|
@ -14684,7 +14672,7 @@ typedef struct
|
|||
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
|
||||
#define USART_ISR_NE_Pos (2U)
|
||||
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
|
||||
#define USART_ISR_ORE_Pos (3U)
|
||||
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
|
||||
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
|
||||
|
|
@ -14753,9 +14741,9 @@ typedef struct
|
|||
#define USART_ICR_FECF_Pos (1U)
|
||||
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
|
||||
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
|
||||
#define USART_ICR_NCF_Pos (2U)
|
||||
#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
|
||||
#define USART_ICR_NECF_Pos (2U)
|
||||
#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
|
||||
#define USART_ICR_ORECF_Pos (3U)
|
||||
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
|
||||
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
|
||||
|
|
@ -14787,6 +14775,11 @@ typedef struct
|
|||
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
|
||||
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
|
||||
#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
|
||||
#define USART_ICR_NCF USART_ICR_NECF
|
||||
|
||||
/******************* Bit definition for USART_RDR register ******************/
|
||||
#define USART_RDR_RDR_Pos (0U)
|
||||
#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
|
||||
|
|
@ -15106,14 +15099,14 @@ typedef struct
|
|||
/* USB Device FS Endpoint registers */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
|
||||
#define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */
|
||||
#define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */
|
||||
#define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */
|
||||
#define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */
|
||||
#define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */
|
||||
#define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */
|
||||
#define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */
|
||||
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
|
||||
#define USB_EP1R (USB_BASE + 0x00000004) /*!< endpoint 1 register address */
|
||||
#define USB_EP2R (USB_BASE + 0x00000008) /*!< endpoint 2 register address */
|
||||
#define USB_EP3R (USB_BASE + 0x0000000C) /*!< endpoint 3 register address */
|
||||
#define USB_EP4R (USB_BASE + 0x00000010) /*!< endpoint 4 register address */
|
||||
#define USB_EP5R (USB_BASE + 0x00000014) /*!< endpoint 5 register address */
|
||||
#define USB_EP6R (USB_BASE + 0x00000018) /*!< endpoint 6 register address */
|
||||
#define USB_EP7R (USB_BASE + 0x0000001C) /*!< endpoint 7 register address */
|
||||
|
||||
/* bit positions */
|
||||
#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l451xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS STM32L451xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -957,7 +955,7 @@ typedef struct
|
|||
/** @addtogroup Peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 512 KB) base address */
|
||||
#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 128 KB) base address */
|
||||
#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
|
||||
|
|
@ -965,7 +963,6 @@ typedef struct
|
|||
|
||||
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -7029,29 +7026,17 @@ typedef struct
|
|||
#define EXTI_IMR2_IM33_Pos (1U)
|
||||
#define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
|
||||
#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
|
||||
#define EXTI_IMR2_IM34_Pos (2U)
|
||||
#define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
|
||||
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
|
||||
#define EXTI_IMR2_IM35_Pos (3U)
|
||||
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
|
||||
#define EXTI_IMR2_IM36_Pos (4U)
|
||||
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
|
||||
#define EXTI_IMR2_IM37_Pos (5U)
|
||||
#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
|
||||
#define EXTI_IMR2_IM38_Pos (6U)
|
||||
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
|
||||
#define EXTI_IMR2_IM39_Pos (7U)
|
||||
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
|
||||
#define EXTI_IMR2_IM40_Pos (8U)
|
||||
#define EXTI_IMR2_IM40_Msk (0x1U << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
|
||||
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0x1FFU << EXTI_IMR2_IM_Pos) /*!< 0x000001FF */
|
||||
#define EXTI_IMR2_IM_Msk (0x162U << EXTI_IMR2_IM_Pos) /*!< 0x00000162 */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 register ******************/
|
||||
|
|
@ -7061,35 +7046,20 @@ typedef struct
|
|||
#define EXTI_EMR2_EM33_Pos (1U)
|
||||
#define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
|
||||
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
|
||||
#define EXTI_EMR2_EM34_Pos (2U)
|
||||
#define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
|
||||
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
|
||||
#define EXTI_EMR2_EM35_Pos (3U)
|
||||
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
|
||||
#define EXTI_EMR2_EM36_Pos (4U)
|
||||
#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
|
||||
#define EXTI_EMR2_EM37_Pos (5U)
|
||||
#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
|
||||
#define EXTI_EMR2_EM38_Pos (6U)
|
||||
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
|
||||
#define EXTI_EMR2_EM39_Pos (7U)
|
||||
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
|
||||
#define EXTI_EMR2_IM40_Pos (8U)
|
||||
#define EXTI_EMR2_IM40_Msk (0x1U << EXTI_EMR2_IM40_Pos) /*!< 0x00000100 */
|
||||
#define EXTI_EMR2_IM40 EXTI_EMR2_IM40_Msk /*!< Event Mask on line 40 */
|
||||
#define EXTI_EMR2_EM40_Pos (8U)
|
||||
#define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
|
||||
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0x162U << EXTI_EMR2_EM_Pos) /*!< 0x00000162 */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ******************/
|
||||
#define EXTI_RTSR2_RT35_Pos (3U)
|
||||
#define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
|
||||
#define EXTI_RTSR2_RT36_Pos (4U)
|
||||
#define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
|
||||
#define EXTI_RTSR2_RT37_Pos (5U)
|
||||
#define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
|
||||
|
|
@ -7098,12 +7068,6 @@ typedef struct
|
|||
#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR2 register ******************/
|
||||
#define EXTI_FTSR2_FT35_Pos (3U)
|
||||
#define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
|
||||
#define EXTI_FTSR2_FT36_Pos (4U)
|
||||
#define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
|
||||
#define EXTI_FTSR2_FT37_Pos (5U)
|
||||
#define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
|
||||
|
|
@ -7112,12 +7076,6 @@ typedef struct
|
|||
#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER2 register *****************/
|
||||
#define EXTI_SWIER2_SWI35_Pos (3U)
|
||||
#define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
|
||||
#define EXTI_SWIER2_SWI36_Pos (4U)
|
||||
#define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
|
||||
#define EXTI_SWIER2_SWI37_Pos (5U)
|
||||
#define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
|
||||
|
|
@ -7126,12 +7084,6 @@ typedef struct
|
|||
#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR2 register *******************/
|
||||
#define EXTI_PR2_PIF35_Pos (3U)
|
||||
#define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
|
||||
#define EXTI_PR2_PIF36_Pos (4U)
|
||||
#define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
|
||||
#define EXTI_PR2_PIF37_Pos (5U)
|
||||
#define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
|
||||
|
|
@ -8823,9 +8775,9 @@ typedef struct
|
|||
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
#define PWR_CR3_EIWF_Pos (15U)
|
||||
#define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_EIWUL_Pos (15U)
|
||||
#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_APC_Pos (10U)
|
||||
#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
|
||||
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
|
||||
|
|
@ -8851,6 +8803,12 @@ typedef struct
|
|||
#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
|
||||
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
|
||||
|
||||
/* Legacy defines */
|
||||
#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
|
||||
#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWUL
|
||||
|
||||
|
||||
/******************** Bit definition for PWR_CR4 register ********************/
|
||||
#define PWR_CR4_VBRS_Pos (9U)
|
||||
#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
|
||||
|
|
@ -14619,7 +14577,7 @@ typedef struct
|
|||
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
|
||||
#define USART_ISR_NE_Pos (2U)
|
||||
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
|
||||
#define USART_ISR_ORE_Pos (3U)
|
||||
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
|
||||
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
|
||||
|
|
@ -14688,9 +14646,9 @@ typedef struct
|
|||
#define USART_ICR_FECF_Pos (1U)
|
||||
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
|
||||
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
|
||||
#define USART_ICR_NCF_Pos (2U)
|
||||
#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
|
||||
#define USART_ICR_NECF_Pos (2U)
|
||||
#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
|
||||
#define USART_ICR_ORECF_Pos (3U)
|
||||
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
|
||||
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
|
||||
|
|
@ -14722,6 +14680,11 @@ typedef struct
|
|||
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
|
||||
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
|
||||
#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
|
||||
#define USART_ICR_NCF USART_ICR_NECF
|
||||
|
||||
/******************* Bit definition for USART_RDR register ******************/
|
||||
#define USART_RDR_RDR_Pos (0U)
|
||||
#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l452xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS STM32L452xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -996,7 +994,7 @@ typedef struct
|
|||
/** @addtogroup Peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 512 KB) base address */
|
||||
#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 128 KB) base address */
|
||||
#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
|
||||
|
|
@ -1004,7 +1002,6 @@ typedef struct
|
|||
|
||||
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -7071,29 +7068,20 @@ typedef struct
|
|||
#define EXTI_IMR2_IM33_Pos (1U)
|
||||
#define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
|
||||
#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
|
||||
#define EXTI_IMR2_IM34_Pos (2U)
|
||||
#define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
|
||||
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
|
||||
#define EXTI_IMR2_IM35_Pos (3U)
|
||||
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
|
||||
#define EXTI_IMR2_IM36_Pos (4U)
|
||||
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
|
||||
#define EXTI_IMR2_IM37_Pos (5U)
|
||||
#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
|
||||
#define EXTI_IMR2_IM38_Pos (6U)
|
||||
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
|
||||
#define EXTI_IMR2_IM39_Pos (7U)
|
||||
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
|
||||
#define EXTI_IMR2_IM40_Pos (8U)
|
||||
#define EXTI_IMR2_IM40_Msk (0x1U << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
|
||||
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0x1FFU << EXTI_IMR2_IM_Pos) /*!< 0x000001FF */
|
||||
#define EXTI_IMR2_IM_Msk (0x16BU << EXTI_IMR2_IM_Pos) /*!< 0x0000016B */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 register ******************/
|
||||
|
|
@ -7103,35 +7091,26 @@ typedef struct
|
|||
#define EXTI_EMR2_EM33_Pos (1U)
|
||||
#define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
|
||||
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
|
||||
#define EXTI_EMR2_EM34_Pos (2U)
|
||||
#define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
|
||||
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
|
||||
#define EXTI_EMR2_EM35_Pos (3U)
|
||||
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
|
||||
#define EXTI_EMR2_EM36_Pos (4U)
|
||||
#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
|
||||
#define EXTI_EMR2_EM37_Pos (5U)
|
||||
#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
|
||||
#define EXTI_EMR2_EM38_Pos (6U)
|
||||
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
|
||||
#define EXTI_EMR2_EM39_Pos (7U)
|
||||
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
|
||||
#define EXTI_EMR2_IM40_Pos (8U)
|
||||
#define EXTI_EMR2_IM40_Msk (0x1U << EXTI_EMR2_IM40_Pos) /*!< 0x00000100 */
|
||||
#define EXTI_EMR2_IM40 EXTI_EMR2_IM40_Msk /*!< Event Mask on line 40 */
|
||||
#define EXTI_EMR2_EM40_Pos (8U)
|
||||
#define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
|
||||
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0x16BU << EXTI_EMR2_EM_Pos) /*!< 0x0000016B */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ******************/
|
||||
#define EXTI_RTSR2_RT35_Pos (3U)
|
||||
#define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
|
||||
#define EXTI_RTSR2_RT36_Pos (4U)
|
||||
#define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
|
||||
#define EXTI_RTSR2_RT37_Pos (5U)
|
||||
#define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
|
||||
|
|
@ -7143,9 +7122,6 @@ typedef struct
|
|||
#define EXTI_FTSR2_FT35_Pos (3U)
|
||||
#define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
|
||||
#define EXTI_FTSR2_FT36_Pos (4U)
|
||||
#define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
|
||||
#define EXTI_FTSR2_FT37_Pos (5U)
|
||||
#define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
|
||||
|
|
@ -7157,9 +7133,6 @@ typedef struct
|
|||
#define EXTI_SWIER2_SWI35_Pos (3U)
|
||||
#define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
|
||||
#define EXTI_SWIER2_SWI36_Pos (4U)
|
||||
#define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
|
||||
#define EXTI_SWIER2_SWI37_Pos (5U)
|
||||
#define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
|
||||
|
|
@ -7171,9 +7144,6 @@ typedef struct
|
|||
#define EXTI_PR2_PIF35_Pos (3U)
|
||||
#define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
|
||||
#define EXTI_PR2_PIF36_Pos (4U)
|
||||
#define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
|
||||
#define EXTI_PR2_PIF37_Pos (5U)
|
||||
#define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
|
||||
|
|
@ -8871,9 +8841,9 @@ typedef struct
|
|||
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
#define PWR_CR3_EIWF_Pos (15U)
|
||||
#define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_EIWUL_Pos (15U)
|
||||
#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_APC_Pos (10U)
|
||||
#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
|
||||
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
|
||||
|
|
@ -8899,6 +8869,12 @@ typedef struct
|
|||
#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
|
||||
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
|
||||
|
||||
/* Legacy defines */
|
||||
#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
|
||||
#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWUL
|
||||
|
||||
|
||||
/******************** Bit definition for PWR_CR4 register ********************/
|
||||
#define PWR_CR4_VBRS_Pos (9U)
|
||||
#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
|
||||
|
|
@ -14679,7 +14655,7 @@ typedef struct
|
|||
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
|
||||
#define USART_ISR_NE_Pos (2U)
|
||||
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
|
||||
#define USART_ISR_ORE_Pos (3U)
|
||||
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
|
||||
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
|
||||
|
|
@ -14748,9 +14724,9 @@ typedef struct
|
|||
#define USART_ICR_FECF_Pos (1U)
|
||||
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
|
||||
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
|
||||
#define USART_ICR_NCF_Pos (2U)
|
||||
#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
|
||||
#define USART_ICR_NECF_Pos (2U)
|
||||
#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
|
||||
#define USART_ICR_ORECF_Pos (3U)
|
||||
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
|
||||
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
|
||||
|
|
@ -14782,6 +14758,11 @@ typedef struct
|
|||
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
|
||||
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
|
||||
#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
|
||||
#define USART_ICR_NCF USART_ICR_NECF
|
||||
|
||||
/******************* Bit definition for USART_RDR register ******************/
|
||||
#define USART_RDR_RDR_Pos (0U)
|
||||
#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
|
||||
|
|
@ -14957,14 +14938,14 @@ typedef struct
|
|||
/* USB Device FS Endpoint registers */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
|
||||
#define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */
|
||||
#define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */
|
||||
#define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */
|
||||
#define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */
|
||||
#define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */
|
||||
#define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */
|
||||
#define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */
|
||||
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
|
||||
#define USB_EP1R (USB_BASE + 0x00000004) /*!< endpoint 1 register address */
|
||||
#define USB_EP2R (USB_BASE + 0x00000008) /*!< endpoint 2 register address */
|
||||
#define USB_EP3R (USB_BASE + 0x0000000C) /*!< endpoint 3 register address */
|
||||
#define USB_EP4R (USB_BASE + 0x00000010) /*!< endpoint 4 register address */
|
||||
#define USB_EP5R (USB_BASE + 0x00000014) /*!< endpoint 5 register address */
|
||||
#define USB_EP6R (USB_BASE + 0x00000018) /*!< endpoint 6 register address */
|
||||
#define USB_EP7R (USB_BASE + 0x0000001C) /*!< endpoint 7 register address */
|
||||
|
||||
/* bit positions */
|
||||
#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l462xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS STM32L462xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -1029,7 +1027,7 @@ typedef struct
|
|||
/** @addtogroup Peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 512 KB) base address */
|
||||
#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 128 KB) base address */
|
||||
#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
|
||||
|
|
@ -1037,7 +1035,6 @@ typedef struct
|
|||
|
||||
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -7287,29 +7284,20 @@ typedef struct
|
|||
#define EXTI_IMR2_IM33_Pos (1U)
|
||||
#define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
|
||||
#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
|
||||
#define EXTI_IMR2_IM34_Pos (2U)
|
||||
#define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
|
||||
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
|
||||
#define EXTI_IMR2_IM35_Pos (3U)
|
||||
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
|
||||
#define EXTI_IMR2_IM36_Pos (4U)
|
||||
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
|
||||
#define EXTI_IMR2_IM37_Pos (5U)
|
||||
#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
|
||||
#define EXTI_IMR2_IM38_Pos (6U)
|
||||
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
|
||||
#define EXTI_IMR2_IM39_Pos (7U)
|
||||
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
|
||||
#define EXTI_IMR2_IM40_Pos (8U)
|
||||
#define EXTI_IMR2_IM40_Msk (0x1U << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
|
||||
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0x1FFU << EXTI_IMR2_IM_Pos) /*!< 0x000001FF */
|
||||
#define EXTI_IMR2_IM_Msk (0x16BU << EXTI_IMR2_IM_Pos) /*!< 0x0000016B */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 register ******************/
|
||||
|
|
@ -7319,35 +7307,26 @@ typedef struct
|
|||
#define EXTI_EMR2_EM33_Pos (1U)
|
||||
#define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
|
||||
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
|
||||
#define EXTI_EMR2_EM34_Pos (2U)
|
||||
#define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
|
||||
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
|
||||
#define EXTI_EMR2_EM35_Pos (3U)
|
||||
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
|
||||
#define EXTI_EMR2_EM36_Pos (4U)
|
||||
#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
|
||||
#define EXTI_EMR2_EM37_Pos (5U)
|
||||
#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
|
||||
#define EXTI_EMR2_EM38_Pos (6U)
|
||||
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
|
||||
#define EXTI_EMR2_EM39_Pos (7U)
|
||||
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
|
||||
#define EXTI_EMR2_IM40_Pos (8U)
|
||||
#define EXTI_EMR2_IM40_Msk (0x1U << EXTI_EMR2_IM40_Pos) /*!< 0x00000100 */
|
||||
#define EXTI_EMR2_IM40 EXTI_EMR2_IM40_Msk /*!< Event Mask on line 40 */
|
||||
#define EXTI_EMR2_EM40_Pos (8U)
|
||||
#define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
|
||||
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0x16BU << EXTI_EMR2_EM_Pos) /*!< 0x0000016B */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ******************/
|
||||
#define EXTI_RTSR2_RT35_Pos (3U)
|
||||
#define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
|
||||
#define EXTI_RTSR2_RT36_Pos (4U)
|
||||
#define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
|
||||
#define EXTI_RTSR2_RT37_Pos (5U)
|
||||
#define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
|
||||
|
|
@ -7359,9 +7338,6 @@ typedef struct
|
|||
#define EXTI_FTSR2_FT35_Pos (3U)
|
||||
#define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
|
||||
#define EXTI_FTSR2_FT36_Pos (4U)
|
||||
#define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
|
||||
#define EXTI_FTSR2_FT37_Pos (5U)
|
||||
#define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
|
||||
|
|
@ -7373,9 +7349,6 @@ typedef struct
|
|||
#define EXTI_SWIER2_SWI35_Pos (3U)
|
||||
#define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
|
||||
#define EXTI_SWIER2_SWI36_Pos (4U)
|
||||
#define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
|
||||
#define EXTI_SWIER2_SWI37_Pos (5U)
|
||||
#define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
|
||||
|
|
@ -7387,9 +7360,6 @@ typedef struct
|
|||
#define EXTI_PR2_PIF35_Pos (3U)
|
||||
#define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
|
||||
#define EXTI_PR2_PIF36_Pos (4U)
|
||||
#define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
|
||||
#define EXTI_PR2_PIF37_Pos (5U)
|
||||
#define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
|
||||
|
|
@ -9087,9 +9057,9 @@ typedef struct
|
|||
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
#define PWR_CR3_EIWF_Pos (15U)
|
||||
#define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_EIWUL_Pos (15U)
|
||||
#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_APC_Pos (10U)
|
||||
#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
|
||||
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
|
||||
|
|
@ -9115,6 +9085,12 @@ typedef struct
|
|||
#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
|
||||
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
|
||||
|
||||
/* Legacy defines */
|
||||
#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
|
||||
#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWUL
|
||||
|
||||
|
||||
/******************** Bit definition for PWR_CR4 register ********************/
|
||||
#define PWR_CR4_VBRS_Pos (9U)
|
||||
#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
|
||||
|
|
@ -14904,7 +14880,7 @@ typedef struct
|
|||
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
|
||||
#define USART_ISR_NE_Pos (2U)
|
||||
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
|
||||
#define USART_ISR_ORE_Pos (3U)
|
||||
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
|
||||
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
|
||||
|
|
@ -14973,9 +14949,9 @@ typedef struct
|
|||
#define USART_ICR_FECF_Pos (1U)
|
||||
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
|
||||
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
|
||||
#define USART_ICR_NCF_Pos (2U)
|
||||
#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
|
||||
#define USART_ICR_NECF_Pos (2U)
|
||||
#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
|
||||
#define USART_ICR_ORECF_Pos (3U)
|
||||
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
|
||||
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
|
||||
|
|
@ -15007,6 +14983,11 @@ typedef struct
|
|||
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
|
||||
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
|
||||
#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
|
||||
#define USART_ICR_NCF USART_ICR_NECF
|
||||
|
||||
/******************* Bit definition for USART_RDR register ******************/
|
||||
#define USART_RDR_RDR_Pos (0U)
|
||||
#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
|
||||
|
|
@ -15182,14 +15163,14 @@ typedef struct
|
|||
/* USB Device FS Endpoint registers */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
|
||||
#define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */
|
||||
#define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */
|
||||
#define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */
|
||||
#define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */
|
||||
#define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */
|
||||
#define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */
|
||||
#define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */
|
||||
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
|
||||
#define USB_EP1R (USB_BASE + 0x00000004) /*!< endpoint 1 register address */
|
||||
#define USB_EP2R (USB_BASE + 0x00000008) /*!< endpoint 2 register address */
|
||||
#define USB_EP3R (USB_BASE + 0x0000000C) /*!< endpoint 3 register address */
|
||||
#define USB_EP4R (USB_BASE + 0x00000010) /*!< endpoint 4 register address */
|
||||
#define USB_EP5R (USB_BASE + 0x00000014) /*!< endpoint 5 register address */
|
||||
#define USB_EP6R (USB_BASE + 0x00000018) /*!< endpoint 6 register address */
|
||||
#define USB_EP7R (USB_BASE + 0x0000001C) /*!< endpoint 7 register address */
|
||||
|
||||
/* bit positions */
|
||||
#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l471xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS STM32L471xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -501,7 +499,7 @@ typedef struct
|
|||
__IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
|
||||
__IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
|
||||
__IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
|
||||
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */
|
||||
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */
|
||||
__IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
|
||||
__IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
|
||||
__IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
|
||||
|
|
@ -1021,7 +1019,6 @@ typedef struct
|
|||
#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
|
||||
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -7282,9 +7279,6 @@ typedef struct
|
|||
#define EXTI_IMR2_IM34_Pos (2U)
|
||||
#define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
|
||||
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
|
||||
#define EXTI_IMR2_IM35_Pos (3U)
|
||||
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
|
||||
#define EXTI_IMR2_IM36_Pos (4U)
|
||||
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
|
||||
|
|
@ -7294,11 +7288,8 @@ typedef struct
|
|||
#define EXTI_IMR2_IM38_Pos (6U)
|
||||
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
|
||||
#define EXTI_IMR2_IM39_Pos (7U)
|
||||
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
|
||||
#define EXTI_IMR2_IM_Msk (0x7EU << EXTI_IMR2_IM_Pos) /*!< 0x0000007E */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 register ******************/
|
||||
|
|
@ -7311,9 +7302,6 @@ typedef struct
|
|||
#define EXTI_EMR2_EM34_Pos (2U)
|
||||
#define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
|
||||
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
|
||||
#define EXTI_EMR2_EM35_Pos (3U)
|
||||
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
|
||||
#define EXTI_EMR2_EM36_Pos (4U)
|
||||
#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
|
||||
|
|
@ -7323,14 +7311,11 @@ typedef struct
|
|||
#define EXTI_EMR2_EM38_Pos (6U)
|
||||
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
|
||||
#define EXTI_EMR2_EM39_Pos (7U)
|
||||
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0x7EU << EXTI_EMR2_EM_Pos) /*!< 0x0000007E */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ******************/
|
||||
#define EXTI_RTSR2_RT35_Pos (3U)
|
||||
#define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
|
||||
#define EXTI_RTSR2_RT36_Pos (4U)
|
||||
#define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
|
||||
|
|
@ -7342,9 +7327,6 @@ typedef struct
|
|||
#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR2 register ******************/
|
||||
#define EXTI_FTSR2_FT35_Pos (3U)
|
||||
#define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
|
||||
#define EXTI_FTSR2_FT36_Pos (4U)
|
||||
#define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
|
||||
|
|
@ -7356,9 +7338,6 @@ typedef struct
|
|||
#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER2 register *****************/
|
||||
#define EXTI_SWIER2_SWI35_Pos (3U)
|
||||
#define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
|
||||
#define EXTI_SWIER2_SWI36_Pos (4U)
|
||||
#define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
|
||||
|
|
@ -7370,9 +7349,6 @@ typedef struct
|
|||
#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR2 register *******************/
|
||||
#define EXTI_PR2_PIF35_Pos (3U)
|
||||
#define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
|
||||
#define EXTI_PR2_PIF36_Pos (4U)
|
||||
#define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
|
||||
|
|
@ -9508,9 +9484,9 @@ typedef struct
|
|||
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
#define PWR_CR3_EIWF_Pos (15U)
|
||||
#define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_EIWUL_Pos (15U)
|
||||
#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_APC_Pos (10U)
|
||||
#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
|
||||
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
|
||||
|
|
@ -9536,6 +9512,12 @@ typedef struct
|
|||
#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
|
||||
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
|
||||
|
||||
/* Legacy defines */
|
||||
#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
|
||||
#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWUL
|
||||
|
||||
|
||||
/******************** Bit definition for PWR_CR4 register ********************/
|
||||
#define PWR_CR4_VBRS_Pos (9U)
|
||||
#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
|
||||
|
|
@ -15812,7 +15794,7 @@ typedef struct
|
|||
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
|
||||
#define USART_ISR_NE_Pos (2U)
|
||||
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
|
||||
#define USART_ISR_ORE_Pos (3U)
|
||||
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
|
||||
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
|
||||
|
|
@ -15878,9 +15860,9 @@ typedef struct
|
|||
#define USART_ICR_FECF_Pos (1U)
|
||||
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
|
||||
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
|
||||
#define USART_ICR_NCF_Pos (2U)
|
||||
#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
|
||||
#define USART_ICR_NECF_Pos (2U)
|
||||
#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
|
||||
#define USART_ICR_ORECF_Pos (3U)
|
||||
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
|
||||
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
|
||||
|
|
@ -15909,6 +15891,11 @@ typedef struct
|
|||
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
|
||||
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
|
||||
#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
|
||||
#define USART_ICR_NCF USART_ICR_NECF
|
||||
|
||||
/******************* Bit definition for USART_RDR register ******************/
|
||||
#define USART_RDR_RDR_Pos (0U)
|
||||
#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
|
||||
|
|
@ -16648,7 +16635,8 @@ typedef struct
|
|||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5))
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
/**************** TIM Instances : external trigger input available ************/
|
||||
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l475xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS STM32L475xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -502,7 +500,7 @@ typedef struct
|
|||
__IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
|
||||
__IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
|
||||
__IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
|
||||
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */
|
||||
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */
|
||||
__IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
|
||||
__IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
|
||||
__IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
|
||||
|
|
@ -1140,7 +1138,6 @@ typedef struct
|
|||
#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
|
||||
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -7431,11 +7428,8 @@ typedef struct
|
|||
#define EXTI_IMR2_IM38_Pos (6U)
|
||||
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
|
||||
#define EXTI_IMR2_IM39_Pos (7U)
|
||||
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
|
||||
#define EXTI_IMR2_IM_Msk (0x7FU << EXTI_IMR2_IM_Pos) /*!< 0x0000007F */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 register ******************/
|
||||
|
|
@ -7460,9 +7454,9 @@ typedef struct
|
|||
#define EXTI_EMR2_EM38_Pos (6U)
|
||||
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
|
||||
#define EXTI_EMR2_EM39_Pos (7U)
|
||||
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0x7FU << EXTI_EMR2_EM_Pos) /*!< 0x0000007F */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ******************/
|
||||
#define EXTI_RTSR2_RT35_Pos (3U)
|
||||
|
|
@ -9651,9 +9645,9 @@ typedef struct
|
|||
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
#define PWR_CR3_EIWF_Pos (15U)
|
||||
#define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_EIWUL_Pos (15U)
|
||||
#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_APC_Pos (10U)
|
||||
#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
|
||||
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
|
||||
|
|
@ -9679,6 +9673,12 @@ typedef struct
|
|||
#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
|
||||
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
|
||||
|
||||
/* Legacy defines */
|
||||
#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
|
||||
#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWUL
|
||||
|
||||
|
||||
/******************** Bit definition for PWR_CR4 register ********************/
|
||||
#define PWR_CR4_VBRS_Pos (9U)
|
||||
#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
|
||||
|
|
@ -15958,7 +15958,7 @@ typedef struct
|
|||
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
|
||||
#define USART_ISR_NE_Pos (2U)
|
||||
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
|
||||
#define USART_ISR_ORE_Pos (3U)
|
||||
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
|
||||
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
|
||||
|
|
@ -16024,9 +16024,9 @@ typedef struct
|
|||
#define USART_ICR_FECF_Pos (1U)
|
||||
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
|
||||
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
|
||||
#define USART_ICR_NCF_Pos (2U)
|
||||
#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
|
||||
#define USART_ICR_NECF_Pos (2U)
|
||||
#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
|
||||
#define USART_ICR_ORECF_Pos (3U)
|
||||
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
|
||||
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
|
||||
|
|
@ -16055,6 +16055,11 @@ typedef struct
|
|||
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
|
||||
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
|
||||
#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
|
||||
#define USART_ICR_NCF USART_ICR_NECF
|
||||
|
||||
/******************* Bit definition for USART_RDR register ******************/
|
||||
#define USART_RDR_RDR_Pos (0U)
|
||||
#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
|
||||
|
|
@ -18167,7 +18172,8 @@ typedef struct
|
|||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5))
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
/**************** TIM Instances : external trigger input available ************/
|
||||
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l476xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS STM32L476xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -503,7 +501,7 @@ typedef struct
|
|||
__IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
|
||||
__IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
|
||||
__IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
|
||||
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */
|
||||
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */
|
||||
__IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
|
||||
__IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
|
||||
__IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
|
||||
|
|
@ -1155,7 +1153,6 @@ typedef struct
|
|||
#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
|
||||
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -7480,6 +7477,9 @@ typedef struct
|
|||
#define EXTI_EMR2_EM39_Pos (7U)
|
||||
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0xFFU << EXTI_EMR2_EM_Pos) /*!< 0x000000FF */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ******************/
|
||||
#define EXTI_RTSR2_RT35_Pos (3U)
|
||||
|
|
@ -9668,9 +9668,9 @@ typedef struct
|
|||
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
#define PWR_CR3_EIWF_Pos (15U)
|
||||
#define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_EIWUL_Pos (15U)
|
||||
#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_APC_Pos (10U)
|
||||
#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
|
||||
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
|
||||
|
|
@ -9696,6 +9696,12 @@ typedef struct
|
|||
#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
|
||||
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
|
||||
|
||||
/* Legacy defines */
|
||||
#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
|
||||
#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWUL
|
||||
|
||||
|
||||
/******************** Bit definition for PWR_CR4 register ********************/
|
||||
#define PWR_CR4_VBRS_Pos (9U)
|
||||
#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
|
||||
|
|
@ -16103,7 +16109,7 @@ typedef struct
|
|||
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
|
||||
#define USART_ISR_NE_Pos (2U)
|
||||
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
|
||||
#define USART_ISR_ORE_Pos (3U)
|
||||
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
|
||||
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
|
||||
|
|
@ -16169,9 +16175,9 @@ typedef struct
|
|||
#define USART_ICR_FECF_Pos (1U)
|
||||
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
|
||||
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
|
||||
#define USART_ICR_NCF_Pos (2U)
|
||||
#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
|
||||
#define USART_ICR_NECF_Pos (2U)
|
||||
#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
|
||||
#define USART_ICR_ORECF_Pos (3U)
|
||||
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
|
||||
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
|
||||
|
|
@ -16200,6 +16206,11 @@ typedef struct
|
|||
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
|
||||
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
|
||||
#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
|
||||
#define USART_ICR_NCF USART_ICR_NECF
|
||||
|
||||
/******************* Bit definition for USART_RDR register ******************/
|
||||
#define USART_RDR_RDR_Pos (0U)
|
||||
#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
|
||||
|
|
@ -18315,7 +18326,8 @@ typedef struct
|
|||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5))
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
/**************** TIM Instances : external trigger input available ************/
|
||||
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l485xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS STM32L485xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -503,7 +501,7 @@ typedef struct
|
|||
__IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
|
||||
__IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
|
||||
__IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
|
||||
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */
|
||||
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */
|
||||
__IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
|
||||
__IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
|
||||
__IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
|
||||
|
|
@ -1173,7 +1171,6 @@ typedef struct
|
|||
#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
|
||||
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -7647,11 +7644,8 @@ typedef struct
|
|||
#define EXTI_IMR2_IM38_Pos (6U)
|
||||
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
|
||||
#define EXTI_IMR2_IM39_Pos (7U)
|
||||
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
|
||||
#define EXTI_IMR2_IM_Pos (0U)
|
||||
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
|
||||
#define EXTI_IMR2_IM_Msk (0x7FU << EXTI_IMR2_IM_Pos) /*!< 0x0000007F */
|
||||
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 register ******************/
|
||||
|
|
@ -7676,9 +7670,9 @@ typedef struct
|
|||
#define EXTI_EMR2_EM38_Pos (6U)
|
||||
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
|
||||
#define EXTI_EMR2_EM39_Pos (7U)
|
||||
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0x7FU << EXTI_EMR2_EM_Pos) /*!< 0x0000007F */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ******************/
|
||||
#define EXTI_RTSR2_RT35_Pos (3U)
|
||||
|
|
@ -9867,9 +9861,9 @@ typedef struct
|
|||
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
#define PWR_CR3_EIWF_Pos (15U)
|
||||
#define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_EIWUL_Pos (15U)
|
||||
#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_APC_Pos (10U)
|
||||
#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
|
||||
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
|
||||
|
|
@ -9895,6 +9889,12 @@ typedef struct
|
|||
#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
|
||||
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
|
||||
|
||||
/* Legacy defines */
|
||||
#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
|
||||
#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWUL
|
||||
|
||||
|
||||
/******************** Bit definition for PWR_CR4 register ********************/
|
||||
#define PWR_CR4_VBRS_Pos (9U)
|
||||
#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
|
||||
|
|
@ -16183,7 +16183,7 @@ typedef struct
|
|||
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
|
||||
#define USART_ISR_NE_Pos (2U)
|
||||
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
|
||||
#define USART_ISR_ORE_Pos (3U)
|
||||
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
|
||||
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
|
||||
|
|
@ -16249,9 +16249,9 @@ typedef struct
|
|||
#define USART_ICR_FECF_Pos (1U)
|
||||
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
|
||||
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
|
||||
#define USART_ICR_NCF_Pos (2U)
|
||||
#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
|
||||
#define USART_ICR_NECF_Pos (2U)
|
||||
#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
|
||||
#define USART_ICR_ORECF_Pos (3U)
|
||||
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
|
||||
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
|
||||
|
|
@ -16280,6 +16280,11 @@ typedef struct
|
|||
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
|
||||
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
|
||||
#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
|
||||
#define USART_ICR_NCF USART_ICR_NECF
|
||||
|
||||
/******************* Bit definition for USART_RDR register ******************/
|
||||
#define USART_RDR_RDR_Pos (0U)
|
||||
#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
|
||||
|
|
@ -18395,7 +18400,8 @@ typedef struct
|
|||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5))
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
/**************** TIM Instances : external trigger input available ************/
|
||||
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l486xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS STM32L486xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -504,7 +502,7 @@ typedef struct
|
|||
__IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
|
||||
__IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
|
||||
__IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
|
||||
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */
|
||||
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */
|
||||
__IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
|
||||
__IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
|
||||
__IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
|
||||
|
|
@ -1188,7 +1186,6 @@ typedef struct
|
|||
#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
|
||||
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -7696,6 +7693,9 @@ typedef struct
|
|||
#define EXTI_EMR2_EM39_Pos (7U)
|
||||
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0xFFU << EXTI_EMR2_EM_Pos) /*!< 0x000000FF */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ******************/
|
||||
#define EXTI_RTSR2_RT35_Pos (3U)
|
||||
|
|
@ -9884,9 +9884,9 @@ typedef struct
|
|||
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
#define PWR_CR3_EIWF_Pos (15U)
|
||||
#define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_EIWUL_Pos (15U)
|
||||
#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_APC_Pos (10U)
|
||||
#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
|
||||
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
|
||||
|
|
@ -9912,6 +9912,12 @@ typedef struct
|
|||
#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
|
||||
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
|
||||
|
||||
/* Legacy defines */
|
||||
#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
|
||||
#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWUL
|
||||
|
||||
|
||||
/******************** Bit definition for PWR_CR4 register ********************/
|
||||
#define PWR_CR4_VBRS_Pos (9U)
|
||||
#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
|
||||
|
|
@ -16328,7 +16334,7 @@ typedef struct
|
|||
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
|
||||
#define USART_ISR_NE_Pos (2U)
|
||||
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
|
||||
#define USART_ISR_ORE_Pos (3U)
|
||||
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
|
||||
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
|
||||
|
|
@ -16394,9 +16400,9 @@ typedef struct
|
|||
#define USART_ICR_FECF_Pos (1U)
|
||||
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
|
||||
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
|
||||
#define USART_ICR_NCF_Pos (2U)
|
||||
#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
|
||||
#define USART_ICR_NECF_Pos (2U)
|
||||
#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
|
||||
#define USART_ICR_ORECF_Pos (3U)
|
||||
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
|
||||
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
|
||||
|
|
@ -16425,6 +16431,11 @@ typedef struct
|
|||
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
|
||||
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
|
||||
#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
|
||||
#define USART_ICR_NCF USART_ICR_NECF
|
||||
|
||||
/******************* Bit definition for USART_RDR register ******************/
|
||||
#define USART_RDR_RDR_Pos (0U)
|
||||
#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
|
||||
|
|
@ -18543,7 +18554,8 @@ typedef struct
|
|||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5))
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
/**************** TIM Instances : external trigger input available ************/
|
||||
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l496xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS STM32L496xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -572,7 +570,7 @@ typedef struct
|
|||
__IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
|
||||
__IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
|
||||
__IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
|
||||
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */
|
||||
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */
|
||||
__IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
|
||||
__IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
|
||||
__IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
|
||||
|
|
@ -1228,7 +1226,6 @@ typedef struct
|
|||
#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
|
||||
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -8318,9 +8315,12 @@ typedef struct
|
|||
#define EXTI_EMR2_EM39_Pos (7U)
|
||||
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
|
||||
#define EXTI_EMR2_IM40_Pos (8U)
|
||||
#define EXTI_EMR2_IM40_Msk (0x1U << EXTI_EMR2_IM40_Pos) /*!< 0x00000100 */
|
||||
#define EXTI_EMR2_IM40 EXTI_EMR2_IM40_Msk /*!< Event Mask on line 40 */
|
||||
#define EXTI_EMR2_EM40_Pos (8U)
|
||||
#define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
|
||||
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0x1FFU << EXTI_EMR2_EM_Pos) /*!< 0x000001FF */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ******************/
|
||||
#define EXTI_RTSR2_RT35_Pos (3U)
|
||||
|
|
@ -10454,9 +10454,9 @@ typedef struct
|
|||
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
#define PWR_CR3_EIWF_Pos (15U)
|
||||
#define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_EIWUL_Pos (15U)
|
||||
#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_APC_Pos (10U)
|
||||
#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
|
||||
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
|
||||
|
|
@ -10482,6 +10482,12 @@ typedef struct
|
|||
#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
|
||||
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
|
||||
|
||||
/* Legacy defines */
|
||||
#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
|
||||
#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWUL
|
||||
|
||||
|
||||
/******************** Bit definition for PWR_CR4 register ********************/
|
||||
#define PWR_CR4_VBRS_Pos (9U)
|
||||
#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
|
||||
|
|
@ -17327,7 +17333,7 @@ typedef struct
|
|||
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
|
||||
#define USART_ISR_NE_Pos (2U)
|
||||
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
|
||||
#define USART_ISR_ORE_Pos (3U)
|
||||
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
|
||||
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
|
||||
|
|
@ -17396,9 +17402,9 @@ typedef struct
|
|||
#define USART_ICR_FECF_Pos (1U)
|
||||
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
|
||||
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
|
||||
#define USART_ICR_NCF_Pos (2U)
|
||||
#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
|
||||
#define USART_ICR_NECF_Pos (2U)
|
||||
#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
|
||||
#define USART_ICR_ORECF_Pos (3U)
|
||||
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
|
||||
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
|
||||
|
|
@ -17430,6 +17436,11 @@ typedef struct
|
|||
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
|
||||
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
|
||||
#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
|
||||
#define USART_ICR_NCF USART_ICR_NECF
|
||||
|
||||
/******************* Bit definition for USART_RDR register ******************/
|
||||
#define USART_RDR_RDR_Pos (0U)
|
||||
#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
|
||||
|
|
@ -19561,7 +19572,8 @@ typedef struct
|
|||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5))
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
/**************** TIM Instances : external trigger input available ************/
|
||||
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l4a6xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS STM32L4A6xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -573,7 +571,7 @@ typedef struct
|
|||
__IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
|
||||
__IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
|
||||
__IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
|
||||
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */
|
||||
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */
|
||||
__IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
|
||||
__IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
|
||||
__IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
|
||||
|
|
@ -1286,7 +1284,6 @@ typedef struct
|
|||
#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
|
||||
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -8563,9 +8560,12 @@ typedef struct
|
|||
#define EXTI_EMR2_EM39_Pos (7U)
|
||||
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
|
||||
#define EXTI_EMR2_IM40_Pos (8U)
|
||||
#define EXTI_EMR2_IM40_Msk (0x1U << EXTI_EMR2_IM40_Pos) /*!< 0x00000100 */
|
||||
#define EXTI_EMR2_IM40 EXTI_EMR2_IM40_Msk /*!< Event Mask on line 40 */
|
||||
#define EXTI_EMR2_EM40_Pos (8U)
|
||||
#define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
|
||||
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
|
||||
#define EXTI_EMR2_EM_Pos (0U)
|
||||
#define EXTI_EMR2_EM_Msk (0x1FFU << EXTI_EMR2_EM_Pos) /*!< 0x000001FF */
|
||||
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ******************/
|
||||
#define EXTI_RTSR2_RT35_Pos (3U)
|
||||
|
|
@ -10776,9 +10776,9 @@ typedef struct
|
|||
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
|
||||
|
||||
/******************** Bit definition for PWR_CR3 register ********************/
|
||||
#define PWR_CR3_EIWF_Pos (15U)
|
||||
#define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_EIWUL_Pos (15U)
|
||||
#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
|
||||
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
|
||||
#define PWR_CR3_APC_Pos (10U)
|
||||
#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
|
||||
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
|
||||
|
|
@ -10804,6 +10804,12 @@ typedef struct
|
|||
#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
|
||||
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
|
||||
|
||||
/* Legacy defines */
|
||||
#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
|
||||
#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
|
||||
#define PWR_CR3_EIWF PWR_CR3_EIWUL
|
||||
|
||||
|
||||
/******************** Bit definition for PWR_CR4 register ********************/
|
||||
#define PWR_CR4_VBRS_Pos (9U)
|
||||
#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
|
||||
|
|
@ -17667,7 +17673,7 @@ typedef struct
|
|||
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
|
||||
#define USART_ISR_NE_Pos (2U)
|
||||
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
|
||||
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
|
||||
#define USART_ISR_ORE_Pos (3U)
|
||||
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
|
||||
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
|
||||
|
|
@ -17736,9 +17742,9 @@ typedef struct
|
|||
#define USART_ICR_FECF_Pos (1U)
|
||||
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
|
||||
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
|
||||
#define USART_ICR_NCF_Pos (2U)
|
||||
#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
|
||||
#define USART_ICR_NECF_Pos (2U)
|
||||
#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
|
||||
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
|
||||
#define USART_ICR_ORECF_Pos (3U)
|
||||
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
|
||||
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
|
||||
|
|
@ -17770,6 +17776,11 @@ typedef struct
|
|||
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
|
||||
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
|
||||
#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
|
||||
#define USART_ICR_NCF USART_ICR_NECF
|
||||
|
||||
/******************* Bit definition for USART_RDR register ******************/
|
||||
#define USART_RDR_RDR_Pos (0U)
|
||||
#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
|
||||
|
|
@ -19904,7 +19915,8 @@ typedef struct
|
|||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5))
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
/**************** TIM Instances : external trigger input available ************/
|
||||
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS STM32L4xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
|
|
@ -78,7 +76,8 @@
|
|||
#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
|
||||
!defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
|
||||
!defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
|
||||
!defined (STM32L496xx) && !defined (STM32L4A6xx)
|
||||
!defined (STM32L496xx) && !defined (STM32L4A6xx) && \
|
||||
!defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx)
|
||||
/* #define STM32L431xx */ /*!< STM32L431xx Devices */
|
||||
/* #define STM32L432xx */ /*!< STM32L432xx Devices */
|
||||
/* #define STM32L433xx */ /*!< STM32L433xx Devices */
|
||||
|
|
@ -94,6 +93,12 @@
|
|||
/* #define STM32L486xx */ /*!< STM32L486xx Devices */
|
||||
/* #define STM32L496xx */ /*!< STM32L496xx Devices */
|
||||
/* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */
|
||||
/* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */
|
||||
/* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */
|
||||
/* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */
|
||||
/* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */
|
||||
/* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */
|
||||
/* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */
|
||||
#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
|
|
@ -109,11 +114,11 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V1.3.1
|
||||
* @brief CMSIS Device version number $VERSION$
|
||||
*/
|
||||
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32L4_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
|
||||
#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
|
||||
#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
|
||||
#define __STM32L4_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
|
||||
|
|
@ -158,6 +163,18 @@
|
|||
#include "stm32l496xx.h"
|
||||
#elif defined(STM32L4A6xx)
|
||||
#include "stm32l4a6xx.h"
|
||||
#elif defined(STM32L4R5xx)
|
||||
#include "stm32l4r5xx.h"
|
||||
#elif defined(STM32L4R7xx)
|
||||
#include "stm32l4r7xx.h"
|
||||
#elif defined(STM32L4R9xx)
|
||||
#include "stm32l4r9xx.h"
|
||||
#elif defined(STM32L4S5xx)
|
||||
#include "stm32l4s5xx.h"
|
||||
#elif defined(STM32L4S7xx)
|
||||
#include "stm32l4s7xx.h"
|
||||
#elif defined(STM32L4S9xx)
|
||||
#include "stm32l4s9xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32l4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
Loading…
Reference in New Issue